[llvm] Opt-in flag for X86DiscriminateMemOps
Summary:
Currently, if an instruction with a memory operand has no debug information,
X86DiscriminateMemOps will generate one based on the first line of the
enclosing function, or the last seen debug info.
This may cause confusion in certain debugging scenarios. The long term
approach would be to use the line number '0' in such cases, however, that
brings in challenges: the base discriminator value range is limited
(4096 values).
For the short term, adding an opt-in flag for this feature.
See bug 40319 (https://bugs.llvm.org/show_bug.cgi?id=40319)
Reviewers: dblaikie, jmorse, gbedwell
Reviewed By: dblaikie
Subscribers: aprantl, eraman, hiraditya
Differential Revision: https://reviews.llvm.org/D57257
llvm-svn: 352246
2019-01-26 05:49:54 +08:00
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; RUN: llc < %s -x86-discriminate-memops -prefetch-hints-file=%S/insert-prefetch-inline.afdo | FileCheck %s
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2018-11-30 09:01:52 +08:00
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;
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; Verify we can insert prefetch instructions in code belonging to inlined
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; functions.
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;
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; ModuleID = 'test.cc'
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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; Function Attrs: norecurse nounwind readonly uwtable
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define dso_local i32 @sum(i32* nocapture readonly %arr, i32 %pos1, i32 %pos2) local_unnamed_addr #0 !dbg !7 {
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entry:
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%idxprom = sext i32 %pos1 to i64, !dbg !10
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%arrayidx = getelementptr inbounds i32, i32* %arr, i64 %idxprom, !dbg !10
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%0 = load i32, i32* %arrayidx, align 4, !dbg !10, !tbaa !11
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%idxprom1 = sext i32 %pos2 to i64, !dbg !15
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%arrayidx2 = getelementptr inbounds i32, i32* %arr, i64 %idxprom1, !dbg !15
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%1 = load i32, i32* %arrayidx2, align 4, !dbg !15, !tbaa !11
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%add = add nsw i32 %1, %0, !dbg !16
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ret i32 %add, !dbg !17
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}
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; "caller" inlines "sum". The associated .afdo file references instructions
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; in "caller" that came from "sum"'s inlining.
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;
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; Function Attrs: norecurse nounwind readonly uwtable
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define dso_local i32 @caller(i32* nocapture readonly %arr) local_unnamed_addr #0 !dbg !18 {
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entry:
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%0 = load i32, i32* %arr, align 4, !dbg !19, !tbaa !11
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%arrayidx2.i = getelementptr inbounds i32, i32* %arr, i64 2, !dbg !21
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%1 = load i32, i32* %arrayidx2.i, align 4, !dbg !21, !tbaa !11
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%add.i = add nsw i32 %1, %0, !dbg !22
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ret i32 %add.i, !dbg !23
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}
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attributes #0 = { "target-cpu"="x86-64" }
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!llvm.dbg.cu = !{!0}
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!llvm.module.flags = !{!3, !4, !5}
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!llvm.ident = !{!6}
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!0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !1, producer: "clang version 7.0.0 (trunk 324940) (llvm/trunk 324941)", isOptimized: true, runtimeVersion: 0, emissionKind: LineTablesOnly, enums: !2, debugInfoForProfiling: true)
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!1 = !DIFile(filename: "test.cc", directory: "/tmp")
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!2 = !{}
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!3 = !{i32 2, !"Dwarf Version", i32 4}
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!4 = !{i32 2, !"Debug Info Version", i32 3}
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!5 = !{i32 1, !"wchar_size", i32 4}
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!6 = !{!"clang version 7.0.0 (trunk 324940) (llvm/trunk 324941)"}
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!7 = distinct !DISubprogram(name: "sum", linkageName: "sum", scope: !8, file: !8, line: 3, type: !9, isLocal: false, isDefinition: true, scopeLine: 3, flags: DIFlagPrototyped, isOptimized: true, unit: !0)
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!8 = !DIFile(filename: "./test.h", directory: "/tmp")
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!9 = !DISubroutineType(types: !2)
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!10 = !DILocation(line: 6, column: 10, scope: !7)
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!11 = !{!12, !12, i64 0}
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!12 = !{!"int", !13, i64 0}
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!13 = !{!"omnipotent char", !14, i64 0}
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!14 = !{!"Simple C++ TBAA"}
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!15 = !DILocation(line: 6, column: 22, scope: !7)
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!16 = !DILocation(line: 6, column: 20, scope: !7)
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!17 = !DILocation(line: 6, column: 3, scope: !7)
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!18 = distinct !DISubprogram(name: "caller", linkageName: "caller", scope: !1, file: !1, line: 4, type: !9, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: true, unit: !0)
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!19 = !DILocation(line: 6, column: 10, scope: !7, inlinedAt: !20)
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!20 = distinct !DILocation(line: 6, column: 10, scope: !18)
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!21 = !DILocation(line: 6, column: 22, scope: !7, inlinedAt: !20)
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!22 = !DILocation(line: 6, column: 20, scope: !7, inlinedAt: !20)
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!23 = !DILocation(line: 6, column: 3, scope: !18)
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; CHECK-LABEL: caller:
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; CHECK-LABEL: # %bb.0:
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; CHECK-NEXT: .loc 1 6 22 prologue_end
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; CHECK-NEXT: prefetchnta 23464(%rdi)
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; CHECK-NEXT: movl 8(%rdi), %eax
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; CHECK-NEXT: .loc 1 6 20 is_stmt 0 discriminator 2
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; CHECK-NEXT: prefetchnta 8764(%rdi)
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; CHECK-NEXT: prefetchnta 64(%rdi)
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; CHECK-NEXT: addl (%rdi), %eax
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