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llvm-project/llvm/test/CodeGen/X86/extract-concat.ll

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[X86] Autogenerate complete checks. NFC llvm-svn: 346188
2018-11-06 08:31:27 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
Teach DAG combine to fold (extract_subvec (concat v1, ..) i) to v_i - If the extracted vector has the same type of all vectored being concatenated together, it should be simplified directly into v_i, where i is the index of the element being extracted. llvm-svn: 166125
2012-10-18 04:48:33 +08:00
; RUN: llc < %s -mcpu=corei7 -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
define void @foo(<4 x float> %in, <4 x i8>* %out) {
[X86] Autogenerate complete checks. NFC llvm-svn: 346188
2018-11-06 08:31:27 +08:00
; CHECK-LABEL: foo:
; CHECK: # %bb.0:
; CHECK-NEXT: cvttps2dq %xmm0, %xmm0
; CHECK-NEXT: movl $255, %eax
; CHECK-NEXT: pinsrd $3, %eax, %xmm0
; CHECK-NEXT: pshufb {{.*#+}} xmm0 = xmm0[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
; CHECK-NEXT: movd %xmm0, (%rdi)
; CHECK-NEXT: retq
Disable extract-concat test case temporarily llvm-svn: 166141
2012-10-18 07:08:19 +08:00
%t0 = fptosi <4 x float> %in to <4 x i32>
Teach DAG combine to fold (extract_subvec (concat v1, ..) i) to v_i - If the extracted vector has the same type of all vectored being concatenated together, it should be simplified directly into v_i, where i is the index of the element being extracted. llvm-svn: 166125
2012-10-18 04:48:33 +08:00
%t1 = trunc <4 x i32> %t0 to <4 x i16>
%t2 = shufflevector <4 x i16> %t1, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
%t3 = trunc <8 x i16> %t2 to <8 x i8>
%t4 = shufflevector <8 x i8> %t3, <8 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%t5 = insertelement <4 x i8> %t4, i8 -1, i32 3
store <4 x i8> %t5, <4 x i8>* %out
ret void
}