forked from OSchip/llvm-project
65 lines
2.9 KiB
LLVM
65 lines
2.9 KiB
LLVM
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; RUN: llc -march=hexagon -O3 < %s | FileCheck %s
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; CHECK-NOT: vsplat
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; CHECK: call f2
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; CHECK: v{{[0-9]+}} = vsplat
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; CHECK: v{{[0-9]+}} = vsplat
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; CHECK: v{{[0-9]+}} = vsplat
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; CHECK: v{{[0-9]+}} = vsplat
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target triple = "hexagon"
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@g0 = common global [2 x <32 x i32>] zeroinitializer, align 128
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@g1 = common global <32 x i32> zeroinitializer, align 128
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@g2 = common global [2 x <16 x i32>] zeroinitializer, align 64
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; Function Attrs: nounwind
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define i32 @f0() #0 {
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b0:
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tail call void @f1() #2
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%v0 = tail call i32 @f2(i8 zeroext 0) #2
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%v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1) #2
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store <16 x i32> %v1, <16 x i32>* getelementptr inbounds ([2 x <16 x i32>], [2 x <16 x i32>]* @g2, i32 0, i32 0), align 64, !tbaa !0
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%v2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2) #2
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store <16 x i32> %v2, <16 x i32>* getelementptr inbounds ([2 x <16 x i32>], [2 x <16 x i32>]* @g2, i32 0, i32 1), align 64, !tbaa !0
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%v3 = tail call <32 x i32> @llvm.hexagon.V6.vaddubh(<16 x i32> %v1, <16 x i32> %v2) #2
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store <32 x i32> %v3, <32 x i32>* getelementptr inbounds ([2 x <32 x i32>], [2 x <32 x i32>]* @g0, i32 0, i32 0), align 128, !tbaa !0
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store <32 x i32> %v3, <32 x i32>* getelementptr inbounds ([2 x <32 x i32>], [2 x <32 x i32>]* @g0, i32 0, i32 1), align 128, !tbaa !0
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%v4 = tail call <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32> %v3, <32 x i32> %v3, i32 -2147483648)
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store <32 x i32> %v4, <32 x i32>* @g1, align 128, !tbaa !0
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ret i32 0
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}
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declare void @f1() #0
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declare i32 @f2(i8 zeroext) #0
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vdmpybus.dv.acc(<32 x i32>, <32 x i32>, i32) #1
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; Function Attrs: nounwind
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define void @f3() #0 {
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b0:
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%v0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)
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store <16 x i32> %v0, <16 x i32>* getelementptr inbounds ([2 x <16 x i32>], [2 x <16 x i32>]* @g2, i32 0, i32 0), align 64, !tbaa !0
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%v1 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2)
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store <16 x i32> %v1, <16 x i32>* getelementptr inbounds ([2 x <16 x i32>], [2 x <16 x i32>]* @g2, i32 0, i32 1), align 64, !tbaa !0
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%v2 = tail call <32 x i32> @llvm.hexagon.V6.vaddubh(<16 x i32> %v0, <16 x i32> %v1)
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store <32 x i32> %v2, <32 x i32>* getelementptr inbounds ([2 x <32 x i32>], [2 x <32 x i32>]* @g0, i32 0, i32 0), align 128, !tbaa !0
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store <32 x i32> %v2, <32 x i32>* getelementptr inbounds ([2 x <32 x i32>], [2 x <32 x i32>]* @g0, i32 0, i32 1), align 128, !tbaa !0
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
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; Function Attrs: nounwind readnone
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declare <32 x i32> @llvm.hexagon.V6.vaddubh(<16 x i32>, <16 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind }
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!0 = !{!1, !1, i64 0}
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!1 = !{!"omnipotent char", !2, i64 0}
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!2 = !{!"Simple C/C++ TBAA"}
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