maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/Hexagon/combine.ll

18 lines
495 B
LLVM
Raw Normal View History

[Hexagon] Generate COPY/REG_SEQUENCE more aggressively for vectors llvm-svn: 277626
2016-08-04 02:35:48 +08:00
; RUN: llc -march=hexagon -mcpu=hexagonv5 -disable-hsdr -hexagon-bit=0 < %s | FileCheck %s
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
; CHECK: combine(r{{[0-9]+}}, r{{[0-9]+}})
@j = external global i32
@k = external global i64
define void @foo() nounwind {
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i32, i32* @j, align 4
%1 = load i64, i64* @k, align 8
Hexagon backend support llvm-svn: 146412
2011-12-13 05:14:40 +08:00
%conv = trunc i64 %1 to i32
%2 = call i64 @llvm.hexagon.A2.combinew(i32 %0, i32 %conv)
store i64 %2, i64* @k, align 8
ret void
}
declare i64 @llvm.hexagon.A2.combinew(i32, i32) nounwind readnone