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llvm-project/llvm/test/CodeGen/AArch64/free-zext.ll

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AArch64/ARM64: enable more AArch64 tests on ARM64. No code changes for this bunch, just some test rejigs. llvm-svn: 206291
2014-04-15 22:00:29 +08:00
; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 | FileCheck %s
[AArch64] Implement the isZExtFree APIs. llvm-svn: 205926
2014-04-10 04:51:21 +08:00
define i64 @test_free_zext(i8* %a, i16* %b) {
[DAGCombiner] Improve zextload optimization. Summary: Don't fold (zext (and (load x), cst)) -> (and (zextload x), (zext cst)) if (and (load x) cst) will match as a zextload already and has additional users. For example, the following IR: %load = load i32, i32* %ptr, align 8 %load16 = and i32 %load, 65535 %load64 = zext i32 %load16 to i64 store i32 %load16, i32* %dst1, align 4 store i64 %load64, i64* %dst2, align 8 used to produce the following aarch64 code: ldr w8, [x0] and w9, w8, #0xffff and x8, x8, #0xffff str w9, [x1] str x8, [x2] but with this change produces the following aarch64 code: ldrh w8, [x0] str w8, [x1] str x8, [x2] Reviewers: resistor, mcrosier Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14340 llvm-svn: 252789
2015-11-12 03:42:52 +08:00
; CHECK-LABEL: test_free_zext:
AArch64/ARM64: enable more AArch64 tests on ARM64. No code changes for this bunch, just some test rejigs. llvm-svn: 206291
2014-04-15 22:00:29 +08:00
; CHECK-DAG: ldrb w[[A:[0-9]+]], [x0]
; CHECK: ldrh w[[B:[0-9]+]], [x1]
; CHECK: add x0, x[[B]], x[[A]]
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%1 = load i8, i8* %a, align 1
[AArch64] Implement the isZExtFree APIs. llvm-svn: 205926
2014-04-10 04:51:21 +08:00
%conv = zext i8 %1 to i64
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%2 = load i16, i16* %b, align 2
[AArch64] Implement the isZExtFree APIs. llvm-svn: 205926
2014-04-10 04:51:21 +08:00
%conv1 = zext i16 %2 to i64
%add = add nsw i64 %conv1, %conv
ret i64 %add
}
[DAGCombiner] Improve zextload optimization. Summary: Don't fold (zext (and (load x), cst)) -> (and (zextload x), (zext cst)) if (and (load x) cst) will match as a zextload already and has additional users. For example, the following IR: %load = load i32, i32* %ptr, align 8 %load16 = and i32 %load, 65535 %load64 = zext i32 %load16 to i64 store i32 %load16, i32* %dst1, align 4 store i64 %load64, i64* %dst2, align 8 used to produce the following aarch64 code: ldr w8, [x0] and w9, w8, #0xffff and x8, x8, #0xffff str w9, [x1] str x8, [x2] but with this change produces the following aarch64 code: ldrh w8, [x0] str w8, [x1] str x8, [x2] Reviewers: resistor, mcrosier Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14340 llvm-svn: 252789
2015-11-12 03:42:52 +08:00
define void @test_free_zext2(i32* %ptr, i32* %dst1, i64* %dst2) {
; CHECK-LABEL: test_free_zext2:
; CHECK: ldrh w[[A:[0-9]+]], [x0]
; CHECK-NOT: and x
; CHECK: str w[[A]], [x1]
; CHECK: str x[[A]], [x2]
%load = load i32, i32* %ptr, align 8
%load16 = and i32 %load, 65535
%load64 = zext i32 %load16 to i64
store i32 %load16, i32* %dst1, align 4
store i64 %load64, i64* %dst2, align 8
ret void
}
[CodeGenPrepare] Create more extloads and fewer ands Summary: Add and instructions immediately after loads that only have their low bits used, assuming that the (and (load x) c) will be matched as a extload and the ands/truncs fed by the extload will be removed by isel. Reviewers: mcrosier, qcolombet, ab Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D14584 llvm-svn: 253722
2015-11-21 06:34:39 +08:00
; Test for CodeGenPrepare::optimizeLoadExt(): simple case: two loads
; feeding a phi that zext's each loaded value.
define i32 @test_free_zext3(i32* %ptr, i32* %ptr2, i32* %dst, i32 %c) {
; CHECK-LABEL: test_free_zext3:
bb1:
; CHECK: ldrh [[REG:w[0-9]+]]
; CHECK-NOT: and {{w[0-9]+}}, [[REG]], #0xffff
%tmp1 = load i32, i32* %ptr, align 4
%cmp = icmp ne i32 %c, 0
br i1 %cmp, label %bb2, label %bb3
bb2:
; CHECK: ldrh [[REG2:w[0-9]+]]
; CHECK-NOT: and {{w[0-9]+}}, [[REG2]], #0xffff
%tmp2 = load i32, i32* %ptr2, align 4
br label %bb3
bb3:
%tmp3 = phi i32 [ %tmp1, %bb1 ], [ %tmp2, %bb2 ]
; CHECK-NOT: and {{w[0-9]+}}, {{w[0-9]+}}, #0xffff
%tmpand = and i32 %tmp3, 65535
ret i32 %tmpand
}
; Test for CodeGenPrepare::optimizeLoadExt(): check case of zext-able
; load feeding a phi in the same block.
define void @test_free_zext4(i32* %ptr, i32* %ptr2, i32* %dst) {
; CHECK-LABEL: test_free_zext4:
; CHECK: ldrh [[REG:w[0-9]+]]
; TODO: fix isel to remove final and XCHECK-NOT: and {{w[0-9]+}}, {{w[0-9]+}}, #0xffff
; CHECK: ldrh [[REG:w[0-9]+]]
bb1:
%load1 = load i32, i32* %ptr, align 4
br label %loop
loop:
%phi = phi i32 [ %load1, %bb1 ], [ %load2, %loop ]
%and = and i32 %phi, 65535
store i32 %and, i32* %dst, align 4
%load2 = load i32, i32* %ptr2, align 4
%cmp = icmp ne i32 %and, 0
br i1 %cmp, label %loop, label %end
end:
ret void
}