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llvm-project/llvm/test/Object/AMDGPU/elf64-relocs.yaml

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[yaml2obj] Remove --format option in favor of YAML tags Summary: Our YAML library's handling of tags isn't perfect, but it is good enough to get rid of the need for the --format argument to yaml2obj. This patch does exactly that. Instead of requiring --format, it infers the format based on the tags found in the object file. The supported tags are: !ELF !COFF !mach-o !fat-mach-o I have a corresponding patch that is quite large that fixes up all the in-tree test cases. Reviewers: rafael, Bigcheese, compnerd, silvas Subscribers: compnerd, llvm-commits Differential Revision: http://reviews.llvm.org/D21711 llvm-svn: 273915
2016-06-28 03:53:53 +08:00
# RUN: yaml2obj %s > %t
Support/ELF: Add AMDGPU relocation definitions to match documentation Reviewers: arsenm, kzhuravl, rafael Subscribers: llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21443 llvm-svn: 273066
2016-06-18 06:38:08 +08:00
# RUN: llvm-readobj -r %t | FileCheck %s
# CHECK: Relocations [
# CHECK: Section (2) .rela.text {
[Support/ELF/AMDGPU] Add 32-bit lo/hi got and pc relative relocations Added relocation names: - R_AMDGPU_GOTPCREL32_LO - R_AMDGPU_GOTPCREL32_HI - R_AMDGPU_REL32_LO - R_AMDGPU_REL32_HI AMDGPU isa only supports 32-bit immediates. In order to access 64-bit address we need to generate 32-bit lo/hi relocations, and do the right math (separate patch). Currently we only generate one 32 bit relocation for lower bits for each access, losing higher bits. Hence we need relocations listed above. Differential Revision: https://reviews.llvm.org/D25546 llvm-svn: 284191
2016-10-14 12:03:49 +08:00
# CHECK: 0x0 R_AMDGPU_NONE - 0x0
# CHECK: 0x2 R_AMDGPU_ABS32_LO - 0x0
# CHECK: 0x4 R_AMDGPU_ABS32_HI - 0x0
# CHECK: 0x6 R_AMDGPU_ABS64 - 0x0
# CHECK: 0x8 R_AMDGPU_REL32 - 0x0
# CHECK: 0x10 R_AMDGPU_REL64 - 0x0
# CHECK: 0x12 R_AMDGPU_ABS32 - 0x0
# CHECK: 0x14 R_AMDGPU_GOTPCREL - 0x0
# CHECK: 0x16 R_AMDGPU_GOTPCREL32_LO - 0x0
# CHECK: 0x18 R_AMDGPU_GOTPCREL32_HI - 0x0
# CHECK: 0x20 R_AMDGPU_REL32_LO - 0x0
# CHECK: 0x22 R_AMDGPU_REL32_HI - 0x0
Add base relative relocation record that can be used for the following case (OpenCL example): static __global int Var = 0; __global int* Ptr[] = {&Var}; ... In this case Var is a non premptable symbol and so its address can be used as the value of Ptr, with a base relative relocation that will add the delta between the ELF address and the actual load address. Such relocations do not require a symbol. Differential Revision: https://reviews.llvm.org/D38909 llvm-svn: 315935
2017-10-17 04:44:29 +08:00
# CHECK: 0x24 R_AMDGPU_RELATIVE64 - 0x0
Support/ELF: Add AMDGPU relocation definitions to match documentation Reviewers: arsenm, kzhuravl, rafael Subscribers: llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21443 llvm-svn: 273066
2016-06-18 06:38:08 +08:00
# CHECK: }
# CHECK: ]
[yaml2obj] Remove --format option in favor of YAML tags Summary: Our YAML library's handling of tags isn't perfect, but it is good enough to get rid of the need for the --format argument to yaml2obj. This patch does exactly that. Instead of requiring --format, it infers the format based on the tags found in the object file. The supported tags are: !ELF !COFF !mach-o !fat-mach-o I have a corresponding patch that is quite large that fixes up all the in-tree test cases. Reviewers: rafael, Bigcheese, compnerd, silvas Subscribers: compnerd, llvm-commits Differential Revision: http://reviews.llvm.org/D21711 llvm-svn: 273915
2016-06-28 03:53:53 +08:00
!ELF
Support/ELF: Add AMDGPU relocation definitions to match documentation Reviewers: arsenm, kzhuravl, rafael Subscribers: llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21443 llvm-svn: 273066
2016-06-18 06:38:08 +08:00
FileHeader:
Class: ELFCLASS64
Data: ELFDATA2LSB
Type: ET_REL
Machine: EM_AMDGPU
Sections:
- Type: SHT_PROGBITS
Name: .text
Flags: [ SHF_ALLOC, SHF_EXECINSTR ]
AddressAlign: 0x08
Content: 0000000000000000
- Type: SHT_RELA
Name: .rela.text
Link: .symtab
Info: .text
AddressAlign: 0x08
Relocations:
- Offset: 0x0
[Support/ELF/AMDGPU] Add 32-bit lo/hi got and pc relative relocations Added relocation names: - R_AMDGPU_GOTPCREL32_LO - R_AMDGPU_GOTPCREL32_HI - R_AMDGPU_REL32_LO - R_AMDGPU_REL32_HI AMDGPU isa only supports 32-bit immediates. In order to access 64-bit address we need to generate 32-bit lo/hi relocations, and do the right math (separate patch). Currently we only generate one 32 bit relocation for lower bits for each access, losing higher bits. Hence we need relocations listed above. Differential Revision: https://reviews.llvm.org/D25546 llvm-svn: 284191
2016-10-14 12:03:49 +08:00
Symbol: s0
Support/ELF: Add AMDGPU relocation definitions to match documentation Reviewers: arsenm, kzhuravl, rafael Subscribers: llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21443 llvm-svn: 273066
2016-06-18 06:38:08 +08:00
Type: R_AMDGPU_NONE
[Support/ELF/AMDGPU] Add 32-bit lo/hi got and pc relative relocations Added relocation names: - R_AMDGPU_GOTPCREL32_LO - R_AMDGPU_GOTPCREL32_HI - R_AMDGPU_REL32_LO - R_AMDGPU_REL32_HI AMDGPU isa only supports 32-bit immediates. In order to access 64-bit address we need to generate 32-bit lo/hi relocations, and do the right math (separate patch). Currently we only generate one 32 bit relocation for lower bits for each access, losing higher bits. Hence we need relocations listed above. Differential Revision: https://reviews.llvm.org/D25546 llvm-svn: 284191
2016-10-14 12:03:49 +08:00
- Offset: 0x2
Symbol: s1
Support/ELF: Add AMDGPU relocation definitions to match documentation Reviewers: arsenm, kzhuravl, rafael Subscribers: llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21443 llvm-svn: 273066
2016-06-18 06:38:08 +08:00
Type: R_AMDGPU_ABS32_LO
[Support/ELF/AMDGPU] Add 32-bit lo/hi got and pc relative relocations Added relocation names: - R_AMDGPU_GOTPCREL32_LO - R_AMDGPU_GOTPCREL32_HI - R_AMDGPU_REL32_LO - R_AMDGPU_REL32_HI AMDGPU isa only supports 32-bit immediates. In order to access 64-bit address we need to generate 32-bit lo/hi relocations, and do the right math (separate patch). Currently we only generate one 32 bit relocation for lower bits for each access, losing higher bits. Hence we need relocations listed above. Differential Revision: https://reviews.llvm.org/D25546 llvm-svn: 284191
2016-10-14 12:03:49 +08:00
- Offset: 0x4
Symbol: s2
Support/ELF: Add AMDGPU relocation definitions to match documentation Reviewers: arsenm, kzhuravl, rafael Subscribers: llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21443 llvm-svn: 273066
2016-06-18 06:38:08 +08:00
Type: R_AMDGPU_ABS32_HI
[Support/ELF/AMDGPU] Add 32-bit lo/hi got and pc relative relocations Added relocation names: - R_AMDGPU_GOTPCREL32_LO - R_AMDGPU_GOTPCREL32_HI - R_AMDGPU_REL32_LO - R_AMDGPU_REL32_HI AMDGPU isa only supports 32-bit immediates. In order to access 64-bit address we need to generate 32-bit lo/hi relocations, and do the right math (separate patch). Currently we only generate one 32 bit relocation for lower bits for each access, losing higher bits. Hence we need relocations listed above. Differential Revision: https://reviews.llvm.org/D25546 llvm-svn: 284191
2016-10-14 12:03:49 +08:00
- Offset: 0x6
Symbol: s3
Support/ELF: Add AMDGPU relocation definitions to match documentation Reviewers: arsenm, kzhuravl, rafael Subscribers: llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21443 llvm-svn: 273066
2016-06-18 06:38:08 +08:00
Type: R_AMDGPU_ABS64
[Support/ELF/AMDGPU] Add 32-bit lo/hi got and pc relative relocations Added relocation names: - R_AMDGPU_GOTPCREL32_LO - R_AMDGPU_GOTPCREL32_HI - R_AMDGPU_REL32_LO - R_AMDGPU_REL32_HI AMDGPU isa only supports 32-bit immediates. In order to access 64-bit address we need to generate 32-bit lo/hi relocations, and do the right math (separate patch). Currently we only generate one 32 bit relocation for lower bits for each access, losing higher bits. Hence we need relocations listed above. Differential Revision: https://reviews.llvm.org/D25546 llvm-svn: 284191
2016-10-14 12:03:49 +08:00
- Offset: 0x8
Symbol: s4
Support/ELF: Add AMDGPU relocation definitions to match documentation Reviewers: arsenm, kzhuravl, rafael Subscribers: llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21443 llvm-svn: 273066
2016-06-18 06:38:08 +08:00
Type: R_AMDGPU_REL32
[Support/ELF/AMDGPU] Add 32-bit lo/hi got and pc relative relocations Added relocation names: - R_AMDGPU_GOTPCREL32_LO - R_AMDGPU_GOTPCREL32_HI - R_AMDGPU_REL32_LO - R_AMDGPU_REL32_HI AMDGPU isa only supports 32-bit immediates. In order to access 64-bit address we need to generate 32-bit lo/hi relocations, and do the right math (separate patch). Currently we only generate one 32 bit relocation for lower bits for each access, losing higher bits. Hence we need relocations listed above. Differential Revision: https://reviews.llvm.org/D25546 llvm-svn: 284191
2016-10-14 12:03:49 +08:00
- Offset: 0x10
Symbol: s5
Support/ELF: Add AMDGPU relocation definitions to match documentation Reviewers: arsenm, kzhuravl, rafael Subscribers: llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21443 llvm-svn: 273066
2016-06-18 06:38:08 +08:00
Type: R_AMDGPU_REL64
[Support/ELF/AMDGPU] Add 32-bit lo/hi got and pc relative relocations Added relocation names: - R_AMDGPU_GOTPCREL32_LO - R_AMDGPU_GOTPCREL32_HI - R_AMDGPU_REL32_LO - R_AMDGPU_REL32_HI AMDGPU isa only supports 32-bit immediates. In order to access 64-bit address we need to generate 32-bit lo/hi relocations, and do the right math (separate patch). Currently we only generate one 32 bit relocation for lower bits for each access, losing higher bits. Hence we need relocations listed above. Differential Revision: https://reviews.llvm.org/D25546 llvm-svn: 284191
2016-10-14 12:03:49 +08:00
- Offset: 0x12
Symbol: s6
Support/ELF: Add AMDGPU relocation definitions to match documentation Reviewers: arsenm, kzhuravl, rafael Subscribers: llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21443 llvm-svn: 273066
2016-06-18 06:38:08 +08:00
Type: R_AMDGPU_ABS32
[Support/ELF/AMDGPU] Add 32-bit lo/hi got and pc relative relocations Added relocation names: - R_AMDGPU_GOTPCREL32_LO - R_AMDGPU_GOTPCREL32_HI - R_AMDGPU_REL32_LO - R_AMDGPU_REL32_HI AMDGPU isa only supports 32-bit immediates. In order to access 64-bit address we need to generate 32-bit lo/hi relocations, and do the right math (separate patch). Currently we only generate one 32 bit relocation for lower bits for each access, losing higher bits. Hence we need relocations listed above. Differential Revision: https://reviews.llvm.org/D25546 llvm-svn: 284191
2016-10-14 12:03:49 +08:00
- Offset: 0x14
Symbol: s7
Type: R_AMDGPU_GOTPCREL
- Offset: 0x16
Symbol: s8
Type: R_AMDGPU_GOTPCREL32_LO
- Offset: 0x18
Symbol: s9
Type: R_AMDGPU_GOTPCREL32_HI
- Offset: 0x20
Symbol: s10
Type: R_AMDGPU_REL32_LO
- Offset: 0x22
Symbol: s11
Type: R_AMDGPU_REL32_HI
Add base relative relocation record that can be used for the following case (OpenCL example): static __global int Var = 0; __global int* Ptr[] = {&Var}; ... In this case Var is a non premptable symbol and so its address can be used as the value of Ptr, with a base relative relocation that will add the delta between the ELF address and the actual load address. Such relocations do not require a symbol. Differential Revision: https://reviews.llvm.org/D38909 llvm-svn: 315935
2017-10-17 04:44:29 +08:00
- Offset: 0x24
Symbol: s12
Type: R_AMDGPU_RELATIVE64
Support/ELF: Add AMDGPU relocation definitions to match documentation Reviewers: arsenm, kzhuravl, rafael Subscribers: llvm-commits, kzhuravl Differential Revision: http://reviews.llvm.org/D21443 llvm-svn: 273066
2016-06-18 06:38:08 +08:00
Symbols:
Local:
- Name: .text
Type: STT_SECTION
Section: .text
Global:
- Name: main
Type: STT_FUNC
Section: .text
Size: 0x08