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[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s
[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs This patch adds support for the RISC-V hard float ABIs, building on top of rL355771, which added basic target-abi parsing and MC layer support. It also builds on some re-organisations and expansion of the upstream ABI and calling convention tests which were recently committed directly upstream. A number of aspects of the RISC-V float hard float ABIs require frontend support (e.g. flattening of structs and passing int+fp for fp+fp structs in a pair of registers), and will be addressed in a Clang patch. As can be seen from the tests, it would be worthwhile extending RISCVMergeBaseOffsets to handle constant pool as well as global accesses. Differential Revision: https://reviews.llvm.org/D59357 llvm-svn: 357352
2019-03-31 01:59:30 +08:00
; RUN: llc -mtriple=riscv32 -mattr=+f -target-abi ilp32f \
; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s
; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi ilp32d \
; RUN: -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s
Replace "no-frame-pointer-*" function attributes with "frame-pointer" Part of the effort to refactoring frame pointer code generation. We used to use two function attributes "no-frame-pointer-elim" and "no-frame-pointer-elim-non-leaf" to represent three kinds of frame pointer usage: (all) frames use frame pointer, (non-leaf) frames use frame pointer, (none) frame use frame pointer. This CL makes the idea explicit by using only one enum function attribute "frame-pointer" Option "-frame-pointer=" replaces "-disable-fp-elim" for tools such as llc. "no-frame-pointer-elim" and "no-frame-pointer-elim-non-leaf" are still supported for easy migration to "frame-pointer". tests are mostly updated with // replace command line args ‘-disable-fp-elim=false’ with ‘-frame-pointer=none’ grep -iIrnl '\-disable-fp-elim=false' * | xargs sed -i '' -e "s/-disable-fp-elim=false/-frame-pointer=none/g" // replace command line args ‘-disable-fp-elim’ with ‘-frame-pointer=all’ grep -iIrnl '\-disable-fp-elim' * | xargs sed -i '' -e "s/-disable-fp-elim/-frame-pointer=all/g" Patch by Yuanfang Chen (tabloid.adroit)! Differential Revision: https://reviews.llvm.org/D56351 llvm-svn: 351049
2019-01-14 18:55:55 +08:00
; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all < %s \
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s
[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs This patch adds support for the RISC-V hard float ABIs, building on top of rL355771, which added basic target-abi parsing and MC layer support. It also builds on some re-organisations and expansion of the upstream ABI and calling convention tests which were recently committed directly upstream. A number of aspects of the RISC-V float hard float ABIs require frontend support (e.g. flattening of structs and passing int+fp for fp+fp structs in a pair of registers), and will be addressed in a Clang patch. As can be seen from the tests, it would be worthwhile extending RISCVMergeBaseOffsets to handle constant pool as well as global accesses. Differential Revision: https://reviews.llvm.org/D59357 llvm-svn: 357352
2019-03-31 01:59:30 +08:00
; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all \
; RUN: -mattr=+f -target-abi ilp32f < %s \
; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s
; RUN: llc -mtriple=riscv32 -verify-machineinstrs -frame-pointer=all \
; RUN: -mattr=+d -target-abi ilp32d < %s \
; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; This file contains tests that should have identical output for the ilp32,
; ilp32f, and ilp32d ABIs. i.e. where no arguments are passed according to
; the floating point ABI. As well as calling convention details, we check that
; ra and fp are consistently stored to fp-4 and fp-8.
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; Check that on RV32, i64 is passed in a pair of registers. Unlike
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
; the convention for varargs, this need not be an aligned pair.
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
define i32 @callee_i64_in_regs(i32 %a, i64 %b) nounwind {
; RV32I-FPELIM-LABEL: callee_i64_in_regs:
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM: # %bb.0:
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-FPELIM-NEXT: add a0, a0, a1
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: ret
;
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-WITHFP-LABEL: callee_i64_in_regs:
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP: # %bb.0:
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
%b_trunc = trunc i64 %b to i32
%1 = add i32 %a, %b_trunc
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
ret i32 %1
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
}
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
define i32 @caller_i64_in_regs() nounwind {
; RV32I-FPELIM-LABEL: caller_i64_in_regs:
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI This reapplies commit r352010 with RISC-V test fixes. llvm-svn: 352237
2019-01-26 04:22:49 +08:00
; RV32I-FPELIM-NEXT: mv a2, zero
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-FPELIM-NEXT: call callee_i64_in_regs
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
;
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-WITHFP-LABEL: caller_i64_in_regs:
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2
Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI This reapplies commit r352010 with RISC-V test fixes. llvm-svn: 352237
2019-01-26 04:22:49 +08:00
; RV32I-WITHFP-NEXT: mv a2, zero
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-WITHFP-NEXT: call callee_i64_in_regs
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_i64_in_regs(i32 1, i64 2)
ret i32 %1
}
; Check that the stack is used once the GPRs are exhausted
define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i64 %d, i32 %e, i32 %f, i64 %g, i32 %h) nounwind {
; RV32I-FPELIM-LABEL: callee_many_scalars:
; RV32I-FPELIM: # %bb.0:
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: lw t0, 4(sp)
; RV32I-FPELIM-NEXT: lw t1, 0(sp)
; RV32I-FPELIM-NEXT: andi t2, a0, 255
; RV32I-FPELIM-NEXT: lui a0, 16
; RV32I-FPELIM-NEXT: addi a0, a0, -1
; RV32I-FPELIM-NEXT: and a0, a1, a0
; RV32I-FPELIM-NEXT: add a0, t2, a0
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-FPELIM-NEXT: add a0, a0, a2
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: xor a1, a4, t1
; RV32I-FPELIM-NEXT: xor a2, a3, a7
; RV32I-FPELIM-NEXT: or a1, a2, a1
; RV32I-FPELIM-NEXT: seqz a1, a1
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-FPELIM-NEXT: add a0, a1, a0
; RV32I-FPELIM-NEXT: add a0, a0, a5
; RV32I-FPELIM-NEXT: add a0, a0, a6
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: add a0, a0, t0
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: callee_many_scalars:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: lw t0, 4(s0)
; RV32I-WITHFP-NEXT: lw t1, 0(s0)
; RV32I-WITHFP-NEXT: andi t2, a0, 255
; RV32I-WITHFP-NEXT: lui a0, 16
; RV32I-WITHFP-NEXT: addi a0, a0, -1
; RV32I-WITHFP-NEXT: and a0, a1, a0
; RV32I-WITHFP-NEXT: add a0, t2, a0
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-WITHFP-NEXT: add a0, a0, a2
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: xor a1, a4, t1
; RV32I-WITHFP-NEXT: xor a2, a3, a7
; RV32I-WITHFP-NEXT: or a1, a2, a1
; RV32I-WITHFP-NEXT: seqz a1, a1
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-WITHFP-NEXT: add a0, a1, a0
; RV32I-WITHFP-NEXT: add a0, a0, a5
; RV32I-WITHFP-NEXT: add a0, a0, a6
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: add a0, a0, t0
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret
%a_ext = zext i8 %a to i32
%b_ext = zext i16 %b to i32
%1 = add i32 %a_ext, %b_ext
%2 = add i32 %1, %c
%3 = icmp eq i64 %d, %g
%4 = zext i1 %3 to i32
%5 = add i32 %4, %2
%6 = add i32 %5, %e
%7 = add i32 %6, %f
%8 = add i32 %7, %h
ret i32 %8
}
define i32 @caller_many_scalars() nounwind {
; RV32I-FPELIM-LABEL: caller_many_scalars:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 8
; RV32I-FPELIM-NEXT: sw a0, 4(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: addi a2, zero, 3
; RV32I-FPELIM-NEXT: addi a3, zero, 4
; RV32I-FPELIM-NEXT: addi a5, zero, 5
; RV32I-FPELIM-NEXT: addi a6, zero, 6
; RV32I-FPELIM-NEXT: addi a7, zero, 7
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: sw zero, 0(sp)
; RV32I-FPELIM-NEXT: mv a4, zero
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-FPELIM-NEXT: call callee_many_scalars
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: caller_many_scalars:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: addi a0, zero, 8
; RV32I-WITHFP-NEXT: sw a0, 4(sp)
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: addi a2, zero, 3
; RV32I-WITHFP-NEXT: addi a3, zero, 4
; RV32I-WITHFP-NEXT: addi a5, zero, 5
; RV32I-WITHFP-NEXT: addi a6, zero, 6
; RV32I-WITHFP-NEXT: addi a7, zero, 7
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: sw zero, 0(sp)
; RV32I-WITHFP-NEXT: mv a4, zero
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-WITHFP-NEXT: call callee_many_scalars
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
%1 = call i32 @callee_many_scalars(i8 1, i16 2, i32 3, i64 4, i32 5, i32 6, i64 7, i32 8)
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
ret i32 %1
}
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
; Check that i128 and fp128 are passed indirectly
define i32 @callee_large_scalars(i128 %a, fp128 %b) nounwind {
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-LABEL: callee_large_scalars:
; RV32I-FPELIM: # %bb.0:
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: lw a6, 0(a1)
; RV32I-FPELIM-NEXT: lw a7, 0(a0)
; RV32I-FPELIM-NEXT: lw a4, 4(a1)
; RV32I-FPELIM-NEXT: lw a5, 12(a1)
; RV32I-FPELIM-NEXT: lw a2, 12(a0)
; RV32I-FPELIM-NEXT: lw a3, 4(a0)
; RV32I-FPELIM-NEXT: lw a1, 8(a1)
; RV32I-FPELIM-NEXT: lw a0, 8(a0)
; RV32I-FPELIM-NEXT: xor a2, a2, a5
; RV32I-FPELIM-NEXT: xor a3, a3, a4
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: or a2, a3, a2
; RV32I-FPELIM-NEXT: xor a0, a0, a1
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: xor a1, a7, a6
; RV32I-FPELIM-NEXT: or a0, a1, a0
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: or a0, a0, a2
; RV32I-FPELIM-NEXT: seqz a0, a0
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: callee_large_scalars:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: lw a6, 0(a1)
; RV32I-WITHFP-NEXT: lw a7, 0(a0)
; RV32I-WITHFP-NEXT: lw a4, 4(a1)
; RV32I-WITHFP-NEXT: lw a5, 12(a1)
; RV32I-WITHFP-NEXT: lw a2, 12(a0)
; RV32I-WITHFP-NEXT: lw a3, 4(a0)
; RV32I-WITHFP-NEXT: lw a1, 8(a1)
; RV32I-WITHFP-NEXT: lw a0, 8(a0)
; RV32I-WITHFP-NEXT: xor a2, a2, a5
; RV32I-WITHFP-NEXT: xor a3, a3, a4
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: or a2, a3, a2
; RV32I-WITHFP-NEXT: xor a0, a0, a1
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: xor a1, a7, a6
; RV32I-WITHFP-NEXT: or a0, a1, a0
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: or a0, a0, a2
; RV32I-WITHFP-NEXT: seqz a0, a0
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
%b_bitcast = bitcast fp128 %b to i128
%1 = icmp eq i128 %a, %b_bitcast
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @caller_large_scalars() nounwind {
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-LABEL: caller_large_scalars:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -48
; RV32I-FPELIM-NEXT: sw ra, 44(sp)
[RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bits These immediates can be materialised with just an lui, rather than an lui+addi pair. llvm-svn: 330293
2018-04-19 04:34:23 +08:00
; RV32I-FPELIM-NEXT: lui a0, 524272
; RV32I-FPELIM-NEXT: sw a0, 12(sp)
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: sw zero, 8(sp)
; RV32I-FPELIM-NEXT: sw zero, 4(sp)
; RV32I-FPELIM-NEXT: sw zero, 0(sp)
; RV32I-FPELIM-NEXT: sw zero, 36(sp)
; RV32I-FPELIM-NEXT: sw zero, 32(sp)
; RV32I-FPELIM-NEXT: sw zero, 28(sp)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: addi a2, zero, 1
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: addi a0, sp, 24
; RV32I-FPELIM-NEXT: mv a1, sp
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: sw a2, 24(sp)
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-FPELIM-NEXT: call callee_large_scalars
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: lw ra, 44(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 48
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: caller_large_scalars:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -48
; RV32I-WITHFP-NEXT: sw ra, 44(sp)
; RV32I-WITHFP-NEXT: sw s0, 40(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 48
[RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bits These immediates can be materialised with just an lui, rather than an lui+addi pair. llvm-svn: 330293
2018-04-19 04:34:23 +08:00
; RV32I-WITHFP-NEXT: lui a0, 524272
; RV32I-WITHFP-NEXT: sw a0, -36(s0)
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: sw zero, -40(s0)
; RV32I-WITHFP-NEXT: sw zero, -44(s0)
; RV32I-WITHFP-NEXT: sw zero, -48(s0)
; RV32I-WITHFP-NEXT: sw zero, -12(s0)
; RV32I-WITHFP-NEXT: sw zero, -16(s0)
; RV32I-WITHFP-NEXT: sw zero, -20(s0)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: addi a2, zero, 1
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: addi a0, s0, -24
; RV32I-WITHFP-NEXT: addi a1, s0, -48
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: sw a2, -24(s0)
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-WITHFP-NEXT: call callee_large_scalars
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: lw s0, 40(sp)
; RV32I-WITHFP-NEXT: lw ra, 44(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 48
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
%1 = call i32 @callee_large_scalars(i128 1, fp128 0xL00000000000000007FFF000000000000)
ret i32 %1
}
; Check that arguments larger than 2*xlen are handled correctly when their
; address is passed on the stack rather than in memory
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; Must keep define on a single line due to an update_llc_test_checks.py limitation
define i32 @callee_large_scalars_exhausted_regs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i128 %h, i32 %i, fp128 %j) nounwind {
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-LABEL: callee_large_scalars_exhausted_regs:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lw a0, 4(sp)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: lw a6, 0(a0)
; RV32I-FPELIM-NEXT: lw t0, 0(a7)
; RV32I-FPELIM-NEXT: lw a3, 4(a0)
; RV32I-FPELIM-NEXT: lw a4, 12(a0)
; RV32I-FPELIM-NEXT: lw a5, 12(a7)
; RV32I-FPELIM-NEXT: lw a1, 4(a7)
; RV32I-FPELIM-NEXT: lw a0, 8(a0)
; RV32I-FPELIM-NEXT: lw a2, 8(a7)
; RV32I-FPELIM-NEXT: xor a4, a5, a4
; RV32I-FPELIM-NEXT: xor a1, a1, a3
; RV32I-FPELIM-NEXT: or a1, a1, a4
; RV32I-FPELIM-NEXT: xor a0, a2, a0
; RV32I-FPELIM-NEXT: xor a2, t0, a6
; RV32I-FPELIM-NEXT: or a0, a2, a0
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: or a0, a0, a1
; RV32I-FPELIM-NEXT: seqz a0, a0
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: callee_large_scalars_exhausted_regs:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw a0, 4(s0)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: lw a6, 0(a0)
; RV32I-WITHFP-NEXT: lw t0, 0(a7)
; RV32I-WITHFP-NEXT: lw a3, 4(a0)
; RV32I-WITHFP-NEXT: lw a4, 12(a0)
; RV32I-WITHFP-NEXT: lw a5, 12(a7)
; RV32I-WITHFP-NEXT: lw a1, 4(a7)
; RV32I-WITHFP-NEXT: lw a0, 8(a0)
; RV32I-WITHFP-NEXT: lw a2, 8(a7)
; RV32I-WITHFP-NEXT: xor a4, a5, a4
; RV32I-WITHFP-NEXT: xor a1, a1, a3
; RV32I-WITHFP-NEXT: or a1, a1, a4
; RV32I-WITHFP-NEXT: xor a0, a2, a0
; RV32I-WITHFP-NEXT: xor a2, t0, a6
; RV32I-WITHFP-NEXT: or a0, a2, a0
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: or a0, a0, a1
; RV32I-WITHFP-NEXT: seqz a0, a0
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
%j_bitcast = bitcast fp128 %j to i128
%1 = icmp eq i128 %h, %j_bitcast
%2 = zext i1 %1 to i32
ret i32 %2
}
define i32 @caller_large_scalars_exhausted_regs() nounwind {
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-LABEL: caller_large_scalars_exhausted_regs:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -64
; RV32I-FPELIM-NEXT: sw ra, 60(sp)
; RV32I-FPELIM-NEXT: addi a0, sp, 16
; RV32I-FPELIM-NEXT: sw a0, 4(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 9
; RV32I-FPELIM-NEXT: sw a0, 0(sp)
[RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bits These immediates can be materialised with just an lui, rather than an lui+addi pair. llvm-svn: 330293
2018-04-19 04:34:23 +08:00
; RV32I-FPELIM-NEXT: lui a0, 524272
; RV32I-FPELIM-NEXT: sw a0, 28(sp)
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: sw zero, 24(sp)
; RV32I-FPELIM-NEXT: sw zero, 20(sp)
; RV32I-FPELIM-NEXT: sw zero, 16(sp)
; RV32I-FPELIM-NEXT: sw zero, 52(sp)
; RV32I-FPELIM-NEXT: sw zero, 48(sp)
; RV32I-FPELIM-NEXT: sw zero, 44(sp)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: addi t0, zero, 8
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: addi a2, zero, 3
; RV32I-FPELIM-NEXT: addi a3, zero, 4
; RV32I-FPELIM-NEXT: addi a4, zero, 5
; RV32I-FPELIM-NEXT: addi a5, zero, 6
; RV32I-FPELIM-NEXT: addi a6, zero, 7
[RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move The isTriviallyRematerializable hook is only called for instructions that are tagged as isAsCheapAsAMove. Since ADDI 0 is used for "mv" it should definitely be marked with "isAsCheapAsAMove". This change avoids one stack spill in most of the atomic-rmw.ll tests functions. It also avoids stack spills in two of our out-of-tree CHERI tests. ORI/XORI with zero may or may not be the same as a move micro-architecturally, but since we are already doing it for register == x0, we might as well do the same if the immediate is zero. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D86480
2020-08-25 22:44:57 +08:00
; RV32I-FPELIM-NEXT: addi a7, sp, 40
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: sw t0, 40(sp)
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-FPELIM-NEXT: call callee_large_scalars_exhausted_regs
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: lw ra, 60(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 64
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: caller_large_scalars_exhausted_regs:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -64
; RV32I-WITHFP-NEXT: sw ra, 60(sp)
; RV32I-WITHFP-NEXT: sw s0, 56(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 64
; RV32I-WITHFP-NEXT: addi a0, s0, -48
; RV32I-WITHFP-NEXT: sw a0, 4(sp)
; RV32I-WITHFP-NEXT: addi a0, zero, 9
; RV32I-WITHFP-NEXT: sw a0, 0(sp)
[RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bits These immediates can be materialised with just an lui, rather than an lui+addi pair. llvm-svn: 330293
2018-04-19 04:34:23 +08:00
; RV32I-WITHFP-NEXT: lui a0, 524272
; RV32I-WITHFP-NEXT: sw a0, -36(s0)
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: sw zero, -40(s0)
; RV32I-WITHFP-NEXT: sw zero, -44(s0)
; RV32I-WITHFP-NEXT: sw zero, -48(s0)
; RV32I-WITHFP-NEXT: sw zero, -12(s0)
; RV32I-WITHFP-NEXT: sw zero, -16(s0)
; RV32I-WITHFP-NEXT: sw zero, -20(s0)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: addi t0, zero, 8
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: addi a2, zero, 3
; RV32I-WITHFP-NEXT: addi a3, zero, 4
; RV32I-WITHFP-NEXT: addi a4, zero, 5
; RV32I-WITHFP-NEXT: addi a5, zero, 6
; RV32I-WITHFP-NEXT: addi a6, zero, 7
[RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move The isTriviallyRematerializable hook is only called for instructions that are tagged as isAsCheapAsAMove. Since ADDI 0 is used for "mv" it should definitely be marked with "isAsCheapAsAMove". This change avoids one stack spill in most of the atomic-rmw.ll tests functions. It also avoids stack spills in two of our out-of-tree CHERI tests. ORI/XORI with zero may or may not be the same as a move micro-architecturally, but since we are already doing it for register == x0, we might as well do the same if the immediate is zero. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D86480
2020-08-25 22:44:57 +08:00
; RV32I-WITHFP-NEXT: addi a7, s0, -24
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: sw t0, -24(s0)
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-WITHFP-NEXT: call callee_large_scalars_exhausted_regs
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: lw s0, 56(sp)
; RV32I-WITHFP-NEXT: lw ra, 60(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 64
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
%1 = call i32 @callee_large_scalars_exhausted_regs(
i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i128 8, i32 9,
fp128 0xL00000000000000007FFF000000000000)
ret i32 %1
}
; Ensure that libcalls generated in the middle-end obey the calling convention
define i32 @caller_mixed_scalar_libcalls(i64 %a) nounwind {
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-LABEL: caller_mixed_scalar_libcalls:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -32
; RV32I-FPELIM-NEXT: sw ra, 28(sp)
; RV32I-FPELIM-NEXT: mv a2, a1
; RV32I-FPELIM-NEXT: mv a1, a0
; RV32I-FPELIM-NEXT: addi a0, sp, 8
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-FPELIM-NEXT: call __floatditf
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: lw a0, 8(sp)
; RV32I-FPELIM-NEXT: lw ra, 28(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 32
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: caller_mixed_scalar_libcalls:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -32
; RV32I-WITHFP-NEXT: sw ra, 28(sp)
; RV32I-WITHFP-NEXT: sw s0, 24(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 32
; RV32I-WITHFP-NEXT: mv a2, a1
; RV32I-WITHFP-NEXT: mv a1, a0
; RV32I-WITHFP-NEXT: addi a0, s0, -24
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-WITHFP-NEXT: call __floatditf
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: lw a0, -24(s0)
; RV32I-WITHFP-NEXT: lw s0, 24(sp)
; RV32I-WITHFP-NEXT: lw ra, 28(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 32
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
%1 = sitofp i64 %a to fp128
%2 = bitcast fp128 %1 to i128
%3 = trunc i128 %2 to i32
ret i32 %3
}
; Check passing of coerced integer arrays
%struct.small = type { i32, i32* }
define i32 @callee_small_coerced_struct([2 x i32] %a.coerce) nounwind {
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-LABEL: callee_small_coerced_struct:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: xor a0, a0, a1
; RV32I-FPELIM-NEXT: seqz a0, a0
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: callee_small_coerced_struct:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: xor a0, a0, a1
; RV32I-WITHFP-NEXT: seqz a0, a0
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
%1 = extractvalue [2 x i32] %a.coerce, 0
%2 = extractvalue [2 x i32] %a.coerce, 1
%3 = icmp eq i32 %1, %2
%4 = zext i1 %3 to i32
ret i32 %4
}
define i32 @caller_small_coerced_struct() nounwind {
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-LABEL: caller_small_coerced_struct:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 2
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-FPELIM-NEXT: call callee_small_coerced_struct
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: caller_small_coerced_struct:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 2
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-WITHFP-NEXT: call callee_small_coerced_struct
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
%1 = call i32 @callee_small_coerced_struct([2 x i32] [i32 1, i32 2])
ret i32 %1
}
; Check large struct arguments, which are passed byval
%struct.large = type { i32, i32, i32, i32 }
define i32 @callee_large_struct(%struct.large* byval align 4 %a) nounwind {
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-LABEL: callee_large_struct:
; RV32I-FPELIM: # %bb.0:
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: lw a1, 0(a0)
; RV32I-FPELIM-NEXT: lw a0, 12(a0)
; RV32I-FPELIM-NEXT: add a0, a1, a0
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: callee_large_struct:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: lw a1, 0(a0)
; RV32I-WITHFP-NEXT: lw a0, 12(a0)
; RV32I-WITHFP-NEXT: add a0, a1, a0
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
%1 = getelementptr inbounds %struct.large, %struct.large* %a, i32 0, i32 0
%2 = getelementptr inbounds %struct.large, %struct.large* %a, i32 0, i32 3
%3 = load i32, i32* %1
%4 = load i32, i32* %2
%5 = add i32 %3, %4
ret i32 %5
}
define i32 @caller_large_struct() nounwind {
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-LABEL: caller_large_struct:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -48
; RV32I-FPELIM-NEXT: sw ra, 44(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: sw a0, 24(sp)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: sw a1, 28(sp)
; RV32I-FPELIM-NEXT: addi a2, zero, 3
; RV32I-FPELIM-NEXT: sw a2, 32(sp)
; RV32I-FPELIM-NEXT: addi a3, zero, 4
; RV32I-FPELIM-NEXT: sw a3, 36(sp)
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: sw a0, 8(sp)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: sw a1, 12(sp)
; RV32I-FPELIM-NEXT: sw a2, 16(sp)
; RV32I-FPELIM-NEXT: sw a3, 20(sp)
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: addi a0, sp, 8
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-FPELIM-NEXT: call callee_large_struct
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: lw ra, 44(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 48
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: caller_large_struct:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -48
; RV32I-WITHFP-NEXT: sw ra, 44(sp)
; RV32I-WITHFP-NEXT: sw s0, 40(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 48
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: sw a0, -24(s0)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: sw a1, -20(s0)
; RV32I-WITHFP-NEXT: addi a2, zero, 3
; RV32I-WITHFP-NEXT: sw a2, -16(s0)
; RV32I-WITHFP-NEXT: addi a3, zero, 4
; RV32I-WITHFP-NEXT: sw a3, -12(s0)
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: sw a0, -40(s0)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: sw a1, -36(s0)
; RV32I-WITHFP-NEXT: sw a2, -32(s0)
; RV32I-WITHFP-NEXT: sw a3, -28(s0)
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: addi a0, s0, -40
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-WITHFP-NEXT: call callee_large_struct
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: lw s0, 40(sp)
; RV32I-WITHFP-NEXT: lw ra, 44(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 48
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
%ls = alloca %struct.large, align 4
%1 = bitcast %struct.large* %ls to i8*
%a = getelementptr inbounds %struct.large, %struct.large* %ls, i32 0, i32 0
store i32 1, i32* %a
%b = getelementptr inbounds %struct.large, %struct.large* %ls, i32 0, i32 1
store i32 2, i32* %b
%c = getelementptr inbounds %struct.large, %struct.large* %ls, i32 0, i32 2
store i32 3, i32* %c
%d = getelementptr inbounds %struct.large, %struct.large* %ls, i32 0, i32 3
store i32 4, i32* %d
%2 = call i32 @callee_large_struct(%struct.large* byval align 4 %ls)
ret i32 %2
}
; Check 2x*xlen values are aligned appropriately when passed on the stack
; Must keep define on a single line due to an update_llc_test_checks.py limitation
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
define i32 @callee_aligned_stack(i32 %a, i32 %b, fp128 %c, i32 %d, i32 %e, i64 %f, i32 %g, i32 %h, i64 %i, i32 %j, [2 x i32] %k) nounwind {
; The i64 should be 8-byte aligned on the stack, but the two-element array
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
; should only be 4-byte aligned
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-LABEL: callee_aligned_stack:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lw a0, 0(a2)
Revert Patch from Phabricator This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
2019-09-17 18:52:09 +08:00
; RV32I-FPELIM-NEXT: lw a1, 20(sp)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: lw a2, 0(sp)
; RV32I-FPELIM-NEXT: lw a3, 8(sp)
; RV32I-FPELIM-NEXT: lw a4, 16(sp)
; RV32I-FPELIM-NEXT: add a0, a0, a7
; RV32I-FPELIM-NEXT: add a0, a0, a2
; RV32I-FPELIM-NEXT: add a0, a0, a3
; RV32I-FPELIM-NEXT: add a0, a0, a4
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: callee_aligned_stack:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw a0, 0(a2)
Revert Patch from Phabricator This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
2019-09-17 18:52:09 +08:00
; RV32I-WITHFP-NEXT: lw a1, 20(s0)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: lw a2, 0(s0)
; RV32I-WITHFP-NEXT: lw a3, 8(s0)
; RV32I-WITHFP-NEXT: lw a4, 16(s0)
; RV32I-WITHFP-NEXT: add a0, a0, a7
; RV32I-WITHFP-NEXT: add a0, a0, a2
; RV32I-WITHFP-NEXT: add a0, a0, a3
; RV32I-WITHFP-NEXT: add a0, a0, a4
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
%1 = bitcast fp128 %c to i128
%2 = trunc i128 %1 to i32
%3 = add i32 %2, %g
%4 = add i32 %3, %h
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
%5 = trunc i64 %i to i32
%6 = add i32 %4, %5
%7 = add i32 %6, %j
%8 = extractvalue [2 x i32] %k, 0
%9 = add i32 %7, %8
ret i32 %9
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
}
define void @caller_aligned_stack() nounwind {
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; The i64 should be 8-byte aligned on the stack, but the two-element array
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
; should only be 4-byte aligned
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-LABEL: caller_aligned_stack:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -64
; RV32I-FPELIM-NEXT: sw ra, 60(sp)
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-FPELIM-NEXT: addi a0, zero, 19
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: sw a0, 24(sp)
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-FPELIM-NEXT: addi a0, zero, 18
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: sw a0, 20(sp)
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-FPELIM-NEXT: addi a0, zero, 17
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: sw a0, 16(sp)
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-FPELIM-NEXT: sw zero, 12(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 16
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: sw a0, 8(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 15
; RV32I-FPELIM-NEXT: sw a0, 0(sp)
; RV32I-FPELIM-NEXT: lui a0, 262153
; RV32I-FPELIM-NEXT: addi a0, a0, 491
; RV32I-FPELIM-NEXT: sw a0, 44(sp)
; RV32I-FPELIM-NEXT: lui a0, 545260
; RV32I-FPELIM-NEXT: addi a0, a0, -1967
; RV32I-FPELIM-NEXT: sw a0, 40(sp)
; RV32I-FPELIM-NEXT: lui a0, 964690
; RV32I-FPELIM-NEXT: addi a0, a0, -328
; RV32I-FPELIM-NEXT: sw a0, 36(sp)
; RV32I-FPELIM-NEXT: lui a0, 335544
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: addi t0, a0, 1311
Revert "[RISCV] implement li pseudo instruction" Reverts rL330224, while issues with the C extension and missed common subexpression elimination opportunities are addressed. Neither of these issues are visible in current RISC-V backend unit tests, which clearly need expanding. llvm-svn: 330281
2018-04-19 03:02:31 +08:00
; RV32I-FPELIM-NEXT: lui a0, 688509
; RV32I-FPELIM-NEXT: addi a5, a0, -2048
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: addi a1, zero, 11
[RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move The isTriviallyRematerializable hook is only called for instructions that are tagged as isAsCheapAsAMove. Since ADDI 0 is used for "mv" it should definitely be marked with "isAsCheapAsAMove". This change avoids one stack spill in most of the atomic-rmw.ll tests functions. It also avoids stack spills in two of our out-of-tree CHERI tests. ORI/XORI with zero may or may not be the same as a move micro-architecturally, but since we are already doing it for register == x0, we might as well do the same if the immediate is zero. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D86480
2020-08-25 22:44:57 +08:00
; RV32I-FPELIM-NEXT: addi a2, sp, 32
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: addi a3, zero, 12
; RV32I-FPELIM-NEXT: addi a4, zero, 13
; RV32I-FPELIM-NEXT: addi a6, zero, 4
; RV32I-FPELIM-NEXT: addi a7, zero, 14
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: sw t0, 32(sp)
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-FPELIM-NEXT: call callee_aligned_stack
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: lw ra, 60(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 64
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: caller_aligned_stack:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -64
; RV32I-WITHFP-NEXT: sw ra, 60(sp)
; RV32I-WITHFP-NEXT: sw s0, 56(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 64
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-WITHFP-NEXT: addi a0, zero, 19
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: sw a0, 24(sp)
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-WITHFP-NEXT: addi a0, zero, 18
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: sw a0, 20(sp)
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-WITHFP-NEXT: addi a0, zero, 17
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: sw a0, 16(sp)
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
; RV32I-WITHFP-NEXT: sw zero, 12(sp)
; RV32I-WITHFP-NEXT: addi a0, zero, 16
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: sw a0, 8(sp)
; RV32I-WITHFP-NEXT: addi a0, zero, 15
; RV32I-WITHFP-NEXT: sw a0, 0(sp)
; RV32I-WITHFP-NEXT: lui a0, 262153
; RV32I-WITHFP-NEXT: addi a0, a0, 491
; RV32I-WITHFP-NEXT: sw a0, -20(s0)
; RV32I-WITHFP-NEXT: lui a0, 545260
; RV32I-WITHFP-NEXT: addi a0, a0, -1967
; RV32I-WITHFP-NEXT: sw a0, -24(s0)
; RV32I-WITHFP-NEXT: lui a0, 964690
; RV32I-WITHFP-NEXT: addi a0, a0, -328
; RV32I-WITHFP-NEXT: sw a0, -28(s0)
; RV32I-WITHFP-NEXT: lui a0, 335544
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: addi t0, a0, 1311
Revert "[RISCV] implement li pseudo instruction" Reverts rL330224, while issues with the C extension and missed common subexpression elimination opportunities are addressed. Neither of these issues are visible in current RISC-V backend unit tests, which clearly need expanding. llvm-svn: 330281
2018-04-19 03:02:31 +08:00
; RV32I-WITHFP-NEXT: lui a0, 688509
; RV32I-WITHFP-NEXT: addi a5, a0, -2048
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: addi a1, zero, 11
[RISC-V] ADDI/ORI/XORI x, 0 should be as cheap as a move The isTriviallyRematerializable hook is only called for instructions that are tagged as isAsCheapAsAMove. Since ADDI 0 is used for "mv" it should definitely be marked with "isAsCheapAsAMove". This change avoids one stack spill in most of the atomic-rmw.ll tests functions. It also avoids stack spills in two of our out-of-tree CHERI tests. ORI/XORI with zero may or may not be the same as a move micro-architecturally, but since we are already doing it for register == x0, we might as well do the same if the immediate is zero. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D86480
2020-08-25 22:44:57 +08:00
; RV32I-WITHFP-NEXT: addi a2, s0, -32
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: addi a3, zero, 12
; RV32I-WITHFP-NEXT: addi a4, zero, 13
; RV32I-WITHFP-NEXT: addi a6, zero, 4
; RV32I-WITHFP-NEXT: addi a7, zero, 14
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: sw t0, -32(s0)
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-WITHFP-NEXT: call callee_aligned_stack
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: lw s0, 56(sp)
; RV32I-WITHFP-NEXT: lw ra, 60(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 64
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
%1 = call i32 @callee_aligned_stack(i32 1, i32 11,
fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13,
[RISCV] Re-organise calling convention tests Re-organise calling convention tests to prepare for ilp32f and ilp32d hard float ABI tests. It's also clear that we need to introduce similar tests for lp64. llvm-svn: 354323
2019-02-19 21:47:19 +08:00
i64 20000000000, i32 14, i32 15, i64 16, i32 17,
[2 x i32] [i32 18, i32 19])
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
ret void
}
; Check return of 2x xlen scalars
define i64 @callee_small_scalar_ret() nounwind {
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-LABEL: callee_small_scalar_ret:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lui a0, 466866
; RV32I-FPELIM-NEXT: addi a0, a0, 1677
; RV32I-FPELIM-NEXT: addi a1, zero, 287
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: callee_small_scalar_ret:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lui a0, 466866
; RV32I-WITHFP-NEXT: addi a0, a0, 1677
; RV32I-WITHFP-NEXT: addi a1, zero, 287
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
ret i64 1234567898765
}
define i32 @caller_small_scalar_ret() nounwind {
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-LABEL: caller_small_scalar_ret:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-FPELIM-NEXT: call callee_small_scalar_ret
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: lui a2, 56
; RV32I-FPELIM-NEXT: addi a2, a2, 580
; RV32I-FPELIM-NEXT: xor a1, a1, a2
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: lui a2, 200614
; RV32I-FPELIM-NEXT: addi a2, a2, 647
; RV32I-FPELIM-NEXT: xor a0, a0, a2
; RV32I-FPELIM-NEXT: or a0, a0, a1
; RV32I-FPELIM-NEXT: seqz a0, a0
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: caller_small_scalar_ret:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-WITHFP-NEXT: call callee_small_scalar_ret
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: lui a2, 56
; RV32I-WITHFP-NEXT: addi a2, a2, 580
; RV32I-WITHFP-NEXT: xor a1, a1, a2
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: lui a2, 200614
; RV32I-WITHFP-NEXT: addi a2, a2, 647
; RV32I-WITHFP-NEXT: xor a0, a0, a2
; RV32I-WITHFP-NEXT: or a0, a0, a1
; RV32I-WITHFP-NEXT: seqz a0, a0
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
%1 = call i64 @callee_small_scalar_ret()
%2 = icmp eq i64 987654321234567, %1
%3 = zext i1 %2 to i32
ret i32 %3
}
; Check return of 2x xlen structs
define %struct.small @callee_small_struct_ret() nounwind {
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-LABEL: callee_small_struct_ret:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: mv a1, zero
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: callee_small_struct_ret:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: mv a1, zero
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
ret %struct.small { i32 1, i32* null }
}
define i32 @caller_small_struct_ret() nounwind {
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-LABEL: caller_small_struct_ret:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-FPELIM-NEXT: call callee_small_struct_ret
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: caller_small_struct_ret:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-WITHFP-NEXT: call callee_small_struct_ret
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
%1 = call %struct.small @callee_small_struct_ret()
%2 = extractvalue %struct.small %1, 0
%3 = extractvalue %struct.small %1, 1
%4 = ptrtoint i32* %3 to i32
%5 = add i32 %2, %4
ret i32 %5
}
; Check return of >2x xlen scalars
define fp128 @callee_large_scalar_ret() nounwind {
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-LABEL: callee_large_scalar_ret:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lui a1, 524272
; RV32I-FPELIM-NEXT: sw a1, 12(a0)
; RV32I-FPELIM-NEXT: sw zero, 8(a0)
; RV32I-FPELIM-NEXT: sw zero, 4(a0)
; RV32I-FPELIM-NEXT: sw zero, 0(a0)
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: callee_large_scalar_ret:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lui a1, 524272
; RV32I-WITHFP-NEXT: sw a1, 12(a0)
; RV32I-WITHFP-NEXT: sw zero, 8(a0)
; RV32I-WITHFP-NEXT: sw zero, 4(a0)
; RV32I-WITHFP-NEXT: sw zero, 0(a0)
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
ret fp128 0xL00000000000000007FFF000000000000
}
define void @caller_large_scalar_ret() nounwind {
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-LABEL: caller_large_scalar_ret:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -32
; RV32I-FPELIM-NEXT: sw ra, 28(sp)
; RV32I-FPELIM-NEXT: mv a0, sp
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-FPELIM-NEXT: call callee_large_scalar_ret
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: lw ra, 28(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 32
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: caller_large_scalar_ret:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -32
; RV32I-WITHFP-NEXT: sw ra, 28(sp)
; RV32I-WITHFP-NEXT: sw s0, 24(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 32
; RV32I-WITHFP-NEXT: addi a0, s0, -32
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-WITHFP-NEXT: call callee_large_scalar_ret
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: lw s0, 24(sp)
; RV32I-WITHFP-NEXT: lw ra, 28(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 32
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
%1 = call fp128 @callee_large_scalar_ret()
ret void
}
; Check return of >2x xlen structs
define void @callee_large_struct_ret(%struct.large* noalias sret %agg.result) nounwind {
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-LABEL: callee_large_struct_ret:
; RV32I-FPELIM: # %bb.0:
Revert Patch from Phabricator This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
2019-09-17 18:52:09 +08:00
; RV32I-FPELIM-NEXT: addi a1, zero, 1
; RV32I-FPELIM-NEXT: sw a1, 0(a0)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: addi a1, zero, 2
; RV32I-FPELIM-NEXT: sw a1, 4(a0)
; RV32I-FPELIM-NEXT: addi a1, zero, 3
; RV32I-FPELIM-NEXT: sw a1, 8(a0)
; RV32I-FPELIM-NEXT: addi a1, zero, 4
; RV32I-FPELIM-NEXT: sw a1, 12(a0)
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: callee_large_struct_ret:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -16
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
Revert Patch from Phabricator This reverts r372092 (git commit e38695a0255c9e7b53639f349f8101bae1ce5c04) llvm-svn: 372104
2019-09-17 18:52:09 +08:00
; RV32I-WITHFP-NEXT: addi a1, zero, 1
; RV32I-WITHFP-NEXT: sw a1, 0(a0)
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: addi a1, zero, 2
; RV32I-WITHFP-NEXT: sw a1, 4(a0)
; RV32I-WITHFP-NEXT: addi a1, zero, 3
; RV32I-WITHFP-NEXT: sw a1, 8(a0)
; RV32I-WITHFP-NEXT: addi a1, zero, 4
; RV32I-WITHFP-NEXT: sw a1, 12(a0)
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
%a = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 0
store i32 1, i32* %a, align 4
%b = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 1
store i32 2, i32* %b, align 4
%c = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 2
store i32 3, i32* %c, align 4
%d = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 3
store i32 4, i32* %d, align 4
ret void
}
define i32 @caller_large_struct_ret() nounwind {
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-LABEL: caller_large_struct_ret:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -32
; RV32I-FPELIM-NEXT: sw ra, 28(sp)
; RV32I-FPELIM-NEXT: addi a0, sp, 8
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-FPELIM-NEXT: call callee_large_struct_ret
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-FPELIM-NEXT: lw a0, 8(sp)
; RV32I-FPELIM-NEXT: lw a1, 20(sp)
; RV32I-FPELIM-NEXT: add a0, a0, a1
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-FPELIM-NEXT: lw ra, 28(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 32
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: caller_large_struct_ret:
; RV32I-WITHFP: # %bb.0:
; RV32I-WITHFP-NEXT: addi sp, sp, -32
; RV32I-WITHFP-NEXT: sw ra, 28(sp)
; RV32I-WITHFP-NEXT: sw s0, 24(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 32
; RV32I-WITHFP-NEXT: addi a0, s0, -24
[RISCV] Expand function call to "call" pseudoinstruction To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
2018-04-25 22:19:12 +08:00
; RV32I-WITHFP-NEXT: call callee_large_struct_ret
[RISCV] Switch to the Machine Scheduler Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106
2019-09-17 19:15:35 +08:00
; RV32I-WITHFP-NEXT: lw a0, -24(s0)
; RV32I-WITHFP-NEXT: lw a1, -12(s0)
; RV32I-WITHFP-NEXT: add a0, a0, a1
[RISCV] Implement frame pointer elimination llvm-svn: 322839
2018-01-18 19:34:02 +08:00
; RV32I-WITHFP-NEXT: lw s0, 24(sp)
; RV32I-WITHFP-NEXT: lw ra, 28(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 32
; RV32I-WITHFP-NEXT: ret
[RISCV] Add custom CC_RISCV calling convention and improved call support The TableGen-based calling convention definitions are inflexible, while writing a function to implement the calling convention is very straight-forward, and allows difficult cases to be handled more easily. With this patch adds support for: * Passing large scalars according to the RV32I calling convention * Byval arguments * Passing values on the stack when the argument registers are exhausted The custom CC_RISCV calling convention is also used for returns. This patch also documents the ABI lowering that a language frontend is expected to perform. I would like to work to simplify these requirements over time, but this will require further discussion within the LLVM community. We add PendingArgFlags CCState, as a companion to PendingLocs. The PendingLocs vector is used by a number of backends to handle arguments that are split during legalisation. However CCValAssign doesn't keep track of the original argument alignment. Therefore, add a PendingArgFlags vector which can be used to keep track of the ISD::ArgFlagsTy for every value added to PendingLocs. Differential Revision: https://reviews.llvm.org/D39898 llvm-svn: 320359
2017-12-11 20:49:02 +08:00
%1 = alloca %struct.large
call void @callee_large_struct_ret(%struct.large* sret %1)
%2 = getelementptr inbounds %struct.large, %struct.large* %1, i32 0, i32 0
%3 = load i32, i32* %2
%4 = getelementptr inbounds %struct.large, %struct.large* %1, i32 0, i32 3
%5 = load i32, i32* %4
%6 = add i32 %3, %5
ret i32 %6
}