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llvm-project/llvm/test/CodeGen/AMDGPU/regcoalesce-prune.mir

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LiveIntervalAnalysis: Fix missing case in pruneSubRegValues() pruneSubRegValues() needs to remove subregister ranges starting at instructions that later get removed by eraseInstrs(). It missed to check one case in which eraseInstrs() would remove an instruction. Fixes http://llvm.org/PR32688 llvm-svn: 303396
2017-05-19 08:18:03 +08:00
# RUN: llc -o - %s -mtriple=amdgcn-amd-amdhsa-opencl -run-pass=simple-register-coalescing | FileCheck %s
---
# Checks for a bug where subregister liveranges were not properly pruned for
# an IMPLCITI_DEF that gets removed completely.
#
# CHECK-LABEL: name: func
# IMPLICIT_DEF should be gone without llc hitting assertion failures.
Fix typo in test llvm-svn: 303436
2017-05-20 01:25:20 +08:00
# CHECK-NOT: IMPLICIT_DEF
LiveIntervalAnalysis: Fix missing case in pruneSubRegValues() pruneSubRegValues() needs to remove subregister ranges starting at instructions that later get removed by eraseInstrs(). It missed to check one case in which eraseInstrs() would remove an instruction. Fixes http://llvm.org/PR32688 llvm-svn: 303396
2017-05-19 08:18:03 +08:00
name: func
tracksRegLiveness: true
body: |
bb.0:
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
undef %5.sub1 = V_MOV_B32_e32 0, implicit $exec
LiveIntervalAnalysis: Fix missing case in pruneSubRegValues() pruneSubRegValues() needs to remove subregister ranges starting at instructions that later get removed by eraseInstrs(). It missed to check one case in which eraseInstrs() would remove an instruction. Fixes http://llvm.org/PR32688 llvm-svn: 303396
2017-05-19 08:18:03 +08:00
%6 = COPY %5
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
S_CBRANCH_VCCZ %bb.2, implicit undef $vcc
LiveIntervalAnalysis: Fix missing case in pruneSubRegValues() pruneSubRegValues() needs to remove subregister ranges starting at instructions that later get removed by eraseInstrs(). It missed to check one case in which eraseInstrs() would remove an instruction. Fixes http://llvm.org/PR32688 llvm-svn: 303396
2017-05-19 08:18:03 +08:00
bb.1:
%1 : sreg_32_xm0 = S_MOV_B32 0
undef %0.sub0 : sreg_64 = COPY %1
%0.sub1 = COPY %1
%4 : vreg_64 = COPY killed %0
%5 : vreg_64 = IMPLICIT_DEF
%6 : vreg_64 = COPY killed %4
bb.2:
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
%2 : vgpr_32 = V_CVT_F32_I32_e32 killed %5.sub1, implicit $mode, implicit $exec
LiveIntervalAnalysis: Fix missing case in pruneSubRegValues() pruneSubRegValues() needs to remove subregister ranges starting at instructions that later get removed by eraseInstrs(). It missed to check one case in which eraseInstrs() would remove an instruction. Fixes http://llvm.org/PR32688 llvm-svn: 303396
2017-05-19 08:18:03 +08:00
bb.3:
AMDGPU: Start adding MODE register uses to instructions This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
2020-05-28 01:25:37 +08:00
%3 : vgpr_32 = V_CVT_F32_I32_e32 killed %6.sub1, implicit $mode, implicit $exec
[AMDGPU] Add support for immediate operand for S_ENDPGM Summary: Add support for immediate operand in S_ENDPGM Change-Id: I0c56a076a10980f719fb2a8f16407e9c301013f6 Reviewers: alexshap Subscribers: qcolombet, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, tpr, t-tye, eraman, arphaman, Petar.Avramovic, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D59213 llvm-svn: 355902
2019-03-12 17:52:58 +08:00
S_ENDPGM 0
LiveIntervalAnalysis: Fix missing case in pruneSubRegValues() pruneSubRegValues() needs to remove subregister ranges starting at instructions that later get removed by eraseInstrs(). It missed to check one case in which eraseInstrs() would remove an instruction. Fixes http://llvm.org/PR32688 llvm-svn: 303396
2017-05-19 08:18:03 +08:00
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