forked from OSchip/llvm-project
64 lines
2.5 KiB
Plaintext
64 lines
2.5 KiB
Plaintext
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=legalizer %s -o - | FileCheck -check-prefix=SI %s
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -run-pass=legalizer %s -o - | FileCheck -check-prefix=VI %s
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---
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name: test_rsq_clamp_flags_ieee_on_f32
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tracksRegLiveness: true
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machineFunctionInfo:
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mode:
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ieee: true
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body: |
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bb.0:
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liveins: $vgpr0
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; SI-LABEL: name: test_rsq_clamp_flags_ieee_on_f32
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; SI: liveins: $vgpr0
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; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; SI: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), [[COPY]](s32)
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; SI: $vgpr0 = COPY [[INT]](s32)
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; VI-LABEL: name: test_rsq_clamp_flags_ieee_on_f32
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; VI: liveins: $vgpr0
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; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; VI: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[COPY]](s32)
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; VI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x47EFFFFFE0000000
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; VI: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMINNUM_IEEE [[INT]], [[C]]
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; VI: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC7EFFFFFE0000000
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; VI: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMAXNUM_IEEE [[FMINNUM_IEEE]], [[C1]]
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; VI: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0
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$vgpr0 = COPY %1
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...
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---
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name: test_rsq_clamp_flags_ieee_off_f32
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tracksRegLiveness: true
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machineFunctionInfo:
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mode:
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ieee: false
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body: |
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bb.0:
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liveins: $vgpr0
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; SI-LABEL: name: test_rsq_clamp_flags_ieee_off_f32
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; SI: liveins: $vgpr0
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; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; SI: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), [[COPY]](s32)
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; SI: $vgpr0 = COPY [[INT]](s32)
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; VI-LABEL: name: test_rsq_clamp_flags_ieee_off_f32
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; VI: liveins: $vgpr0
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; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; VI: [[INT:%[0-9]+]]:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq), [[COPY]](s32)
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; VI: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x47EFFFFFE0000000
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; VI: [[FMINNUM:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMINNUM [[INT]], [[C]]
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; VI: [[C1:%[0-9]+]]:_(s32) = G_FCONSTANT float 0xC7EFFFFFE0000000
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; VI: [[FMAXNUM:%[0-9]+]]:_(s32) = nnan ninf nsz G_FMAXNUM [[FMINNUM]], [[C1]]
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; VI: $vgpr0 = COPY [[FMAXNUM]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = nnan ninf nsz G_INTRINSIC intrinsic(@llvm.amdgcn.rsq.clamp), %0
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$vgpr0 = COPY %1
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...
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