maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call-sret.ll

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

89 lines
5.9 KiB
LLVM
Raw Normal View History

AMDGPU/GlobalISel: Handle call return values The only case that I know doesn't work is the implicit sret case when the return type doesn't fit in the return registers.
2020-07-06 04:15:36 +08:00
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -global-isel -amdgpu-fixed-function-abi -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -stop-after=irtranslator -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
declare hidden void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret, { i8, i32 } addrspace(5)* byval) #0
define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32(i32) #0 {
; GCN-LABEL: name: test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32
; GCN: bb.1 (%ir-block.1):
; GCN: liveins: $sgpr14, $sgpr15, $sgpr16, $vgpr0, $vgpr1, $vgpr2, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11
; GCN: [[COPY:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr2
; GCN: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr1
; GCN: [[COPY2:%[0-9]+]]:vgpr_32(s32) = COPY $vgpr0
; GCN: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr16
; GCN: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr15
; GCN: [[COPY5:%[0-9]+]]:sgpr_32 = COPY $sgpr14
; GCN: [[COPY6:%[0-9]+]]:sgpr_64 = COPY $sgpr10_sgpr11
; GCN: [[COPY7:%[0-9]+]]:sgpr_64 = COPY $sgpr6_sgpr7
; GCN: [[COPY8:%[0-9]+]]:sgpr_64 = COPY $sgpr4_sgpr5
; GCN: [[COPY9:%[0-9]+]]:_(p4) = COPY $sgpr8_sgpr9
; GCN: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
; GCN: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
; GCN: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF
; GCN: [[COPY10:%[0-9]+]]:_(p1) = COPY [[DEF]](p1)
; GCN: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.0.in.val
; GCN: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %stack.1.out.val
; GCN: [[INT:%[0-9]+]]:_(p4) = G_INTRINSIC intrinsic(@llvm.amdgcn.kernarg.segment.ptr)
; GCN: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
; GCN: [[PTR_ADD:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX]], [[C2]](s32)
; GCN: G_STORE [[C]](s8), [[FRAME_INDEX]](p5) :: (store 1 into %ir.in.gep01, addrspace 5)
; GCN: G_STORE [[C1]](s32), [[PTR_ADD]](p5) :: (store 4 into %ir.in.gep1, addrspace 5)
; GCN: ADJCALLSTACKUP 0, 0, implicit-def $scc
; GCN: [[GV:%[0-9]+]]:sreg_64(p0) = G_GLOBAL_VALUE @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32
; GCN: [[COPY11:%[0-9]+]]:_(p4) = COPY [[COPY8]]
; GCN: [[COPY12:%[0-9]+]]:_(p4) = COPY [[COPY7]]
; GCN: [[COPY13:%[0-9]+]]:_(p4) = COPY [[COPY9]](p4)
; GCN: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; GCN: [[PTR_ADD1:%[0-9]+]]:_(p4) = G_PTR_ADD [[COPY13]], [[C3]](s64)
; GCN: [[COPY14:%[0-9]+]]:_(s64) = COPY [[COPY6]]
; GCN: [[COPY15:%[0-9]+]]:_(s32) = COPY [[COPY5]]
; GCN: [[COPY16:%[0-9]+]]:_(s32) = COPY [[COPY4]]
; GCN: [[COPY17:%[0-9]+]]:_(s32) = COPY [[COPY3]]
; GCN: [[COPY18:%[0-9]+]]:_(s32) = COPY [[COPY2]](s32)
; GCN: [[COPY19:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32)
; GCN: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; GCN: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY19]], [[C4]](s32)
; GCN: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY18]], [[SHL]]
; GCN: [[COPY20:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; GCN: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 20
; GCN: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[COPY20]], [[C5]](s32)
; GCN: [[OR1:%[0-9]+]]:_(s32) = G_OR [[OR]], [[SHL1]]
; GCN: $vgpr0 = COPY [[FRAME_INDEX1]](p5)
[GlobalISel][CallLowering] Look through call parameters for flags We weren't looking through the parameters on calls at all. E.g., say you had ``` declare i32 @zext(i32 zeroext %x) ... %y = call i32 @zext(i32 %something) ... ``` At the point of the call, we wouldn't know that the %something should have the zeroext attribute. This sets flags in about the same way as TargetLoweringBase::ArgListEntry::setAttributes. Differential Revision: https://reviews.llvm.org/D86125
2020-08-18 07:42:28 +08:00
; GCN: [[COPY21:%[0-9]+]]:_(p5) = COPY $sp_reg
; GCN: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; GCN: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C6]](s32)
; GCN: G_STORE [[FRAME_INDEX]](p5), [[PTR_ADD2]](p5) :: (store 4 into stack, align 16, addrspace 5)
; GCN: [[COPY22:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg
; GCN: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY22]](<4 x s32>)
AMDGPU/GlobalISel: Handle call return values The only case that I know doesn't work is the implicit sret case when the return type doesn't fit in the return registers.
2020-07-06 04:15:36 +08:00
; GCN: $sgpr4_sgpr5 = COPY [[COPY11]](p4)
; GCN: $sgpr6_sgpr7 = COPY [[COPY12]](p4)
; GCN: $sgpr8_sgpr9 = COPY [[PTR_ADD1]](p4)
; GCN: $sgpr10_sgpr11 = COPY [[COPY14]](s64)
; GCN: $sgpr12 = COPY [[COPY15]](s32)
; GCN: $sgpr13 = COPY [[COPY16]](s32)
; GCN: $sgpr14 = COPY [[COPY17]](s32)
; GCN: $vgpr31 = COPY [[OR1]](s32)
[GlobalISel][CallLowering] Look through call parameters for flags We weren't looking through the parameters on calls at all. E.g., say you had ``` declare i32 @zext(i32 zeroext %x) ... %y = call i32 @zext(i32 %something) ... ``` At the point of the call, we wouldn't know that the %something should have the zeroext attribute. This sets flags in about the same way as TargetLoweringBase::ArgListEntry::setAttributes. Differential Revision: https://reviews.llvm.org/D86125
2020-08-18 07:42:28 +08:00
; GCN: $sgpr30_sgpr31 = SI_CALL [[GV]](p0), @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32, csr_amdgpu_highregs, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $sgpr4_sgpr5, implicit $sgpr6_sgpr7, implicit $sgpr8_sgpr9, implicit $sgpr10_sgpr11, implicit $sgpr12, implicit $sgpr13, implicit $sgpr14, implicit $vgpr31
; GCN: ADJCALLSTACKDOWN 0, 8, implicit-def $scc
; GCN: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[FRAME_INDEX1]], [[C2]](s32)
AMDGPU/GlobalISel: Handle call return values The only case that I know doesn't work is the implicit sret case when the return type doesn't fit in the return registers.
2020-07-06 04:15:36 +08:00
; GCN: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[FRAME_INDEX1]](p5) :: (dereferenceable load 1 from %ir.out.gep02, addrspace 5)
[GlobalISel][CallLowering] Look through call parameters for flags We weren't looking through the parameters on calls at all. E.g., say you had ``` declare i32 @zext(i32 zeroext %x) ... %y = call i32 @zext(i32 %something) ... ``` At the point of the call, we wouldn't know that the %something should have the zeroext attribute. This sets flags in about the same way as TargetLoweringBase::ArgListEntry::setAttributes. Differential Revision: https://reviews.llvm.org/D86125
2020-08-18 07:42:28 +08:00
; GCN: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD3]](p5) :: (dereferenceable load 4 from %ir.out.gep1, addrspace 5)
AMDGPU/GlobalISel: Handle call return values The only case that I know doesn't work is the implicit sret case when the return type doesn't fit in the return registers.
2020-07-06 04:15:36 +08:00
; GCN: G_STORE [[LOAD]](s8), [[DEF]](p1) :: (volatile store 1 into `i8 addrspace(1)* undef`, addrspace 1)
; GCN: G_STORE [[LOAD1]](s32), [[COPY10]](p1) :: (volatile store 4 into `i32 addrspace(1)* undef`, addrspace 1)
; GCN: S_ENDPGM 0
%in.val = alloca { i8, i32 }, align 4, addrspace(5)
%out.val = alloca { i8, i32 }, align 4, addrspace(5)
%in.gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %in.val, i32 0, i32 0
%in.gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %in.val, i32 0, i32 1
store i8 3, i8 addrspace(5)* %in.gep0
store i32 8, i32 addrspace(5)* %in.gep1
call void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* %out.val, { i8, i32 } addrspace(5)* %in.val)
%out.gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %out.val, i32 0, i32 0
%out.gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %out.val, i32 0, i32 1
%out.val0 = load i8, i8 addrspace(5)* %out.gep0
%out.val1 = load i32, i32 addrspace(5)* %out.gep1
store volatile i8 %out.val0, i8 addrspace(1)* undef
store volatile i32 %out.val1, i32 addrspace(1)* undef
ret void
}