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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir

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GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE32 %s
---
name: fcmp_false_s32_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_false_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[COPY]](s32), [[COPY1]]
; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
; WAVE32-LABEL: name: fcmp_false_s32_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[COPY]](s32), [[COPY1]]
; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(false), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_oeq_s32_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_oeq_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_oeq_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_ogt_s32_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ogt_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_ogt_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_oge_s32_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_oge_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_oge_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(oge), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_olt_s32_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_olt_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_olt_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(olt), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_ole_s32_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ole_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_ole_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ole), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_one_s32_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_one_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_one_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(one), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_ord_s32_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ord_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_ord_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ord), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_uno_s32_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_uno_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_uno_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(uno), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_ueq_s32_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ueq_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_ueq_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_ugt_s32_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ugt_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_ugt_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_uge_s32_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_uge_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_uge_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(uge), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_ult_s32_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ult_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_ult_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ult), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_ule_s32_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_ule_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_ule_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(ule), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_une_s32_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_une_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_une_s32_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(une), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_true_s32_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_true_s32_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[COPY]](s32), [[COPY1]]
; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
; WAVE32-LABEL: name: fcmp_true_s32_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[COPY]](s32), [[COPY1]]
; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(true), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_false_s64_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_false_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[COPY]](s64), [[COPY1]]
; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
; WAVE32-LABEL: name: fcmp_false_s64_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[COPY]](s64), [[COPY1]]
; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(false), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_oeq_s64_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_oeq_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_oeq_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_ogt_s64_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ogt_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_ogt_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_oge_s64_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_oge_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_oge_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(oge), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_olt_s64_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_olt_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_olt_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(olt), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_ole_s64_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ole_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_ole_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ole), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_one_s64_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_one_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_one_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(one), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_ord_s64_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ord_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_ord_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ord), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_uno_s64_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_uno_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_uno_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(uno), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_ueq_s64_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ueq_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_ueq_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_ugt_s64_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ugt_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_ugt_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_uge_s64_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_uge_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_uge_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(uge), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_ult_s64_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ult_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_ult_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ult), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_ule_s64_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_ule_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_ule_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(ule), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_une_s64_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_une_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64 = nofpexcept V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
; WAVE32-LABEL: name: fcmp_une_s64_vv
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32 = nofpexcept V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: S_ENDPGM 0, implicit %2
GlobalISel/TableGen: Handle setcc patterns This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
2019-08-29 09:13:41 +08:00
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(une), %0, %1
S_ENDPGM 0, implicit %2
...
---
name: fcmp_true_s64_vv
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
; WAVE64-LABEL: name: fcmp_true_s64_vv
; WAVE64: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[COPY]](s64), [[COPY1]]
; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
; WAVE32-LABEL: name: fcmp_true_s64_vv
; WAVE32: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[COPY]](s64), [[COPY1]]
; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
%0:vgpr(s64) = COPY $vgpr0_vgpr1
%1:vgpr(s64) = COPY $vgpr2_vgpr3
%2:vcc(s1) = G_FCMP floatpred(true), %0, %1
S_ENDPGM 0, implicit %2
...
AMDGPU/GlobalISel: Replace handling of boolean values This solves selection failures with generated selection patterns, which would fail due to inferring the SGPR reg bank for virtual registers with a set register class instead of VCC bank. Use instruction selection would constrain the virtual register to a specific class, so when the def was selected later the bank no longer was set to VCC. Remove the SCC reg bank. SCC isn't directly addressable, so it requires copying from SCC to an allocatable 32-bit register during selection, so these might as well be treated as 32-bit SGPR values. Now any scalar boolean value that will produce an outupt in SCC should be widened during RegBankSelect to s32. Any s1 value should be a vector boolean during selection. This makes the vcc register bank unambiguous with a normal SGPR during selection. Summary of how this should now work: - G_TRUNC is always a no-op, and never should use a vcc bank result. - SALU boolean operations should be promoted to s32 in RegBankSelect apply mapping - An s1 value means vcc bank at selection. The exception is for legalization artifacts that use s1, which are never VCC. All other contexts should infer the VCC register classes for s1 typed registers. The LLT for the register is now needed to infer the correct register class. Extensions with vcc sources should be legalized to a select of constants during RegBankSelect. - Copy from non-vcc to vcc ensures high bits of the input value are cleared during selection. - SALU boolean inputs should ensure the inputs are 0/1. This includes select, conditional branches, and carry-ins. There are a few somewhat dirty details. One is that G_TRUNC/G_*EXT selection ignores the usual register-bank from register class functions, and can't handle truncates with VCC result banks. I think this is OK, since the artifacts are specially treated anyway. This does require some care to avoid producing cases with vcc. There will also be no 100% reliable way to verify this rule is followed in selection in case of register classes, and violations manifests themselves as invalid copy instructions much later. Standard phi handling also only considers the bank of the result register, and doesn't insert copies to make the source banks match. This doesn't work for vcc, so we have to manually correct phi inputs in this case. We should add a verifier check to make sure there are no phis with mixed vcc and non-vcc register bank inputs. There's also some duplication with the LegalizerHelper, and some code which should live in the helper. I don't see a good way to share special knowledge about what types to use for intermediate operations depending on the bank for example. Using the helper to replace extensions with selects also seems somewhat awkward to me. Another issue is there are some contexts calling getRegBankFromRegClass that apparently don't have the LLT type for the register, but I haven't yet run into a real issue from this. This also introduces new unnecessary instructions in most cases, since we don't yet try to optimize out the zext when the source is known to come from a compare.
2019-11-03 00:30:59 +08:00
---
name: fcmp_oeq_s32_vv_select_user
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
; WAVE64-LABEL: name: fcmp_oeq_s32_vv_select_user
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE64: %2:sreg_64_xexec = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE64: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], %2, implicit $exec
AMDGPU/GlobalISel: Replace handling of boolean values This solves selection failures with generated selection patterns, which would fail due to inferring the SGPR reg bank for virtual registers with a set register class instead of VCC bank. Use instruction selection would constrain the virtual register to a specific class, so when the def was selected later the bank no longer was set to VCC. Remove the SCC reg bank. SCC isn't directly addressable, so it requires copying from SCC to an allocatable 32-bit register during selection, so these might as well be treated as 32-bit SGPR values. Now any scalar boolean value that will produce an outupt in SCC should be widened during RegBankSelect to s32. Any s1 value should be a vector boolean during selection. This makes the vcc register bank unambiguous with a normal SGPR during selection. Summary of how this should now work: - G_TRUNC is always a no-op, and never should use a vcc bank result. - SALU boolean operations should be promoted to s32 in RegBankSelect apply mapping - An s1 value means vcc bank at selection. The exception is for legalization artifacts that use s1, which are never VCC. All other contexts should infer the VCC register classes for s1 typed registers. The LLT for the register is now needed to infer the correct register class. Extensions with vcc sources should be legalized to a select of constants during RegBankSelect. - Copy from non-vcc to vcc ensures high bits of the input value are cleared during selection. - SALU boolean inputs should ensure the inputs are 0/1. This includes select, conditional branches, and carry-ins. There are a few somewhat dirty details. One is that G_TRUNC/G_*EXT selection ignores the usual register-bank from register class functions, and can't handle truncates with VCC result banks. I think this is OK, since the artifacts are specially treated anyway. This does require some care to avoid producing cases with vcc. There will also be no 100% reliable way to verify this rule is followed in selection in case of register classes, and violations manifests themselves as invalid copy instructions much later. Standard phi handling also only considers the bank of the result register, and doesn't insert copies to make the source banks match. This doesn't work for vcc, so we have to manually correct phi inputs in this case. We should add a verifier check to make sure there are no phis with mixed vcc and non-vcc register bank inputs. There's also some duplication with the LegalizerHelper, and some code which should live in the helper. I don't see a good way to share special knowledge about what types to use for intermediate operations depending on the bank for example. Using the helper to replace extensions with selects also seems somewhat awkward to me. Another issue is there are some contexts calling getRegBankFromRegClass that apparently don't have the LLT type for the register, but I haven't yet run into a real issue from this. This also introduces new unnecessary instructions in most cases, since we don't yet try to optimize out the zext when the source is known to come from a compare.
2019-11-03 00:30:59 +08:00
; WAVE64: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
; WAVE32-LABEL: name: fcmp_oeq_s32_vv_select_user
; WAVE32: $vcc_hi = IMPLICIT_DEF
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
GlobalISel: Infer nofpexcept flag during selection for non-strict ops Match SelectionDAG's behavior of adding nofpexcept to out instructions that may raise fp exceptions that are selected from instructions that do not.
2020-06-01 02:19:46 +08:00
; WAVE32: %2:sreg_32_xm0_xexec = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $mode, implicit $exec
; WAVE32: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY1]], 0, [[COPY]], %2, implicit $exec
AMDGPU/GlobalISel: Replace handling of boolean values This solves selection failures with generated selection patterns, which would fail due to inferring the SGPR reg bank for virtual registers with a set register class instead of VCC bank. Use instruction selection would constrain the virtual register to a specific class, so when the def was selected later the bank no longer was set to VCC. Remove the SCC reg bank. SCC isn't directly addressable, so it requires copying from SCC to an allocatable 32-bit register during selection, so these might as well be treated as 32-bit SGPR values. Now any scalar boolean value that will produce an outupt in SCC should be widened during RegBankSelect to s32. Any s1 value should be a vector boolean during selection. This makes the vcc register bank unambiguous with a normal SGPR during selection. Summary of how this should now work: - G_TRUNC is always a no-op, and never should use a vcc bank result. - SALU boolean operations should be promoted to s32 in RegBankSelect apply mapping - An s1 value means vcc bank at selection. The exception is for legalization artifacts that use s1, which are never VCC. All other contexts should infer the VCC register classes for s1 typed registers. The LLT for the register is now needed to infer the correct register class. Extensions with vcc sources should be legalized to a select of constants during RegBankSelect. - Copy from non-vcc to vcc ensures high bits of the input value are cleared during selection. - SALU boolean inputs should ensure the inputs are 0/1. This includes select, conditional branches, and carry-ins. There are a few somewhat dirty details. One is that G_TRUNC/G_*EXT selection ignores the usual register-bank from register class functions, and can't handle truncates with VCC result banks. I think this is OK, since the artifacts are specially treated anyway. This does require some care to avoid producing cases with vcc. There will also be no 100% reliable way to verify this rule is followed in selection in case of register classes, and violations manifests themselves as invalid copy instructions much later. Standard phi handling also only considers the bank of the result register, and doesn't insert copies to make the source banks match. This doesn't work for vcc, so we have to manually correct phi inputs in this case. We should add a verifier check to make sure there are no phis with mixed vcc and non-vcc register bank inputs. There's also some duplication with the LegalizerHelper, and some code which should live in the helper. I don't see a good way to share special knowledge about what types to use for intermediate operations depending on the bank for example. Using the helper to replace extensions with selects also seems somewhat awkward to me. Another issue is there are some contexts calling getRegBankFromRegClass that apparently don't have the LLT type for the register, but I haven't yet run into a real issue from this. This also introduces new unnecessary instructions in most cases, since we don't yet try to optimize out the zext when the source is known to come from a compare.
2019-11-03 00:30:59 +08:00
; WAVE32: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
%3:vgpr(s32) = G_SELECT %2, %0, %1
S_ENDPGM 0, implicit %3
...