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llvm-project/llvm/test/CodeGen/X86/pr34080.ll

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[X86][X87] Add test case for PR34080 Test with/without the sandybridge (default) model for SSE2, SSE3 and AVX targets. pre-SSE3 the issue is the order of the fpsw and fpcw load/stores (with SSE3 trunc-store FIST instructions avoid the sw/cw manipulations). llvm-svn: 310198
2017-08-06 19:22:33 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 | FileCheck %s --check-prefix=SSE2
[X86][X87] Renamed CHECK prefix, its not actually broken anymore just scheduled differently llvm-svn: 321423
2017-12-24 18:25:01 +08:00
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 -mcpu=x86-64 | FileCheck %s --check-prefix=SSE2-SCHEDULE
[X86][X87] Add test case for PR34080 Test with/without the sandybridge (default) model for SSE2, SSE3 and AVX targets. pre-SSE3 the issue is the order of the fpsw and fpcw load/stores (with SSE3 trunc-store FIST instructions avoid the sw/cw manipulations). llvm-svn: 310198
2017-08-06 19:22:33 +08:00
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse3 | FileCheck %s --check-prefix=SSE3
[X86] Make Feature64Bit useful We now only add +64bit to the CPU string for "generic" CPU. All other CPU names are assumed to have the feature flag already set if they support 64-bit. I've remove the implies from CMPXCHG8 so that Feature64Bit only comes in via CPUs or user passing -mattr=+64bit. I've changed the assert to a report_fatal_error so it's not lost in Release builds. The test updates are to fix things that tripped the new error. Differential Revision: https://reviews.llvm.org/D51231 llvm-svn: 341022
2018-08-30 14:01:05 +08:00
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse3 -mcpu=nocona | FileCheck %s --check-prefix=SSE3
[X86][X87] Add test case for PR34080 Test with/without the sandybridge (default) model for SSE2, SSE3 and AVX targets. pre-SSE3 the issue is the order of the fpsw and fpcw load/stores (with SSE3 trunc-store FIST instructions avoid the sw/cw manipulations). llvm-svn: 310198
2017-08-06 19:22:33 +08:00
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx | FileCheck %s --check-prefix=AVX
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+avx -mcpu=sandybridge | FileCheck %s --check-prefix=AVX
define void @_Z1fe(x86_fp80 %z) local_unnamed_addr #0 {
; SSE2-LABEL: _Z1fe:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SSE2: ## %bb.0: ## %entry
[X86][X87] Add test case for PR34080 Test with/without the sandybridge (default) model for SSE2, SSE3 and AVX targets. pre-SSE3 the issue is the order of the fpsw and fpcw load/stores (with SSE3 trunc-store FIST instructions avoid the sw/cw manipulations). llvm-svn: 310198
2017-08-06 19:22:33 +08:00
; SSE2-NEXT: pushq %rbp
; SSE2-NEXT: .cfi_def_cfa_offset 16
; SSE2-NEXT: .cfi_offset %rbp, -16
; SSE2-NEXT: movq %rsp, %rbp
; SSE2-NEXT: .cfi_def_cfa_register %rbp
; SSE2-NEXT: fldt 16(%rbp)
; SSE2-NEXT: fnstcw -4(%rbp)
; SSE2-NEXT: movzwl -4(%rbp), %eax
; SSE2-NEXT: movw $3199, -4(%rbp) ## imm = 0xC7F
; SSE2-NEXT: fldcw -4(%rbp)
; SSE2-NEXT: movw %ax, -4(%rbp)
; SSE2-NEXT: fistl -8(%rbp)
; SSE2-NEXT: fldcw -4(%rbp)
; SSE2-NEXT: cvtsi2sdl -8(%rbp), %xmm0
; SSE2-NEXT: movsd %xmm0, -64(%rbp)
; SSE2-NEXT: movsd %xmm0, -32(%rbp)
; SSE2-NEXT: fsubl -32(%rbp)
; SSE2-NEXT: flds {{.*}}(%rip)
[X86] Print %st(0) as %st when its implicit to the instruction. Continue printing it as %st(0) when its encoded in the instruction. This is a step back from the change I made in r352985. This appears to be more consistent with gcc and objdump behavior. llvm-svn: 353015
2019-02-04 12:15:10 +08:00
; SSE2-NEXT: fmul %st, %st(1)
[X86][X87] Add test case for PR34080 Test with/without the sandybridge (default) model for SSE2, SSE3 and AVX targets. pre-SSE3 the issue is the order of the fpsw and fpcw load/stores (with SSE3 trunc-store FIST instructions avoid the sw/cw manipulations). llvm-svn: 310198
2017-08-06 19:22:33 +08:00
; SSE2-NEXT: fnstcw -2(%rbp)
; SSE2-NEXT: movzwl -2(%rbp), %eax
; SSE2-NEXT: movw $3199, -2(%rbp) ## imm = 0xC7F
; SSE2-NEXT: fldcw -2(%rbp)
; SSE2-NEXT: movw %ax, -2(%rbp)
; SSE2-NEXT: fxch %st(1)
; SSE2-NEXT: fistl -12(%rbp)
; SSE2-NEXT: fldcw -2(%rbp)
; SSE2-NEXT: xorps %xmm0, %xmm0
; SSE2-NEXT: cvtsi2sdl -12(%rbp), %xmm0
; SSE2-NEXT: movsd %xmm0, -56(%rbp)
; SSE2-NEXT: movsd %xmm0, -24(%rbp)
; SSE2-NEXT: fsubl -24(%rbp)
; SSE2-NEXT: fmulp %st(1)
; SSE2-NEXT: fstpl -48(%rbp)
; SSE2-NEXT: popq %rbp
; SSE2-NEXT: retq
;
[X86][X87] Renamed CHECK prefix, its not actually broken anymore just scheduled differently llvm-svn: 321423
2017-12-24 18:25:01 +08:00
; SSE2-SCHEDULE-LABEL: _Z1fe:
; SSE2-SCHEDULE: ## %bb.0: ## %entry
; SSE2-SCHEDULE-NEXT: pushq %rbp
; SSE2-SCHEDULE-NEXT: .cfi_def_cfa_offset 16
; SSE2-SCHEDULE-NEXT: .cfi_offset %rbp, -16
; SSE2-SCHEDULE-NEXT: movq %rsp, %rbp
; SSE2-SCHEDULE-NEXT: .cfi_def_cfa_register %rbp
; SSE2-SCHEDULE-NEXT: fnstcw -4(%rbp)
; SSE2-SCHEDULE-NEXT: movzwl -4(%rbp), %eax
; SSE2-SCHEDULE-NEXT: movw $3199, -4(%rbp) ## imm = 0xC7F
; SSE2-SCHEDULE-NEXT: fldcw -4(%rbp)
[X86] Remove some InstRWs for plain store instructions on Sandy Bridge. We were forcing the latency of these instructions to 5 cycles, but every other scheduler model had them as 1 cycle. I'm sure I didn't get everything, but this gets a big portion. llvm-svn: 329339
2018-04-06 04:04:06 +08:00
; SSE2-SCHEDULE-NEXT: fldt 16(%rbp)
[X86][X87] Renamed CHECK prefix, its not actually broken anymore just scheduled differently llvm-svn: 321423
2017-12-24 18:25:01 +08:00
; SSE2-SCHEDULE-NEXT: movw %ax, -4(%rbp)
; SSE2-SCHEDULE-NEXT: fistl -8(%rbp)
; SSE2-SCHEDULE-NEXT: fldcw -4(%rbp)
; SSE2-SCHEDULE-NEXT: cvtsi2sdl -8(%rbp), %xmm0
; SSE2-SCHEDULE-NEXT: movsd %xmm0, -64(%rbp)
; SSE2-SCHEDULE-NEXT: movsd %xmm0, -32(%rbp)
; SSE2-SCHEDULE-NEXT: fsubl -32(%rbp)
[X86] Revert r329251-329254 It's failing on the bots and I'm not sure why. This reverts: [X86] Synchronize the SchedRW on some EVEX instructions with their VEX equivalents. [X86] Use WriteFShuffle256 for VEXTRACTF128 to be consistent with VEXTRACTI128 which uses WriteShuffle256. [X86] Remove some InstRWs for plain store instructions on Sandy Bridge. [X86] Auto-generate complete checks. NFC llvm-svn: 329256
2018-04-05 13:19:36 +08:00
; SSE2-SCHEDULE-NEXT: fnstcw -2(%rbp)
[X86] Remove some InstRWs for plain store instructions on Sandy Bridge. We were forcing the latency of these instructions to 5 cycles, but every other scheduler model had them as 1 cycle. I'm sure I didn't get everything, but this gets a big portion. llvm-svn: 329339
2018-04-06 04:04:06 +08:00
; SSE2-SCHEDULE-NEXT: flds {{.*}}(%rip)
[X86][X87] Renamed CHECK prefix, its not actually broken anymore just scheduled differently llvm-svn: 321423
2017-12-24 18:25:01 +08:00
; SSE2-SCHEDULE-NEXT: movzwl -2(%rbp), %eax
; SSE2-SCHEDULE-NEXT: movw $3199, -2(%rbp) ## imm = 0xC7F
; SSE2-SCHEDULE-NEXT: fldcw -2(%rbp)
[X86] Print %st(0) as %st when its implicit to the instruction. Continue printing it as %st(0) when its encoded in the instruction. This is a step back from the change I made in r352985. This appears to be more consistent with gcc and objdump behavior. llvm-svn: 353015
2019-02-04 12:15:10 +08:00
; SSE2-SCHEDULE-NEXT: fmul %st, %st(1)
[X86][X87] Renamed CHECK prefix, its not actually broken anymore just scheduled differently llvm-svn: 321423
2017-12-24 18:25:01 +08:00
; SSE2-SCHEDULE-NEXT: movw %ax, -2(%rbp)
; SSE2-SCHEDULE-NEXT: fxch %st(1)
; SSE2-SCHEDULE-NEXT: fistl -12(%rbp)
; SSE2-SCHEDULE-NEXT: fldcw -2(%rbp)
; SSE2-SCHEDULE-NEXT: xorps %xmm0, %xmm0
; SSE2-SCHEDULE-NEXT: cvtsi2sdl -12(%rbp), %xmm0
; SSE2-SCHEDULE-NEXT: movsd %xmm0, -56(%rbp)
; SSE2-SCHEDULE-NEXT: movsd %xmm0, -24(%rbp)
; SSE2-SCHEDULE-NEXT: fsubl -24(%rbp)
; SSE2-SCHEDULE-NEXT: fmulp %st(1)
; SSE2-SCHEDULE-NEXT: fstpl -48(%rbp)
; SSE2-SCHEDULE-NEXT: popq %rbp
; SSE2-SCHEDULE-NEXT: retq
[X86][X87] Add test case for PR34080 Test with/without the sandybridge (default) model for SSE2, SSE3 and AVX targets. pre-SSE3 the issue is the order of the fpsw and fpcw load/stores (with SSE3 trunc-store FIST instructions avoid the sw/cw manipulations). llvm-svn: 310198
2017-08-06 19:22:33 +08:00
;
; SSE3-LABEL: _Z1fe:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; SSE3: ## %bb.0: ## %entry
[X86][X87] Add test case for PR34080 Test with/without the sandybridge (default) model for SSE2, SSE3 and AVX targets. pre-SSE3 the issue is the order of the fpsw and fpcw load/stores (with SSE3 trunc-store FIST instructions avoid the sw/cw manipulations). llvm-svn: 310198
2017-08-06 19:22:33 +08:00
; SSE3-NEXT: pushq %rbp
; SSE3-NEXT: .cfi_def_cfa_offset 16
; SSE3-NEXT: .cfi_offset %rbp, -16
; SSE3-NEXT: movq %rsp, %rbp
; SSE3-NEXT: .cfi_def_cfa_register %rbp
; SSE3-NEXT: fldt 16(%rbp)
Revert r352985 "[X86] Print %st(0) as %st to match what gcc inline asm uses as the clobber name to make MS inline asm work correctly" Looking into gcc and objdump behavior more this was overly aggressive. If the register is encoded in the instruction we should print %st(0), if its implicit we should print %st. I'll be making a more directed change in a future patch. llvm-svn: 353013
2019-02-04 12:15:02 +08:00
; SSE3-NEXT: fld %st(0)
[X86][X87] Add test case for PR34080 Test with/without the sandybridge (default) model for SSE2, SSE3 and AVX targets. pre-SSE3 the issue is the order of the fpsw and fpcw load/stores (with SSE3 trunc-store FIST instructions avoid the sw/cw manipulations). llvm-svn: 310198
2017-08-06 19:22:33 +08:00
; SSE3-NEXT: fisttpl -4(%rbp)
; SSE3-NEXT: cvtsi2sdl -4(%rbp), %xmm0
; SSE3-NEXT: movsd %xmm0, -48(%rbp)
; SSE3-NEXT: movsd %xmm0, -24(%rbp)
; SSE3-NEXT: fsubl -24(%rbp)
; SSE3-NEXT: flds {{.*}}(%rip)
[X86] Print %st(0) as %st when its implicit to the instruction. Continue printing it as %st(0) when its encoded in the instruction. This is a step back from the change I made in r352985. This appears to be more consistent with gcc and objdump behavior. llvm-svn: 353015
2019-02-04 12:15:10 +08:00
; SSE3-NEXT: fmul %st, %st(1)
[X86][X87] Add test case for PR34080 Test with/without the sandybridge (default) model for SSE2, SSE3 and AVX targets. pre-SSE3 the issue is the order of the fpsw and fpcw load/stores (with SSE3 trunc-store FIST instructions avoid the sw/cw manipulations). llvm-svn: 310198
2017-08-06 19:22:33 +08:00
; SSE3-NEXT: fld %st(1)
; SSE3-NEXT: fisttpl -8(%rbp)
; SSE3-NEXT: xorps %xmm0, %xmm0
; SSE3-NEXT: cvtsi2sdl -8(%rbp), %xmm0
; SSE3-NEXT: movsd %xmm0, -40(%rbp)
; SSE3-NEXT: movsd %xmm0, -16(%rbp)
; SSE3-NEXT: fxch %st(1)
; SSE3-NEXT: fsubl -16(%rbp)
; SSE3-NEXT: fmulp %st(1)
; SSE3-NEXT: fstpl -32(%rbp)
; SSE3-NEXT: popq %rbp
; SSE3-NEXT: retq
;
; AVX-LABEL: _Z1fe:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; AVX: ## %bb.0: ## %entry
[X86][X87] Add test case for PR34080 Test with/without the sandybridge (default) model for SSE2, SSE3 and AVX targets. pre-SSE3 the issue is the order of the fpsw and fpcw load/stores (with SSE3 trunc-store FIST instructions avoid the sw/cw manipulations). llvm-svn: 310198
2017-08-06 19:22:33 +08:00
; AVX-NEXT: pushq %rbp
; AVX-NEXT: .cfi_def_cfa_offset 16
; AVX-NEXT: .cfi_offset %rbp, -16
; AVX-NEXT: movq %rsp, %rbp
; AVX-NEXT: .cfi_def_cfa_register %rbp
; AVX-NEXT: fldt 16(%rbp)
Revert r352985 "[X86] Print %st(0) as %st to match what gcc inline asm uses as the clobber name to make MS inline asm work correctly" Looking into gcc and objdump behavior more this was overly aggressive. If the register is encoded in the instruction we should print %st(0), if its implicit we should print %st. I'll be making a more directed change in a future patch. llvm-svn: 353013
2019-02-04 12:15:02 +08:00
; AVX-NEXT: fld %st(0)
[X86][X87] Add test case for PR34080 Test with/without the sandybridge (default) model for SSE2, SSE3 and AVX targets. pre-SSE3 the issue is the order of the fpsw and fpcw load/stores (with SSE3 trunc-store FIST instructions avoid the sw/cw manipulations). llvm-svn: 310198
2017-08-06 19:22:33 +08:00
; AVX-NEXT: fisttpl -4(%rbp)
; AVX-NEXT: vcvtsi2sdl -4(%rbp), %xmm0, %xmm0
; AVX-NEXT: vmovsd %xmm0, -48(%rbp)
; AVX-NEXT: vmovsd %xmm0, -24(%rbp)
; AVX-NEXT: fsubl -24(%rbp)
; AVX-NEXT: flds {{.*}}(%rip)
[X86] Print %st(0) as %st when its implicit to the instruction. Continue printing it as %st(0) when its encoded in the instruction. This is a step back from the change I made in r352985. This appears to be more consistent with gcc and objdump behavior. llvm-svn: 353015
2019-02-04 12:15:10 +08:00
; AVX-NEXT: fmul %st, %st(1)
[X86][X87] Add test case for PR34080 Test with/without the sandybridge (default) model for SSE2, SSE3 and AVX targets. pre-SSE3 the issue is the order of the fpsw and fpcw load/stores (with SSE3 trunc-store FIST instructions avoid the sw/cw manipulations). llvm-svn: 310198
2017-08-06 19:22:33 +08:00
; AVX-NEXT: fld %st(1)
; AVX-NEXT: fisttpl -8(%rbp)
; AVX-NEXT: vcvtsi2sdl -8(%rbp), %xmm1, %xmm0
; AVX-NEXT: vmovsd %xmm0, -40(%rbp)
; AVX-NEXT: vmovsd %xmm0, -16(%rbp)
; AVX-NEXT: fxch %st(1)
; AVX-NEXT: fsubl -16(%rbp)
; AVX-NEXT: fmulp %st(1)
; AVX-NEXT: fstpl -32(%rbp)
; AVX-NEXT: popq %rbp
; AVX-NEXT: retq
entry:
%tx = alloca [3 x double], align 16
%0 = bitcast [3 x double]* %tx to i8*
%conv = fptosi x86_fp80 %z to i32
%conv1 = sitofp i32 %conv to double
%arrayidx = getelementptr inbounds [3 x double], [3 x double]* %tx, i64 0, i64 0
store double %conv1, double* %arrayidx, align 16
%conv4 = fpext double %conv1 to x86_fp80
%sub = fsub x86_fp80 %z, %conv4
%mul = fmul x86_fp80 %sub, 0xK40178000000000000000
%conv.1 = fptosi x86_fp80 %mul to i32
%conv1.1 = sitofp i32 %conv.1 to double
%arrayidx.1 = getelementptr inbounds [3 x double], [3 x double]* %tx, i64 0, i64 1
store double %conv1.1, double* %arrayidx.1, align 8
%conv4.1 = fpext double %conv1.1 to x86_fp80
%sub.1 = fsub x86_fp80 %mul, %conv4.1
%mul.1 = fmul x86_fp80 %sub.1, 0xK40178000000000000000
%conv5 = fptrunc x86_fp80 %mul.1 to double
%arrayidx6 = getelementptr inbounds [3 x double], [3 x double]* %tx, i64 0, i64 2
store double %conv5, double* %arrayidx6, align 16
ret void
}
attributes #0 = { noinline uwtable "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }