2016-02-19 05:38:19 +08:00
|
|
|
//===-------- LoopDataPrefetch.cpp - Loop Data Prefetching Pass -----------===//
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
//
|
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
|
//
|
|
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
|
// License. See LICENSE.TXT for details.
|
|
|
|
|
//
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
//
|
|
|
|
|
// This file implements a Loop Data Prefetching Pass.
|
|
|
|
|
//
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
2016-08-13 12:11:27 +08:00
|
|
|
#include "llvm/Transforms/Scalar/LoopDataPrefetch.h"
|
|
|
|
|
|
2016-02-19 05:37:12 +08:00
|
|
|
#define DEBUG_TYPE "loop-data-prefetch"
|
2015-04-10 23:05:02 +08:00
|
|
|
#include "llvm/ADT/DepthFirstIterator.h"
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
#include "llvm/ADT/Statistic.h"
|
|
|
|
|
#include "llvm/Analysis/AssumptionCache.h"
|
|
|
|
|
#include "llvm/Analysis/CodeMetrics.h"
|
|
|
|
|
#include "llvm/Analysis/InstructionSimplify.h"
|
|
|
|
|
#include "llvm/Analysis/LoopInfo.h"
|
2016-07-23 06:53:17 +08:00
|
|
|
#include "llvm/Analysis/OptimizationDiagnosticInfo.h"
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
#include "llvm/Analysis/ScalarEvolution.h"
|
[PM/AA] Rebuild LLVM's alias analysis infrastructure in a way compatible
with the new pass manager, and no longer relying on analysis groups.
This builds essentially a ground-up new AA infrastructure stack for
LLVM. The core ideas are the same that are used throughout the new pass
manager: type erased polymorphism and direct composition. The design is
as follows:
- FunctionAAResults is a type-erasing alias analysis results aggregation
interface to walk a single query across a range of results from
different alias analyses. Currently this is function-specific as we
always assume that aliasing queries are *within* a function.
- AAResultBase is a CRTP utility providing stub implementations of
various parts of the alias analysis result concept, notably in several
cases in terms of other more general parts of the interface. This can
be used to implement only a narrow part of the interface rather than
the entire interface. This isn't really ideal, this logic should be
hoisted into FunctionAAResults as currently it will cause
a significant amount of redundant work, but it faithfully models the
behavior of the prior infrastructure.
- All the alias analysis passes are ported to be wrapper passes for the
legacy PM and new-style analysis passes for the new PM with a shared
result object. In some cases (most notably CFL), this is an extremely
naive approach that we should revisit when we can specialize for the
new pass manager.
- BasicAA has been restructured to reflect that it is much more
fundamentally a function analysis because it uses dominator trees and
loop info that need to be constructed for each function.
All of the references to getting alias analysis results have been
updated to use the new aggregation interface. All the preservation and
other pass management code has been updated accordingly.
The way the FunctionAAResultsWrapperPass works is to detect the
available alias analyses when run, and add them to the results object.
This means that we should be able to continue to respect when various
passes are added to the pipeline, for example adding CFL or adding TBAA
passes should just cause their results to be available and to get folded
into this. The exception to this rule is BasicAA which really needs to
be a function pass due to using dominator trees and loop info. As
a consequence, the FunctionAAResultsWrapperPass directly depends on
BasicAA and always includes it in the aggregation.
This has significant implications for preserving analyses. Generally,
most passes shouldn't bother preserving FunctionAAResultsWrapperPass
because rebuilding the results just updates the set of known AA passes.
The exception to this rule are LoopPass instances which need to preserve
all the function analyses that the loop pass manager will end up
needing. This means preserving both BasicAAWrapperPass and the
aggregating FunctionAAResultsWrapperPass.
Now, when preserving an alias analysis, you do so by directly preserving
that analysis. This is only necessary for non-immutable-pass-provided
alias analyses though, and there are only three of interest: BasicAA,
GlobalsAA (formerly GlobalsModRef), and SCEVAA. Usually BasicAA is
preserved when needed because it (like DominatorTree and LoopInfo) is
marked as a CFG-only pass. I've expanded GlobalsAA into the preserved
set everywhere we previously were preserving all of AliasAnalysis, and
I've added SCEVAA in the intersection of that with where we preserve
SCEV itself.
One significant challenge to all of this is that the CGSCC passes were
actually using the alias analysis implementations by taking advantage of
a pretty amazing set of loop holes in the old pass manager's analysis
management code which allowed analysis groups to slide through in many
cases. Moving away from analysis groups makes this problem much more
obvious. To fix it, I've leveraged the flexibility the design of the new
PM components provides to just directly construct the relevant alias
analyses for the relevant functions in the IPO passes that need them.
This is a bit hacky, but should go away with the new pass manager, and
is already in many ways cleaner than the prior state.
Another significant challenge is that various facilities of the old
alias analysis infrastructure just don't fit any more. The most
significant of these is the alias analysis 'counter' pass. That pass
relied on the ability to snoop on AA queries at different points in the
analysis group chain. Instead, I'm planning to build printing
functionality directly into the aggregation layer. I've not included
that in this patch merely to keep it smaller.
Note that all of this needs a nearly complete rewrite of the AA
documentation. I'm planning to do that, but I'd like to make sure the
new design settles, and to flesh out a bit more of what it looks like in
the new pass manager first.
Differential Revision: http://reviews.llvm.org/D12080
llvm-svn: 247167
2015-09-10 01:55:00 +08:00
|
|
|
#include "llvm/Analysis/ScalarEvolutionAliasAnalysis.h"
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
#include "llvm/Analysis/ScalarEvolutionExpander.h"
|
|
|
|
|
#include "llvm/Analysis/ScalarEvolutionExpressions.h"
|
|
|
|
|
#include "llvm/Analysis/TargetTransformInfo.h"
|
|
|
|
|
#include "llvm/Analysis/ValueTracking.h"
|
|
|
|
|
#include "llvm/IR/CFG.h"
|
|
|
|
|
#include "llvm/IR/Dominators.h"
|
|
|
|
|
#include "llvm/IR/Function.h"
|
|
|
|
|
#include "llvm/IR/IntrinsicInst.h"
|
|
|
|
|
#include "llvm/IR/Module.h"
|
|
|
|
|
#include "llvm/Support/CommandLine.h"
|
|
|
|
|
#include "llvm/Support/Debug.h"
|
2016-07-23 06:53:12 +08:00
|
|
|
#include "llvm/Transforms/Scalar.h"
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
#include "llvm/Transforms/Utils/BasicBlockUtils.h"
|
|
|
|
|
#include "llvm/Transforms/Utils/Local.h"
|
|
|
|
|
#include "llvm/Transforms/Utils/ValueMapper.h"
|
|
|
|
|
using namespace llvm;
|
|
|
|
|
|
|
|
|
|
// By default, we limit this to creating 16 PHIs (which is a little over half
|
|
|
|
|
// of the allocatable register set).
|
|
|
|
|
static cl::opt<bool>
|
2016-02-19 05:37:12 +08:00
|
|
|
PrefetchWrites("loop-prefetch-writes", cl::Hidden, cl::init(false),
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
cl::desc("Prefetch write addresses"));
|
|
|
|
|
|
2016-03-30 07:45:52 +08:00
|
|
|
static cl::opt<unsigned>
|
|
|
|
|
PrefetchDistance("prefetch-distance",
|
|
|
|
|
cl::desc("Number of instructions to prefetch ahead"),
|
|
|
|
|
cl::Hidden);
|
|
|
|
|
|
|
|
|
|
static cl::opt<unsigned>
|
|
|
|
|
MinPrefetchStride("min-prefetch-stride",
|
|
|
|
|
cl::desc("Min stride to add prefetches"), cl::Hidden);
|
|
|
|
|
|
|
|
|
|
static cl::opt<unsigned> MaxPrefetchIterationsAhead(
|
|
|
|
|
"max-prefetch-iters-ahead",
|
|
|
|
|
cl::desc("Max number of iterations to prefetch ahead"), cl::Hidden);
|
|
|
|
|
|
2016-03-09 13:33:21 +08:00
|
|
|
STATISTIC(NumPrefetches, "Number of prefetches inserted");
|
|
|
|
|
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
namespace {
|
|
|
|
|
|
2016-08-13 12:11:27 +08:00
|
|
|
/// Loop prefetch implementation class.
|
|
|
|
|
class LoopDataPrefetch {
|
|
|
|
|
public:
|
|
|
|
|
LoopDataPrefetch(AssumptionCache *AC, LoopInfo *LI, ScalarEvolution *SE,
|
|
|
|
|
const TargetTransformInfo *TTI,
|
|
|
|
|
OptimizationRemarkEmitter *ORE)
|
|
|
|
|
: AC(AC), LI(LI), SE(SE), TTI(TTI), ORE(ORE) {}
|
|
|
|
|
|
|
|
|
|
bool run();
|
|
|
|
|
|
|
|
|
|
private:
|
|
|
|
|
bool runOnLoop(Loop *L);
|
|
|
|
|
|
|
|
|
|
/// \brief Check if the the stride of the accesses is large enough to
|
|
|
|
|
/// warrant a prefetch.
|
|
|
|
|
bool isStrideLargeEnough(const SCEVAddRecExpr *AR);
|
|
|
|
|
|
|
|
|
|
unsigned getMinPrefetchStride() {
|
|
|
|
|
if (MinPrefetchStride.getNumOccurrences() > 0)
|
|
|
|
|
return MinPrefetchStride;
|
|
|
|
|
return TTI->getMinPrefetchStride();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
unsigned getPrefetchDistance() {
|
|
|
|
|
if (PrefetchDistance.getNumOccurrences() > 0)
|
|
|
|
|
return PrefetchDistance;
|
|
|
|
|
return TTI->getPrefetchDistance();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
unsigned getMaxPrefetchIterationsAhead() {
|
|
|
|
|
if (MaxPrefetchIterationsAhead.getNumOccurrences() > 0)
|
|
|
|
|
return MaxPrefetchIterationsAhead;
|
|
|
|
|
return TTI->getMaxPrefetchIterationsAhead();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
AssumptionCache *AC;
|
|
|
|
|
LoopInfo *LI;
|
|
|
|
|
ScalarEvolution *SE;
|
|
|
|
|
const TargetTransformInfo *TTI;
|
|
|
|
|
OptimizationRemarkEmitter *ORE;
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
/// Legacy class for inserting loop data prefetches.
|
|
|
|
|
class LoopDataPrefetchLegacyPass : public FunctionPass {
|
|
|
|
|
public:
|
|
|
|
|
static char ID; // Pass ID, replacement for typeid
|
|
|
|
|
LoopDataPrefetchLegacyPass() : FunctionPass(ID) {
|
|
|
|
|
initializeLoopDataPrefetchLegacyPassPass(*PassRegistry::getPassRegistry());
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void getAnalysisUsage(AnalysisUsage &AU) const override {
|
|
|
|
|
AU.addRequired<AssumptionCacheTracker>();
|
|
|
|
|
AU.addPreserved<DominatorTreeWrapperPass>();
|
|
|
|
|
AU.addRequired<LoopInfoWrapperPass>();
|
|
|
|
|
AU.addPreserved<LoopInfoWrapperPass>();
|
|
|
|
|
AU.addRequired<OptimizationRemarkEmitterWrapperPass>();
|
|
|
|
|
AU.addRequired<ScalarEvolutionWrapperPass>();
|
|
|
|
|
// FIXME: For some reason, preserving SE here breaks LSR (even if
|
|
|
|
|
// this pass changes nothing).
|
|
|
|
|
// AU.addPreserved<ScalarEvolutionWrapperPass>();
|
|
|
|
|
AU.addRequired<TargetTransformInfoWrapperPass>();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool runOnFunction(Function &F) override;
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
};
|
2015-06-23 17:49:53 +08:00
|
|
|
}
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
|
2016-08-13 12:11:27 +08:00
|
|
|
char LoopDataPrefetchLegacyPass::ID = 0;
|
|
|
|
|
INITIALIZE_PASS_BEGIN(LoopDataPrefetchLegacyPass, "loop-data-prefetch",
|
2016-02-19 05:37:12 +08:00
|
|
|
"Loop Data Prefetch", false, false)
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
INITIALIZE_PASS_DEPENDENCY(AssumptionCacheTracker)
|
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(TargetTransformInfoWrapperPass)
|
|
|
|
|
INITIALIZE_PASS_DEPENDENCY(LoopInfoWrapperPass)
|
2016-07-23 06:53:17 +08:00
|
|
|
INITIALIZE_PASS_DEPENDENCY(OptimizationRemarkEmitterWrapperPass)
|
[PM] Port ScalarEvolution to the new pass manager.
This change makes ScalarEvolution a stand-alone object and just produces
one from a pass as needed. Making this work well requires making the
object movable, using references instead of overwritten pointers in
a number of places, and other refactorings.
I've also wired it up to the new pass manager and added a RUN line to
a test to exercise it under the new pass manager. This includes basic
printing support much like with other analyses.
But there is a big and somewhat scary change here. Prior to this patch
ScalarEvolution was never *actually* invalidated!!! Re-running the pass
just re-wired up the various other analyses and didn't remove any of the
existing entries in the SCEV caches or clear out anything at all. This
might seem OK as everything in SCEV that can uses ValueHandles to track
updates to the values that serve as SCEV keys. However, this still means
that as we ran SCEV over each function in the module, we kept
accumulating more and more SCEVs into the cache. At the end, we would
have a SCEV cache with every value that we ever needed a SCEV for in the
entire module!!! Yowzers. The releaseMemory routine would dump all of
this, but that isn't realy called during normal runs of the pipeline as
far as I can see.
To make matters worse, there *is* actually a key that we don't update
with value handles -- there is a map keyed off of Loop*s. Because
LoopInfo *does* release its memory from run to run, it is entirely
possible to run SCEV over one function, then over another function, and
then lookup a Loop* from the second function but find an entry inserted
for the first function! Ouch.
To make matters still worse, there are plenty of updates that *don't*
trip a value handle. It seems incredibly unlikely that today GVN or
another pass that invalidates SCEV can update values in *just* such
a way that a subsequent run of SCEV will incorrectly find lookups in
a cache, but it is theoretically possible and would be a nightmare to
debug.
With this refactoring, I've fixed all this by actually destroying and
recreating the ScalarEvolution object from run to run. Technically, this
could increase the amount of malloc traffic we see, but then again it is
also technically correct. ;] I don't actually think we're suffering from
tons of malloc traffic from SCEV because if we were, the fact that we
never clear the memory would seem more likely to have come up as an
actual problem before now. So, I've made the simple fix here. If in fact
there are serious issues with too much allocation and deallocation,
I can work on a clever fix that preserves the allocations (while
clearing the data) between each run, but I'd prefer to do that kind of
optimization with a test case / benchmark that shows why we need such
cleverness (and that can test that we actually make it faster). It's
possible that this will make some things faster by making the SCEV
caches have higher locality (due to being significantly smaller) so
until there is a clear benchmark, I think the simple change is best.
Differential Revision: http://reviews.llvm.org/D12063
llvm-svn: 245193
2015-08-17 10:08:17 +08:00
|
|
|
INITIALIZE_PASS_DEPENDENCY(ScalarEvolutionWrapperPass)
|
2016-08-13 12:11:27 +08:00
|
|
|
INITIALIZE_PASS_END(LoopDataPrefetchLegacyPass, "loop-data-prefetch",
|
2016-02-19 05:37:12 +08:00
|
|
|
"Loop Data Prefetch", false, false)
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
|
2016-08-13 12:11:27 +08:00
|
|
|
FunctionPass *llvm::createLoopDataPrefetchPass() {
|
|
|
|
|
return new LoopDataPrefetchLegacyPass();
|
|
|
|
|
}
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
|
2016-03-18 08:27:38 +08:00
|
|
|
bool LoopDataPrefetch::isStrideLargeEnough(const SCEVAddRecExpr *AR) {
|
2016-03-30 07:45:52 +08:00
|
|
|
unsigned TargetMinStride = getMinPrefetchStride();
|
2016-03-18 08:27:38 +08:00
|
|
|
// No need to check if any stride goes.
|
|
|
|
|
if (TargetMinStride <= 1)
|
|
|
|
|
return true;
|
|
|
|
|
|
|
|
|
|
const auto *ConstStride = dyn_cast<SCEVConstant>(AR->getStepRecurrence(*SE));
|
|
|
|
|
// If MinStride is set, don't prefetch unless we can ensure that stride is
|
|
|
|
|
// larger.
|
|
|
|
|
if (!ConstStride)
|
|
|
|
|
return false;
|
|
|
|
|
|
|
|
|
|
unsigned AbsStride = std::abs(ConstStride->getAPInt().getSExtValue());
|
|
|
|
|
return TargetMinStride <= AbsStride;
|
|
|
|
|
}
|
|
|
|
|
|
2016-08-13 12:11:27 +08:00
|
|
|
PreservedAnalyses LoopDataPrefetchPass::run(Function &F,
|
|
|
|
|
FunctionAnalysisManager &AM) {
|
|
|
|
|
LoopInfo *LI = &AM.getResult<LoopAnalysis>(F);
|
|
|
|
|
ScalarEvolution *SE = &AM.getResult<ScalarEvolutionAnalysis>(F);
|
|
|
|
|
AssumptionCache *AC = &AM.getResult<AssumptionAnalysis>(F);
|
|
|
|
|
OptimizationRemarkEmitter *ORE =
|
|
|
|
|
&AM.getResult<OptimizationRemarkEmitterAnalysis>(F);
|
|
|
|
|
const TargetTransformInfo *TTI = &AM.getResult<TargetIRAnalysis>(F);
|
|
|
|
|
|
|
|
|
|
LoopDataPrefetch LDP(AC, LI, SE, TTI, ORE);
|
|
|
|
|
bool Changed = LDP.run();
|
|
|
|
|
|
|
|
|
|
if (Changed) {
|
|
|
|
|
PreservedAnalyses PA;
|
|
|
|
|
PA.preserve<DominatorTreeAnalysis>();
|
|
|
|
|
PA.preserve<LoopAnalysis>();
|
|
|
|
|
return PA;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return PreservedAnalyses::all();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
bool LoopDataPrefetchLegacyPass::runOnFunction(Function &F) {
|
2016-05-04 06:32:30 +08:00
|
|
|
if (skipFunction(F))
|
|
|
|
|
return false;
|
|
|
|
|
|
2016-08-13 12:11:27 +08:00
|
|
|
LoopInfo *LI = &getAnalysis<LoopInfoWrapperPass>().getLoopInfo();
|
|
|
|
|
ScalarEvolution *SE = &getAnalysis<ScalarEvolutionWrapperPass>().getSE();
|
|
|
|
|
AssumptionCache *AC =
|
|
|
|
|
&getAnalysis<AssumptionCacheTracker>().getAssumptionCache(F);
|
|
|
|
|
OptimizationRemarkEmitter *ORE =
|
|
|
|
|
&getAnalysis<OptimizationRemarkEmitterWrapperPass>().getORE();
|
|
|
|
|
const TargetTransformInfo *TTI =
|
|
|
|
|
&getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
|
|
|
|
|
|
|
|
|
|
LoopDataPrefetch LDP(AC, LI, SE, TTI, ORE);
|
|
|
|
|
return LDP.run();
|
|
|
|
|
}
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
|
2016-08-13 12:11:27 +08:00
|
|
|
bool LoopDataPrefetch::run() {
|
2016-03-08 02:35:42 +08:00
|
|
|
// If PrefetchDistance is not set, don't run the pass. This gives an
|
|
|
|
|
// opportunity for targets to run this pass for selected subtargets only
|
|
|
|
|
// (whose TTI sets PrefetchDistance).
|
2016-03-30 07:45:52 +08:00
|
|
|
if (getPrefetchDistance() == 0)
|
2016-03-08 02:35:42 +08:00
|
|
|
return false;
|
2016-01-22 02:28:36 +08:00
|
|
|
assert(TTI->getCacheLineSize() && "Cache line size is not set for target");
|
|
|
|
|
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
bool MadeChange = false;
|
|
|
|
|
|
2016-06-26 20:28:59 +08:00
|
|
|
for (Loop *I : *LI)
|
|
|
|
|
for (auto L = df_begin(I), LE = df_end(I); L != LE; ++L)
|
2015-04-13 01:18:56 +08:00
|
|
|
MadeChange |= runOnLoop(*L);
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
|
|
|
|
|
return MadeChange;
|
|
|
|
|
}
|
|
|
|
|
|
2016-02-19 05:37:12 +08:00
|
|
|
bool LoopDataPrefetch::runOnLoop(Loop *L) {
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
bool MadeChange = false;
|
|
|
|
|
|
|
|
|
|
// Only prefetch in the inner-most loop
|
|
|
|
|
if (!L->empty())
|
|
|
|
|
return MadeChange;
|
|
|
|
|
|
|
|
|
|
SmallPtrSet<const Value *, 32> EphValues;
|
|
|
|
|
CodeMetrics::collectEphemeralValues(L, AC, EphValues);
|
|
|
|
|
|
|
|
|
|
// Calculate the number of iterations ahead to prefetch
|
|
|
|
|
CodeMetrics Metrics;
|
|
|
|
|
for (Loop::block_iterator I = L->block_begin(), IE = L->block_end();
|
|
|
|
|
I != IE; ++I) {
|
|
|
|
|
|
|
|
|
|
// If the loop already has prefetches, then assume that the user knows
|
2016-06-11 04:06:03 +08:00
|
|
|
// what they are doing and don't add any more.
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
for (BasicBlock::iterator J = (*I)->begin(), JE = (*I)->end();
|
|
|
|
|
J != JE; ++J)
|
|
|
|
|
if (CallInst *CI = dyn_cast<CallInst>(J))
|
|
|
|
|
if (Function *F = CI->getCalledFunction())
|
|
|
|
|
if (F->getIntrinsicID() == Intrinsic::prefetch)
|
|
|
|
|
return MadeChange;
|
|
|
|
|
|
|
|
|
|
Metrics.analyzeBasicBlock(*I, *TTI, EphValues);
|
|
|
|
|
}
|
|
|
|
|
unsigned LoopSize = Metrics.NumInsts;
|
|
|
|
|
if (!LoopSize)
|
|
|
|
|
LoopSize = 1;
|
|
|
|
|
|
2016-03-30 07:45:52 +08:00
|
|
|
unsigned ItersAhead = getPrefetchDistance() / LoopSize;
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
if (!ItersAhead)
|
|
|
|
|
ItersAhead = 1;
|
|
|
|
|
|
2016-03-30 07:45:52 +08:00
|
|
|
if (ItersAhead > getMaxPrefetchIterationsAhead())
|
2016-03-18 08:27:43 +08:00
|
|
|
return MadeChange;
|
|
|
|
|
|
2016-03-09 13:33:21 +08:00
|
|
|
DEBUG(dbgs() << "Prefetching " << ItersAhead
|
|
|
|
|
<< " iterations ahead (loop size: " << LoopSize << ") in "
|
2016-07-23 07:08:10 +08:00
|
|
|
<< L->getHeader()->getParent()->getName() << ": " << *L);
|
2016-03-09 13:33:21 +08:00
|
|
|
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
SmallVector<std::pair<Instruction *, const SCEVAddRecExpr *>, 16> PrefLoads;
|
|
|
|
|
for (Loop::block_iterator I = L->block_begin(), IE = L->block_end();
|
|
|
|
|
I != IE; ++I) {
|
|
|
|
|
for (BasicBlock::iterator J = (*I)->begin(), JE = (*I)->end();
|
|
|
|
|
J != JE; ++J) {
|
|
|
|
|
Value *PtrValue;
|
|
|
|
|
Instruction *MemI;
|
|
|
|
|
|
|
|
|
|
if (LoadInst *LMemI = dyn_cast<LoadInst>(J)) {
|
|
|
|
|
MemI = LMemI;
|
|
|
|
|
PtrValue = LMemI->getPointerOperand();
|
|
|
|
|
} else if (StoreInst *SMemI = dyn_cast<StoreInst>(J)) {
|
|
|
|
|
if (!PrefetchWrites) continue;
|
|
|
|
|
MemI = SMemI;
|
|
|
|
|
PtrValue = SMemI->getPointerOperand();
|
|
|
|
|
} else continue;
|
|
|
|
|
|
|
|
|
|
unsigned PtrAddrSpace = PtrValue->getType()->getPointerAddressSpace();
|
|
|
|
|
if (PtrAddrSpace)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
if (L->isLoopInvariant(PtrValue))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
const SCEV *LSCEV = SE->getSCEV(PtrValue);
|
|
|
|
|
const SCEVAddRecExpr *LSCEVAddRec = dyn_cast<SCEVAddRecExpr>(LSCEV);
|
|
|
|
|
if (!LSCEVAddRec)
|
|
|
|
|
continue;
|
|
|
|
|
|
2016-03-18 08:27:38 +08:00
|
|
|
// Check if the the stride of the accesses is large enough to warrant a
|
|
|
|
|
// prefetch.
|
|
|
|
|
if (!isStrideLargeEnough(LSCEVAddRec))
|
|
|
|
|
continue;
|
|
|
|
|
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
// We don't want to double prefetch individual cache lines. If this load
|
|
|
|
|
// is known to be within one cache line of some other load that has
|
|
|
|
|
// already been prefetched, then don't prefetch this one as well.
|
|
|
|
|
bool DupPref = false;
|
2016-06-26 20:28:59 +08:00
|
|
|
for (const auto &PrefLoad : PrefLoads) {
|
|
|
|
|
const SCEV *PtrDiff = SE->getMinusSCEV(LSCEVAddRec, PrefLoad.second);
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
if (const SCEVConstant *ConstPtrDiff =
|
|
|
|
|
dyn_cast<SCEVConstant>(PtrDiff)) {
|
2015-03-10 04:20:16 +08:00
|
|
|
int64_t PD = std::abs(ConstPtrDiff->getValue()->getSExtValue());
|
2016-01-22 02:28:36 +08:00
|
|
|
if (PD < (int64_t) TTI->getCacheLineSize()) {
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
DupPref = true;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
if (DupPref)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
const SCEV *NextLSCEV = SE->getAddExpr(LSCEVAddRec, SE->getMulExpr(
|
|
|
|
|
SE->getConstant(LSCEVAddRec->getType(), ItersAhead),
|
|
|
|
|
LSCEVAddRec->getStepRecurrence(*SE)));
|
|
|
|
|
if (!isSafeToExpand(NextLSCEV, *SE))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
PrefLoads.push_back(std::make_pair(MemI, LSCEVAddRec));
|
|
|
|
|
|
|
|
|
|
Type *I8Ptr = Type::getInt8PtrTy((*I)->getContext(), PtrAddrSpace);
|
2015-03-10 10:37:25 +08:00
|
|
|
SCEVExpander SCEVE(*SE, J->getModule()->getDataLayout(), "prefaddr");
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
Value *PrefPtrValue = SCEVE.expandCodeFor(NextLSCEV, I8Ptr, MemI);
|
|
|
|
|
|
|
|
|
|
IRBuilder<> Builder(MemI);
|
|
|
|
|
Module *M = (*I)->getParent()->getParent();
|
|
|
|
|
Type *I32 = Type::getInt32Ty((*I)->getContext());
|
|
|
|
|
Value *PrefetchFunc = Intrinsic::getDeclaration(M, Intrinsic::prefetch);
|
2015-05-19 06:13:54 +08:00
|
|
|
Builder.CreateCall(
|
|
|
|
|
PrefetchFunc,
|
|
|
|
|
{PrefPtrValue,
|
|
|
|
|
ConstantInt::get(I32, MemI->mayReadFromMemory() ? 0 : 1),
|
|
|
|
|
ConstantInt::get(I32, 3), ConstantInt::get(I32, 1)});
|
2016-03-09 13:33:21 +08:00
|
|
|
++NumPrefetches;
|
|
|
|
|
DEBUG(dbgs() << " Access: " << *PtrValue << ", SCEV: " << *LSCEV
|
|
|
|
|
<< "\n");
|
2016-07-23 06:53:17 +08:00
|
|
|
ORE->emitOptimizationRemark(DEBUG_TYPE, MemI, "prefetched memory access");
|
[PowerPC] Loop Data Prefetching for the BG/Q
The IBM BG/Q supercomputer's A2 cores have a hardware prefetching unit, the
L1P, but it does not prefetch directly into the A2's L1 cache. Instead, it
prefetches into its own L1P buffer, and the latency to access that buffer is
significantly higher than that to the L1 cache (although smaller than the
latency to the L2 cache). As a result, especially when multiple hardware
threads are not actively busy, explicitly prefetching data into the L1 cache is
advantageous.
I've been using this pass out-of-tree for data prefetching on the BG/Q for well
over a year, and it has worked quite well. It is enabled by default only for
the BG/Q, but can be enabled for other cores as well via a command-line option.
Eventually, we might want to add some TTI interfaces and move this into
Transforms/Scalar (there is nothing particularly target dependent about it,
although only machines like the BG/Q will benefit from its simplistic
strategy).
llvm-svn: 229966
2015-02-20 13:08:21 +08:00
|
|
|
|
|
|
|
|
MadeChange = true;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return MadeChange;
|
|
|
|
|
}
|
|
|
|
|
|