2017-09-29 06:27:31 +08:00
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//===- HexagonMachineScheduler.h - Custom Hexagon MI scheduler --*- C++ -*-===//
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2012-09-04 22:49:56 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Custom Hexagon MI scheduler.
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//
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//===----------------------------------------------------------------------===//
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2014-08-14 00:26:38 +08:00
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
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2012-09-04 22:49:56 +08:00
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2017-09-29 06:27:31 +08:00
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/CodeGen/DFAPacketizer.h"
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2012-09-04 22:49:56 +08:00
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#include "llvm/CodeGen/MachineScheduler.h"
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#include "llvm/CodeGen/RegisterPressure.h"
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#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
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2017-11-08 09:01:31 +08:00
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetSchedule.h"
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2017-11-17 09:07:10 +08:00
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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2017-09-29 06:27:31 +08:00
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#include <algorithm>
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#include <cassert>
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#include <limits>
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#include <memory>
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#include <vector>
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2012-09-04 22:49:56 +08:00
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namespace llvm {
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2017-09-29 06:27:31 +08:00
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class SUnit;
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2012-09-04 22:49:56 +08:00
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class VLIWResourceModel {
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/// ResourcesModel - Represents VLIW state.
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2017-04-27 22:38:21 +08:00
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/// Not limited to VLIW targets per se, but assumes
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2012-09-04 22:49:56 +08:00
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/// definition of DFA by a target.
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DFAPacketizer *ResourcesModel;
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2012-10-10 13:43:09 +08:00
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const TargetSchedModel *SchedModel;
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2012-09-04 22:49:56 +08:00
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/// Local packet/bundle model. Purely
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/// internal to the MI schedulre at the time.
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std::vector<SUnit *> Packet;
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2012-09-04 22:49:56 +08:00
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/// Total packets created.
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unsigned TotalPackets = 0;
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2012-09-04 22:49:56 +08:00
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2016-07-16 04:16:03 +08:00
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public:
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2015-02-03 06:11:40 +08:00
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VLIWResourceModel(const TargetSubtargetInfo &STI, const TargetSchedModel *SM)
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: SchedModel(SM) {
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ResourcesModel = STI.getInstrInfo()->CreateTargetScheduleState(STI);
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2012-09-04 22:49:56 +08:00
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2012-09-11 01:31:34 +08:00
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// This hard requirement could be relaxed,
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// but for now do not let it proceed.
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assert(ResourcesModel && "Unimplemented CreateTargetScheduleState.");
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2012-10-10 13:43:09 +08:00
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Packet.resize(SchedModel->getIssueWidth());
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2012-09-04 22:49:56 +08:00
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Packet.clear();
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ResourcesModel->clearResources();
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}
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~VLIWResourceModel() {
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delete ResourcesModel;
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}
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void resetPacketState() {
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Packet.clear();
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}
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void resetDFA() {
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ResourcesModel->clearResources();
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}
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2012-09-11 01:31:34 +08:00
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void reset() {
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Packet.clear();
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ResourcesModel->clearResources();
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}
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2018-03-20 20:28:43 +08:00
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bool isResourceAvailable(SUnit *SU, bool IsTop);
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bool reserveResources(SUnit *SU, bool IsTop);
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2012-09-04 22:49:56 +08:00
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unsigned getTotalPackets() const { return TotalPackets; }
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2016-08-12 06:21:41 +08:00
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bool isInPacket(SUnit *SU) const { return is_contained(Packet, SU); }
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2012-09-04 22:49:56 +08:00
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};
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2012-09-11 08:39:15 +08:00
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/// Extend the standard ScheduleDAGMI to provide more context and override the
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/// top-level schedule() driver.
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2013-12-29 05:56:47 +08:00
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class VLIWMachineScheduler : public ScheduleDAGMILive {
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2012-09-04 22:49:56 +08:00
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public:
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2014-04-22 04:32:32 +08:00
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VLIWMachineScheduler(MachineSchedContext *C,
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std::unique_ptr<MachineSchedStrategy> S)
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: ScheduleDAGMILive(C, std::move(S)) {}
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2012-09-04 22:49:56 +08:00
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/// Schedule - This is called back from ScheduleDAGInstrs::Run() when it's
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/// time to do some work.
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2014-08-31 00:48:34 +08:00
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void schedule() override;
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2018-03-20 20:28:43 +08:00
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RegisterClassInfo *getRegClassInfo() { return RegClassInfo; }
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2018-03-20 22:54:01 +08:00
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int getBBSize() { return BB->size(); }
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2012-09-04 22:49:56 +08:00
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};
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2012-09-11 01:31:34 +08:00
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2017-04-27 22:38:21 +08:00
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//===----------------------------------------------------------------------===//
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// ConvergingVLIWScheduler - Implementation of the standard
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// MachineSchedStrategy.
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//===----------------------------------------------------------------------===//
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2012-09-11 01:31:34 +08:00
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/// ConvergingVLIWScheduler shrinks the unscheduled zone using heuristics
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/// to balance the schedule.
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class ConvergingVLIWScheduler : public MachineSchedStrategy {
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/// Store the state used by ConvergingVLIWScheduler heuristics, required
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/// for the lifetime of one invocation of pickNode().
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struct SchedCandidate {
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// The best SUnit candidate.
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SUnit *SU = nullptr;
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2012-09-11 01:31:34 +08:00
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// Register pressure values for the best candidate.
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RegPressureDelta RPDelta;
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// Best scheduling cost.
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int SCost = 0;
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2012-09-11 01:31:34 +08:00
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2017-09-29 06:27:31 +08:00
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SchedCandidate() = default;
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2012-09-11 01:31:34 +08:00
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};
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/// Represent the type of SchedCandidate found within a single queue.
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enum CandResult {
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NoCand, NodeOrder, SingleExcess, SingleCritical, SingleMax, MultiPressure,
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BestCost, Weak};
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/// Each Scheduling boundary is associated with ready queues. It tracks the
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/// current cycle in whichever direction at has moved, and maintains the state
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/// of "hazards" and other interlocks at the current cycle.
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struct VLIWSchedBoundary {
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VLIWMachineScheduler *DAG = nullptr;
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const TargetSchedModel *SchedModel = nullptr;
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2012-09-11 01:31:34 +08:00
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ReadyQueue Available;
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ReadyQueue Pending;
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bool CheckPending = false;
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2012-09-11 01:31:34 +08:00
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2017-09-29 06:27:31 +08:00
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ScheduleHazardRecognizer *HazardRec = nullptr;
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VLIWResourceModel *ResourceModel = nullptr;
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2012-09-11 01:31:34 +08:00
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2017-09-29 06:27:31 +08:00
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unsigned CurrCycle = 0;
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unsigned IssueCount = 0;
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2018-03-20 22:54:01 +08:00
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unsigned CriticalPathLength = 0;
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2012-09-11 01:31:34 +08:00
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/// MinReadyCycle - Cycle of the soonest available instruction.
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unsigned MinReadyCycle = std::numeric_limits<unsigned>::max();
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2012-09-11 01:31:34 +08:00
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// Remember the greatest min operand latency.
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unsigned MaxMinLatency = 0;
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2012-09-11 01:31:34 +08:00
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/// Pending queues extend the ready queues with the same ID and the
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/// PendingFlag set.
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VLIWSchedBoundary(unsigned ID, const Twine &Name)
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: Available(ID, Name+".A"),
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Pending(ID << ConvergingVLIWScheduler::LogMaxQID, Name+".P") {}
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2013-12-29 05:56:47 +08:00
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~VLIWSchedBoundary() {
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2012-09-11 01:31:34 +08:00
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delete ResourceModel;
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delete HazardRec;
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}
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2012-10-10 13:43:09 +08:00
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void init(VLIWMachineScheduler *dag, const TargetSchedModel *smodel) {
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DAG = dag;
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SchedModel = smodel;
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2018-03-20 20:28:43 +08:00
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CurrCycle = 0;
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2016-07-16 04:16:03 +08:00
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IssueCount = 0;
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2018-03-20 22:54:01 +08:00
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// Initialize the critical path length limit, which used by the scheduling
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// cost model to determine the value for scheduling an instruction. We use
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// a slightly different heuristic for small and large functions. For small
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// functions, it's important to use the height/depth of the instruction.
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// For large functions, prioritizing by height or depth increases spills.
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CriticalPathLength = DAG->getBBSize() / SchedModel->getIssueWidth();
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if (DAG->getBBSize() < 50)
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// We divide by two as a cheap and simple heuristic to reduce the
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// critcal path length, which increases the priority of using the graph
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// height/depth in the scheduler's cost computation.
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CriticalPathLength >>= 1;
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else {
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// For large basic blocks, we prefer a larger critical path length to
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// decrease the priority of using the graph height/depth.
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unsigned MaxPath = 0;
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for (auto &SU : DAG->SUnits)
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MaxPath = std::max(MaxPath, isTop() ? SU.getHeight() : SU.getDepth());
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CriticalPathLength = std::max(CriticalPathLength, MaxPath) + 1;
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}
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2012-10-10 13:43:09 +08:00
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}
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2012-09-11 01:31:34 +08:00
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bool isTop() const {
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return Available.getID() == ConvergingVLIWScheduler::TopQID;
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}
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bool checkHazard(SUnit *SU);
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void releaseNode(SUnit *SU, unsigned ReadyCycle);
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void bumpCycle();
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void bumpNode(SUnit *SU);
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void releasePending();
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void removeReady(SUnit *SU);
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SUnit *pickOnlyChoice();
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2018-03-21 03:26:27 +08:00
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2018-03-20 22:54:01 +08:00
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bool isLatencyBound(SUnit *SU) {
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if (CurrCycle >= CriticalPathLength)
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return true;
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unsigned PathLength = isTop() ? SU->getHeight() : SU->getDepth();
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return CriticalPathLength - CurrCycle <= PathLength;
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}
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2012-09-11 01:31:34 +08:00
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};
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2017-09-29 06:27:31 +08:00
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VLIWMachineScheduler *DAG = nullptr;
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const TargetSchedModel *SchedModel = nullptr;
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2012-09-11 01:31:34 +08:00
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// State of the top and bottom scheduled instruction boundaries.
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2013-12-29 05:56:47 +08:00
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VLIWSchedBoundary Top;
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VLIWSchedBoundary Bot;
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2012-09-11 01:31:34 +08:00
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2018-03-20 20:28:43 +08:00
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/// List of pressure sets that have a high pressure level in the region.
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std::vector<bool> HighPressureSets;
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2012-09-11 01:31:34 +08:00
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public:
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/// SUnit::NodeQueueId: 0 (none), 1 (top), 2 (bot), 3 (both)
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enum {
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TopQID = 1,
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BotQID = 2,
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LogMaxQID = 2
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};
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2017-09-29 06:27:31 +08:00
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ConvergingVLIWScheduler() : Top(TopQID, "TopQ"), Bot(BotQID, "BotQ") {}
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2012-09-11 01:31:34 +08:00
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2014-08-31 00:48:34 +08:00
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void initialize(ScheduleDAGMI *dag) override;
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2012-09-11 01:31:34 +08:00
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2014-08-31 00:48:34 +08:00
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SUnit *pickNode(bool &IsTopNode) override;
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2012-09-11 01:31:34 +08:00
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2014-08-31 00:48:34 +08:00
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void schedNode(SUnit *SU, bool IsTopNode) override;
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2012-09-11 01:31:34 +08:00
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2014-08-31 00:48:34 +08:00
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void releaseTopNode(SUnit *SU) override;
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2012-09-11 01:31:34 +08:00
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2014-08-31 00:48:34 +08:00
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void releaseBottomNode(SUnit *SU) override;
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2012-09-11 01:31:34 +08:00
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2018-03-21 03:26:27 +08:00
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unsigned reportPackets() {
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2012-09-14 23:07:59 +08:00
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return Top.ResourceModel->getTotalPackets() +
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Bot.ResourceModel->getTotalPackets();
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}
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2012-09-11 01:31:34 +08:00
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protected:
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SUnit *pickNodeBidrectional(bool &IsTopNode);
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2018-03-20 20:28:43 +08:00
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int pressureChange(const SUnit *SU, bool isBotUp);
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2012-09-11 01:31:34 +08:00
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int SchedulingCost(ReadyQueue &Q,
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SUnit *SU, SchedCandidate &Candidate,
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RegPressureDelta &Delta, bool verbose);
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2018-03-21 03:26:27 +08:00
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CandResult pickNodeFromQueue(VLIWSchedBoundary &Zone,
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2012-09-11 01:31:34 +08:00
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const RegPressureTracker &RPTracker,
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SchedCandidate &Candidate);
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#ifndef NDEBUG
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void traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU,
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2016-07-18 23:47:25 +08:00
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int Cost, PressureChange P = PressureChange());
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void readyQueueVerboseDump(const RegPressureTracker &RPTracker,
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SchedCandidate &Candidate, ReadyQueue &Q);
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2012-09-11 01:31:34 +08:00
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#endif
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};
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2017-09-29 06:27:31 +08:00
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} // end namespace llvm
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2012-09-04 22:49:56 +08:00
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2017-09-29 06:27:31 +08:00
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#endif // LLVM_LIB_TARGET_HEXAGON_HEXAGONMACHINESCHEDULER_H
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