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llvm-project/llvm/test/CodeGen/PowerPC/i64_fp_round.ll

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Adding -verify-machineinstrs option to PowerPC tests Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624
2016-08-04 02:17:35 +08:00
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt < %s | FileCheck %s
[PowerPC] Expand ISEL instruction into if-then-else sequence. Generally, the ISEL is expanded into if-then-else sequence, in some cases (like when the destination register is the same with the true or false value register), it may just be expanded into just the if or else sequence. llvm-svn: 292154
2017-01-17 04:12:26 +08:00
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -ppc-gen-isel=false < %s | FileCheck %s --check-prefix=CHECK-NO-ISEL
This patch fixes failures in the SingleSource/Regression/C/uint64_to_float test case on PowerPC caused by rounding errors when converting from a 64-bit integer to a single-precision floating point. The reason for this are double-rounding effects, since on PowerPC we have to convert to an intermediate double-precision value first, which gets rounded to the final single-precision result. The patch fixes the problem by preparing the 64-bit integer so that the first conversion step to double-precision will always be exact, and the final rounding step will result in the correctly-rounded single-precision result. The generated code sequence is equivalent to what GCC would generate. When -enable-unsafe-fp-math is in effect, that extra effort is omitted and we accept possible rounding errors (just like GCC does as well). llvm-svn: 166178
2012-10-18 21:16:11 +08:00
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
define float @test(i64 %x) nounwind readnone {
entry:
%conv = sitofp i64 %x to float
ret float %conv
}
; Verify that we get the code sequence needed to avoid double-rounding.
; Note that only parts of the sequence are checked for here, to allow
; for minor code generation differences.
[PowerPC] Expand ISEL instruction into if-then-else sequence. Generally, the ISEL is expanded into if-then-else sequence, in some cases (like when the destination register is the same with the true or false value register), it may just be expanded into just the if or else sequence. llvm-svn: 292154
2017-01-17 04:12:26 +08:00
;CHECK-LABEL: test
;CHECK-NO-ISEL-LABEL: test
Rewrite test to not use a FileCheck variable and redefine it on the same line. In preparation for the FileCheck functionality change which will allow using a variable later on the same line. No functionality change. llvm-svn: 168588
2012-11-26 22:09:46 +08:00
; CHECK: sradi [[REG1:[0-9]+]], 3, 53
; CHECK: addi [[REG2:[0-9]+]], [[REG1]], 1
[PowerPC] Enable printing instructions using aliases TableGen had been nicely generating code to print a number of instructions using shorter aliases (and PowerPC has plenty of short mnemonics), but we were not calling it. For some of the aliases we support in the parser, TableGen can't infer the "inverse" alias relationship, so there is still more to do. Thus, after some hours of updating test cases... llvm-svn: 235616
2015-04-24 02:30:38 +08:00
; CHECK: cmpldi [[REG2]], 1
Rewrite test to not use a FileCheck variable and redefine it on the same line. In preparation for the FileCheck functionality change which will allow using a variable later on the same line. No functionality change. llvm-svn: 168588
2012-11-26 22:09:46 +08:00
; CHECK: isel [[REG3:[0-9]+]], {{[0-9]+}}, 3, 1
[PowerPC] Use rldicr instruction for AND with an immediate if possible Emit clrrdi (extended mnemonic for rldicr) for AND-ing with masks that clear bits from the right hand size. Committing on behalf of Hiroshi Inoue. Differential Revision: https://reviews.llvm.org/D29388 llvm-svn: 296143
2017-02-25 02:03:16 +08:00
; CHECK-NO-ISEL: rldicr [[REG2:[0-9]+]], {{[0-9]+}}, 0, 52
[PowerPC] Expand ISEL instruction into if-then-else sequence. Generally, the ISEL is expanded into if-then-else sequence, in some cases (like when the destination register is the same with the true or false value register), it may just be expanded into just the if or else sequence. llvm-svn: 292154
2017-01-17 04:12:26 +08:00
; CHECK-NO-ISEL: bc 12, 1, [[TRUE:.LBB[0-9]+]]
[PowerPC] Use rldicr instruction for AND with an immediate if possible Emit clrrdi (extended mnemonic for rldicr) for AND-ing with masks that clear bits from the right hand size. Committing on behalf of Hiroshi Inoue. Differential Revision: https://reviews.llvm.org/D29388 llvm-svn: 296143
2017-02-25 02:03:16 +08:00
; CHECK-NO-ISEL: ori [[REG3:[0-9]+]], 3, 0
[PowerPC] Expand ISEL instruction into if-then-else sequence. Generally, the ISEL is expanded into if-then-else sequence, in some cases (like when the destination register is the same with the true or false value register), it may just be expanded into just the if or else sequence. llvm-svn: 292154
2017-01-17 04:12:26 +08:00
; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
; CHECK-NO-ISEL-NEXT: [[TRUE]]
[PowerPC] Use rldicr instruction for AND with an immediate if possible Emit clrrdi (extended mnemonic for rldicr) for AND-ing with masks that clear bits from the right hand size. Committing on behalf of Hiroshi Inoue. Differential Revision: https://reviews.llvm.org/D29388 llvm-svn: 296143
2017-02-25 02:03:16 +08:00
; CHECK-NO-ISEL-NEXT: addi [[REG3]], [[REG2]], 0
; CHECK-NO-ISEL-NEXT: [[SUCCESSOR]]
; CHECK-NO-ISEL: std [[REG3]], -{{[0-9]+}}(1)
Rewrite test to not use a FileCheck variable and redefine it on the same line. In preparation for the FileCheck functionality change which will allow using a variable later on the same line. No functionality change. llvm-svn: 168588
2012-11-26 22:09:46 +08:00
; CHECK: std [[REG3]], -{{[0-9]+}}(1)
This patch fixes failures in the SingleSource/Regression/C/uint64_to_float test case on PowerPC caused by rounding errors when converting from a 64-bit integer to a single-precision floating point. The reason for this are double-rounding effects, since on PowerPC we have to convert to an intermediate double-precision value first, which gets rounded to the final single-precision result. The patch fixes the problem by preparing the 64-bit integer so that the first conversion step to double-precision will always be exact, and the final rounding step will result in the correctly-rounded single-precision result. The generated code sequence is equivalent to what GCC would generate. When -enable-unsafe-fp-math is in effect, that extra effort is omitted and we accept possible rounding errors (just like GCC does as well). llvm-svn: 166178
2012-10-18 21:16:11 +08:00
; Also check that with -enable-unsafe-fp-math we do not get that extra
; code sequence. Simply verify that there is no "isel" present.
Adding -verify-machineinstrs option to PowerPC tests Currently we have a number of tests that fail with -verify-machineinstrs. To detect this cases earlier we add the option to the testcases with the exception of tests that will currently fail with this option. PR 27456 keeps track of this failures. No code review, as discussed with Hal Finkel. llvm-svn: 277624
2016-08-04 02:17:35 +08:00
; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-fpcvt -enable-unsafe-fp-math < %s | FileCheck %s -check-prefix=CHECK-UNSAFE
This patch fixes failures in the SingleSource/Regression/C/uint64_to_float test case on PowerPC caused by rounding errors when converting from a 64-bit integer to a single-precision floating point. The reason for this are double-rounding effects, since on PowerPC we have to convert to an intermediate double-precision value first, which gets rounded to the final single-precision result. The patch fixes the problem by preparing the 64-bit integer so that the first conversion step to double-precision will always be exact, and the final rounding step will result in the correctly-rounded single-precision result. The generated code sequence is equivalent to what GCC would generate. When -enable-unsafe-fp-math is in effect, that extra effort is omitted and we accept possible rounding errors (just like GCC does as well). llvm-svn: 166178
2012-10-18 21:16:11 +08:00
; CHECK-UNSAFE-NOT: isel