2011-09-24 09:40:18 +08:00
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//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes Mips64 instructions.
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//
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//===----------------------------------------------------------------------===//
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2011-09-29 01:50:27 +08:00
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2011-09-30 10:08:54 +08:00
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//===----------------------------------------------------------------------===//
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// Mips Operand, Complex Patterns and Transformations Definitions.
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//===----------------------------------------------------------------------===//
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// Unsigned Operand
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def uimm16_64 : Operand<i64> {
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let PrintMethod = "printUnsignedImm";
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}
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2011-09-30 11:18:46 +08:00
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// Transformation Function - get Imm - 32.
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def Subtract32 : SDNodeXForm<imm, [{
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2011-12-08 04:10:24 +08:00
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return getImm(N, (unsigned)N->getZExtValue() - 32);
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2011-09-30 11:18:46 +08:00
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}]>;
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2011-12-20 03:44:09 +08:00
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// shamt must fit in 6 bits.
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def immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>;
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2011-09-30 11:18:46 +08:00
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2011-09-30 04:37:56 +08:00
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//===----------------------------------------------------------------------===//
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// Instructions specific format
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//===----------------------------------------------------------------------===//
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2013-08-21 05:08:22 +08:00
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let usesCustomInserter = 1 in {
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def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>;
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def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>;
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def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>;
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def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>;
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def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>;
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def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>;
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def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>;
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def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>;
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2011-11-11 12:14:30 +08:00
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}
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2013-05-01 07:22:09 +08:00
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/// Pseudo instructions for loading and storing accumulator registers.
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2013-08-02 07:14:16 +08:00
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let isPseudo = 1, isCodeGenOnly = 1 in {
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2013-08-21 05:08:22 +08:00
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def LOAD_ACC128 : Load<"", ACC128>;
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def STORE_ACC128 : Store<"", ACC128>;
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2013-03-30 08:54:52 +08:00
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}
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2011-09-30 04:37:56 +08:00
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//===----------------------------------------------------------------------===//
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// Instruction definition
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//===----------------------------------------------------------------------===//
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2012-04-18 02:03:21 +08:00
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let DecoderNamespace = "Mips64" in {
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2011-09-30 10:08:54 +08:00
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/// Arithmetic Instructions (ALU Immediate)
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2013-08-07 07:08:38 +08:00
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def DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
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def DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, II_DADDIU,
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2013-07-31 08:55:34 +08:00
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immSExt16, add>,
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2012-12-20 11:40:03 +08:00
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ADDI_FM<0x19>, IsAsCheapAsAMove;
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2013-08-07 07:01:10 +08:00
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let isCodeGenOnly = 1 in {
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2013-08-07 07:08:38 +08:00
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def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>,
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2012-12-20 12:27:52 +08:00
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SLTI_FM<0xa>;
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2013-08-07 07:08:38 +08:00
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def SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>,
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2012-12-20 12:27:52 +08:00
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SLTI_FM<0xb>;
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2014-01-16 23:57:05 +08:00
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def ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, II_AND, immZExt16, and>,
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2013-07-31 08:57:41 +08:00
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ADDI_FM<0xc>;
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2014-01-16 23:57:05 +08:00
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def ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, II_OR, immZExt16, or>,
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2012-12-20 11:40:03 +08:00
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ADDI_FM<0xd>;
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2014-01-16 23:57:05 +08:00
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def XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, II_XOR, immZExt16, xor>,
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2012-12-20 11:40:03 +08:00
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ADDI_FM<0xe>;
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2013-08-07 07:08:38 +08:00
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def LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM;
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2013-08-07 07:01:10 +08:00
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}
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2011-09-30 10:08:54 +08:00
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2011-09-30 04:37:56 +08:00
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/// Arithmetic Instructions (3-Operand, R-Type)
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2013-08-07 07:08:38 +08:00
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def DADD : ArithLogicR<"dadd", GPR64Opnd>, ADD_FM<0, 0x2c>;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
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def DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, II_DADDU, add>,
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2013-01-12 09:03:14 +08:00
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ADD_FM<0, 0x2d>;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
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def DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, II_DSUBU, sub>,
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2013-01-12 09:03:14 +08:00
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ADD_FM<0, 0x2f>;
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2013-08-07 06:35:29 +08:00
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let isCodeGenOnly = 1 in {
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2013-08-07 07:08:38 +08:00
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def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>;
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def SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
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def AND64 : ArithLogicR<"and", GPR64Opnd, 1, II_AND, and>, ADD_FM<0, 0x24>;
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def OR64 : ArithLogicR<"or", GPR64Opnd, 1, II_OR, or>, ADD_FM<0, 0x25>;
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def XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, II_XOR, xor>, ADD_FM<0, 0x26>;
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2013-08-07 07:08:38 +08:00
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def NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>;
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2013-08-07 06:35:29 +08:00
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}
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2011-09-30 11:18:46 +08:00
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/// Shift Instructions
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
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def DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, II_DSLL, shl, immZExt6>,
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2013-01-05 03:25:46 +08:00
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SRA_FM<0x38, 0>;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
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def DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, II_DSRL, srl, immZExt6>,
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2013-01-05 03:25:46 +08:00
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SRA_FM<0x3a, 0>;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
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def DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, II_DSRA, sra, immZExt6>,
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2013-01-05 03:25:46 +08:00
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SRA_FM<0x3b, 0>;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
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def DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, II_DSLLV, shl>,
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SRLV_FM<0x14, 0>;
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def DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, II_DSRLV, srl>,
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SRLV_FM<0x16, 0>;
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def DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, II_DSRAV, sra>,
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SRLV_FM<0x17, 0>;
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def DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd, II_DSLL32>,
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SRA_FM<0x3c, 0>;
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def DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd, II_DSRL32>,
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SRA_FM<0x3e, 0>;
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def DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd, II_DSRA32>,
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SRA_FM<0x3f, 0>;
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2013-08-07 07:01:10 +08:00
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2011-10-01 02:51:46 +08:00
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// Rotate Instructions
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2013-08-07 07:01:10 +08:00
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let Predicates = [HasMips64r2, HasStdEnc] in {
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
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def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, II_DROTR, rotr,
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immZExt6>, SRA_FM<0x3a, 1>;
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def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, II_DROTRV, rotr>,
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2013-01-19 04:15:06 +08:00
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SRLV_FM<0x16, 1>;
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[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
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def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd, II_DROTR32>,
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SRA_FM<0x3e, 1>;
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2011-10-01 02:51:46 +08:00
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}
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2011-10-11 08:27:28 +08:00
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/// Load and Store Instructions
|
2012-02-28 15:46:26 +08:00
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|
/// aligned
|
2013-08-07 07:01:10 +08:00
|
|
|
let isCodeGenOnly = 1 in {
|
2014-01-21 23:21:14 +08:00
|
|
|
def LB64 : Load<"lb", GPR64Opnd, sextloadi8, II_LB>, LW_FM<0x20>;
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def LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, II_LBU>, LW_FM<0x24>;
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def LH64 : Load<"lh", GPR64Opnd, sextloadi16, II_LH>, LW_FM<0x21>;
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def LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, II_LHU>, LW_FM<0x25>;
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def LW64 : Load<"lw", GPR64Opnd, sextloadi32, II_LW>, LW_FM<0x23>;
|
2013-08-21 05:08:22 +08:00
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|
def SB64 : Store<"sb", GPR64Opnd, truncstorei8, IIStore>, LW_FM<0x28>;
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def SH64 : Store<"sh", GPR64Opnd, truncstorei16, IIStore>, LW_FM<0x29>;
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def SW64 : Store<"sw", GPR64Opnd, truncstorei32, IIStore>, LW_FM<0x2b>;
|
2013-08-07 07:01:10 +08:00
|
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|
}
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|
2014-01-21 23:21:14 +08:00
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|
def LWu : Load<"lwu", GPR64Opnd, zextloadi32, II_LWU>, LW_FM<0x27>;
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def LD : Load<"ld", GPR64Opnd, load, II_LD>, LW_FM<0x37>;
|
2013-08-21 05:08:22 +08:00
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|
def SD : Store<"sd", GPR64Opnd, store, IIStore>, LW_FM<0x3f>;
|
2011-10-11 08:27:28 +08:00
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|
2012-06-02 08:04:19 +08:00
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|
/// load/store left/right
|
2013-08-07 07:01:10 +08:00
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|
let isCodeGenOnly = 1 in {
|
2014-01-21 23:21:14 +08:00
|
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|
def LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, II_LWL>, LW_FM<0x22>;
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def LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, II_LWR>, LW_FM<0x26>;
|
2013-09-07 07:28:24 +08:00
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|
def SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, IIStore>, LW_FM<0x2a>;
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def SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, IIStore>, LW_FM<0x2e>;
|
2013-08-07 07:01:10 +08:00
|
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|
}
|
2013-01-12 09:03:14 +08:00
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|
2014-01-21 23:21:14 +08:00
|
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|
def LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, II_LDL>, LW_FM<0x1a>;
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def LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, II_LDR>, LW_FM<0x1b>;
|
2013-09-07 07:28:24 +08:00
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|
def SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, IIStore>, LW_FM<0x2c>;
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def SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, IIStore>, LW_FM<0x2d>;
|
2012-06-02 08:04:19 +08:00
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|
2011-11-11 12:14:30 +08:00
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/// Load-linked, Store-conditional
|
2013-08-21 05:08:22 +08:00
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|
def LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>;
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def SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>;
|
2011-11-11 12:14:30 +08:00
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|
2011-10-12 02:49:17 +08:00
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|
/// Jump and Branch Instructions
|
2013-08-07 07:01:10 +08:00
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|
let isCodeGenOnly = 1 in {
|
2013-10-30 00:38:59 +08:00
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|
def JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>;
|
2013-11-04 22:53:22 +08:00
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|
def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
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def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
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def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
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def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
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def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
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|
def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
|
2013-08-07 07:08:38 +08:00
|
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|
def JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM;
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|
def JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>;
|
2013-11-28 07:58:32 +08:00
|
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|
def TAILCALL64_R : TailCallReg<GPR64Opnd, JR, GPR32Opnd>;
|
2013-08-07 07:01:10 +08:00
|
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|
}
|
2012-01-04 11:02:47 +08:00
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|
2011-10-04 04:01:11 +08:00
|
|
|
/// Multiply and Divide Instructions.
|
2014-01-17 22:32:41 +08:00
|
|
|
def DMULT : Mult<"dmult", II_DMULT, GPR64Opnd, [HI0_64, LO0_64]>,
|
2013-01-19 04:15:06 +08:00
|
|
|
MULT_FM<0, 0x1c>;
|
2014-01-17 22:32:41 +08:00
|
|
|
def DMULTu : Mult<"dmultu", II_DMULTU, GPR64Opnd, [HI0_64, LO0_64]>,
|
2013-01-19 04:15:06 +08:00
|
|
|
MULT_FM<0, 0x1d>;
|
2013-08-09 05:54:26 +08:00
|
|
|
def PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult,
|
2014-01-17 22:32:41 +08:00
|
|
|
II_DMULT>;
|
2013-08-09 05:54:26 +08:00
|
|
|
def PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu,
|
2014-01-17 22:32:41 +08:00
|
|
|
II_DMULTU>;
|
2014-01-17 22:48:06 +08:00
|
|
|
def DSDIV : Div<"ddiv", II_DDIV, GPR64Opnd, [HI0_64, LO0_64]>,
|
|
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|
|
MULT_FM<0, 0x1e>;
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|
def DUDIV : Div<"ddivu", II_DDIVU, GPR64Opnd, [HI0_64, LO0_64]>,
|
|
|
|
|
MULT_FM<0, 0x1f>;
|
2013-08-09 05:54:26 +08:00
|
|
|
def PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem,
|
2014-01-17 22:48:06 +08:00
|
|
|
II_DDIV, 0, 1, 1>;
|
2013-08-09 05:54:26 +08:00
|
|
|
def PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU,
|
2014-01-17 22:48:06 +08:00
|
|
|
II_DDIVU, 0, 1, 1>;
|
2011-10-04 04:01:11 +08:00
|
|
|
|
2013-08-07 07:01:10 +08:00
|
|
|
let isCodeGenOnly = 1 in {
|
2013-08-14 08:47:08 +08:00
|
|
|
def MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>;
|
|
|
|
|
def MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>;
|
2013-10-08 02:49:46 +08:00
|
|
|
def MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>;
|
|
|
|
|
def MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>;
|
2013-10-15 09:12:50 +08:00
|
|
|
def PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>;
|
|
|
|
|
def PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>;
|
2013-10-15 09:48:30 +08:00
|
|
|
def PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>;
|
2011-10-04 03:28:44 +08:00
|
|
|
|
2012-01-25 05:41:09 +08:00
|
|
|
/// Sign Ext In Register Instructions.
|
2014-01-17 00:19:38 +08:00
|
|
|
def SEB64 : SignExtInReg<"seb", i8, GPR64Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
|
|
|
|
|
def SEH64 : SignExtInReg<"seh", i16, GPR64Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
|
2013-08-07 07:01:10 +08:00
|
|
|
}
|
2012-01-25 05:41:09 +08:00
|
|
|
|
2011-10-04 05:16:50 +08:00
|
|
|
/// Count Leading
|
2013-08-07 07:08:38 +08:00
|
|
|
def DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>;
|
|
|
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|
def DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>;
|
2011-10-04 05:16:50 +08:00
|
|
|
|
2011-12-21 07:56:43 +08:00
|
|
|
/// Double Word Swap Bytes/HalfWords
|
2013-08-07 07:08:38 +08:00
|
|
|
def DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>;
|
|
|
|
|
def DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>;
|
2012-12-22 07:21:32 +08:00
|
|
|
|
2013-08-21 05:08:22 +08:00
|
|
|
def LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>;
|
2011-12-21 07:56:43 +08:00
|
|
|
|
2013-08-07 07:01:10 +08:00
|
|
|
let isCodeGenOnly = 1 in
|
2013-08-09 05:37:32 +08:00
|
|
|
def RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM;
|
2011-12-08 07:31:26 +08:00
|
|
|
|
2013-09-07 08:02:02 +08:00
|
|
|
def DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>;
|
|
|
|
|
def DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>;
|
|
|
|
|
def DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>;
|
|
|
|
|
|
|
|
|
|
def DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>;
|
|
|
|
|
def DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>;
|
|
|
|
|
def DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>;
|
2011-12-06 05:26:34 +08:00
|
|
|
|
2012-08-07 08:35:22 +08:00
|
|
|
let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
|
2013-08-07 07:08:38 +08:00
|
|
|
def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt),
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
"dsll\t$rd, $rt, 32", [], II_DSLL>;
|
2013-08-07 07:08:38 +08:00
|
|
|
def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt),
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
"sll\t$rd, $rt, 0", [], II_SLL>;
|
2013-08-07 07:08:38 +08:00
|
|
|
def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt),
|
[mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU.
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
II_SR[AL]V, II_SUBU, II_XOR
No functional change since the InstrItinData's have been duplicated.
This is necessary because the classes are shared between all schedulers.
Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.
llvm-svn: 199391
2014-01-16 22:27:20 +08:00
|
|
|
"sll\t$rd, $rt, 0", [], II_SLL>;
|
2012-08-07 08:35:22 +08:00
|
|
|
}
|
2012-04-18 02:03:21 +08:00
|
|
|
}
|
2011-10-01 02:51:46 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
// Arbitrary patterns that map to one or more instructions
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
2011-11-15 03:06:14 +08:00
|
|
|
// extended loads
|
2013-08-21 05:08:22 +08:00
|
|
|
let Predicates = [HasStdEnc] in {
|
2012-06-15 05:03:23 +08:00
|
|
|
def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>;
|
|
|
|
|
def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>;
|
2012-09-15 09:52:08 +08:00
|
|
|
def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>;
|
|
|
|
|
def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>;
|
2011-11-15 03:06:14 +08:00
|
|
|
}
|
2011-10-11 08:55:05 +08:00
|
|
|
|
|
|
|
|
// hi/lo relocs
|
2012-06-15 05:03:23 +08:00
|
|
|
def : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>;
|
|
|
|
|
def : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>;
|
|
|
|
|
def : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>;
|
|
|
|
|
def : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>;
|
|
|
|
|
def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>;
|
2012-11-22 04:40:38 +08:00
|
|
|
def : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>;
|
2012-06-15 05:03:23 +08:00
|
|
|
|
|
|
|
|
def : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>;
|
|
|
|
|
def : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>;
|
|
|
|
|
def : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>;
|
|
|
|
|
def : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>;
|
|
|
|
|
def : MipsPat<(MipsLo tglobaltlsaddr:$in),
|
|
|
|
|
(DADDiu ZERO_64, tglobaltlsaddr:$in)>;
|
2012-11-22 04:40:38 +08:00
|
|
|
def : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>;
|
2012-06-15 05:03:23 +08:00
|
|
|
|
2013-08-07 07:08:38 +08:00
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)),
|
|
|
|
|
(DADDiu GPR64:$hi, tglobaladdr:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)),
|
|
|
|
|
(DADDiu GPR64:$hi, tblockaddress:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)),
|
|
|
|
|
(DADDiu GPR64:$hi, tjumptable:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)),
|
|
|
|
|
(DADDiu GPR64:$hi, tconstpool:$lo)>;
|
|
|
|
|
def : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)),
|
|
|
|
|
(DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>;
|
|
|
|
|
|
|
|
|
|
def : WrapperPat<tglobaladdr, DADDiu, GPR64>;
|
|
|
|
|
def : WrapperPat<tconstpool, DADDiu, GPR64>;
|
|
|
|
|
def : WrapperPat<texternalsym, DADDiu, GPR64>;
|
|
|
|
|
def : WrapperPat<tblockaddress, DADDiu, GPR64>;
|
|
|
|
|
def : WrapperPat<tjumptable, DADDiu, GPR64>;
|
|
|
|
|
def : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>;
|
|
|
|
|
|
|
|
|
|
defm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
|
2011-10-12 03:09:09 +08:00
|
|
|
ZERO_64>;
|
|
|
|
|
|
2013-05-22 01:13:47 +08:00
|
|
|
def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
|
|
|
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(BLEZ64 i64:$lhs, bb:$dst)>;
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def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
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(BGEZ64 i64:$lhs, bb:$dst)>;
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2011-10-12 02:53:46 +08:00
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// setcc patterns
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2013-08-07 07:08:38 +08:00
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defm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>;
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defm : SetlePats<GPR64, SLT64, SLTu64>;
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defm : SetgtPats<GPR64, SLT64, SLTu64>;
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defm : SetgePats<GPR64, SLT64, SLTu64>;
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defm : SetgeImmPats<GPR64, SLTi64, SLTiu64>;
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2011-11-08 02:57:41 +08:00
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// truncate
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2013-08-07 07:08:38 +08:00
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def : MipsPat<(i32 (trunc GPR64:$src)),
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(SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>,
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2013-08-21 07:21:55 +08:00
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Requires<[HasStdEnc]>;
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2012-02-28 15:46:26 +08:00
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2011-12-08 07:14:41 +08:00
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// 32-to-64-bit extension
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2013-08-07 07:08:38 +08:00
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def : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>;
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def : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>;
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def : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>;
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2011-12-21 06:06:20 +08:00
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2011-12-21 06:40:40 +08:00
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// Sign extend in register
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2013-08-07 07:08:38 +08:00
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def : MipsPat<(i64 (sext_inreg GPR64:$src, i32)),
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(SLL64_64 GPR64:$src)>;
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2011-12-21 06:40:40 +08:00
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2012-06-15 05:03:23 +08:00
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// bswap MipsPattern
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2013-08-07 07:08:38 +08:00
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def : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>;
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2012-10-10 00:27:43 +08:00
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//===----------------------------------------------------------------------===//
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// Instruction aliases
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//===----------------------------------------------------------------------===//
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2013-02-05 16:32:10 +08:00
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def : InstAlias<"move $dst, $src",
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2013-08-07 07:08:38 +08:00
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(DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>,
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2013-01-19 04:15:06 +08:00
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Requires<[HasMips64]>;
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2013-01-12 09:03:14 +08:00
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def : InstAlias<"daddu $rs, $rt, $imm",
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2013-08-07 07:08:38 +08:00
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(DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
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2013-08-07 06:35:29 +08:00
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0>;
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2013-01-12 09:03:14 +08:00
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def : InstAlias<"dadd $rs, $rt, $imm",
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2013-08-07 07:08:38 +08:00
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(DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm),
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2013-08-07 06:35:29 +08:00
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0>;
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2013-01-19 04:15:06 +08:00
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2013-05-17 03:40:19 +08:00
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/// Move between CPU and coprocessor registers
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2013-08-28 08:42:50 +08:00
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let DecoderNamespace = "Mips64", Predicates = [HasMips64] in {
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def DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>;
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def DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>;
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def DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>;
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def DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>;
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2012-10-11 18:21:34 +08:00
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}
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2013-01-19 04:15:06 +08:00
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2012-10-11 18:21:34 +08:00
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// Two operand (implicit 0 selector) versions:
|
2013-08-28 08:42:50 +08:00
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def : InstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
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def : InstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
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def : InstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
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def : InstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>;
|
2012-10-11 18:21:34 +08:00
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