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llvm-project/llvm/lib/Target/WebAssembly/CMakeLists.txt

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[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
2015-06-30 07:51:55 +08:00
set(LLVM_TARGET_DEFINITIONS WebAssembly.td)
WebAssembly: basic bitcode → assembly CodeGen test Summary: Add a basic CodeGen bitcode test which (for now) only prints out the function name and nothing else. The current code merely implements the basic needed for the test run to not crash / assert. Getting to that point required: - Basic InstPrinter. - Basic AsmPrinter. - DiagnosticInfoUnsupported (not strictly required, but nice to have, duplicated from AMDGPU/BPF's ISelLowering). - Some SP and register setup in WebAssemblyTargetLowering. - Basic LowerFormalArguments. - GenInstrInfo. - Placeholder LowerFormalArguments. - Placeholder CanLowerReturn and LowerReturn. - Basic DAGToDAGISel::Select, which requiresGenDAGISel.inc as well as GET_INSTRINFO_ENUM with GenInstrInfo.inc. - Remove WebAssemblyFrameLowering::determineCalleeSaves and rely on default. - Implement WebAssemblyFrameLowering::hasFP, same as AArch64's implementation. Follow-up patches will implement a real AsmPrinter, which will require adding MI opcodes specific to WebAssembly. Reviewers: sunfish Subscribers: aemerson, jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D11369 llvm-svn: 242939
2015-07-23 05:28:15 +08:00
tablegen(LLVM WebAssemblyGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM WebAssemblyGenDAGISel.inc -gen-dag-isel)
[WebAssembly] Skeleton FastISel support llvm-svn: 245860
2015-08-25 02:44:37 +08:00
tablegen(LLVM WebAssemblyGenFastISel.inc -gen-fast-isel)
WebAssembly: basic bitcode → assembly CodeGen test Summary: Add a basic CodeGen bitcode test which (for now) only prints out the function name and nothing else. The current code merely implements the basic needed for the test run to not crash / assert. Getting to that point required: - Basic InstPrinter. - Basic AsmPrinter. - DiagnosticInfoUnsupported (not strictly required, but nice to have, duplicated from AMDGPU/BPF's ISelLowering). - Some SP and register setup in WebAssemblyTargetLowering. - Basic LowerFormalArguments. - GenInstrInfo. - Placeholder LowerFormalArguments. - Placeholder CanLowerReturn and LowerReturn. - Basic DAGToDAGISel::Select, which requiresGenDAGISel.inc as well as GET_INSTRINFO_ENUM with GenInstrInfo.inc. - Remove WebAssemblyFrameLowering::determineCalleeSaves and rely on default. - Implement WebAssemblyFrameLowering::hasFP, same as AArch64's implementation. Follow-up patches will implement a real AsmPrinter, which will require adding MI opcodes specific to WebAssembly. Reviewers: sunfish Subscribers: aemerson, jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D11369 llvm-svn: 242939
2015-07-23 05:28:15 +08:00
tablegen(LLVM WebAssemblyGenInstrInfo.inc -gen-instr-info)
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
2015-06-30 07:51:55 +08:00
tablegen(LLVM WebAssemblyGenMCCodeEmitter.inc -gen-emitter)
WebAssembly: basic instructions todo, and basic register info. Summary: This code is based on AArch64 for modern backend good practice, and NVPTX for virtual ISA concerns. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11070 llvm-svn: 241923
2015-07-11 02:23:10 +08:00
tablegen(LLVM WebAssemblyGenRegisterInfo.inc -gen-register-info)
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
2015-06-30 07:51:55 +08:00
tablegen(LLVM WebAssemblyGenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(WebAssemblyCommonTableGen)
add_llvm_target(WebAssemblyCodeGen
[WebAssembly] Reintroduce ARGUMENT moving logic Reinteroduce the code for moving ARGUMENTS back to the top of the basic block. While the ARGUMENTS physical register prevents sinking and scheduling from moving them, it does not appear to be sufficient to prevent SelectionDAG from moving them down in the initial schedule. This patch introduces a patch that moves them back to the top immediately after SelectionDAG runs. This is still hopefully a temporary solution. http://reviews.llvm.org/D14750 is one alternative, though the review has not been favorable, and proposed alternatives are longer-term and have other downsides. This fixes the main outstanding -verify-machineinstrs failures, so it adds -verify-machineinstrs to several tests. Differential Revision: http://reviews.llvm.org/D15377 llvm-svn: 255125
2015-12-10 00:23:59 +08:00
WebAssemblyArgumentMove.cpp
WebAssembly: basic bitcode → assembly CodeGen test Summary: Add a basic CodeGen bitcode test which (for now) only prints out the function name and nothing else. The current code merely implements the basic needed for the test run to not crash / assert. Getting to that point required: - Basic InstPrinter. - Basic AsmPrinter. - DiagnosticInfoUnsupported (not strictly required, but nice to have, duplicated from AMDGPU/BPF's ISelLowering). - Some SP and register setup in WebAssemblyTargetLowering. - Basic LowerFormalArguments. - GenInstrInfo. - Placeholder LowerFormalArguments. - Placeholder CanLowerReturn and LowerReturn. - Basic DAGToDAGISel::Select, which requiresGenDAGISel.inc as well as GET_INSTRINFO_ENUM with GenInstrInfo.inc. - Remove WebAssemblyFrameLowering::determineCalleeSaves and rely on default. - Implement WebAssemblyFrameLowering::hasFP, same as AArch64's implementation. Follow-up patches will implement a real AsmPrinter, which will require adding MI opcodes specific to WebAssembly. Reviewers: sunfish Subscribers: aemerson, jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D11369 llvm-svn: 242939
2015-07-23 05:28:15 +08:00
WebAssemblyAsmPrinter.cpp
[WebAssembly] Check in an initial CFG Stackifier pass This pass implements a simple algorithm for conversion from CFG to wasm's structured control flow. It doesn't yet handle multiple-entry loops; that will be added in a future patch. It also adds initial support for switch statements. Differential Revision: http://reviews.llvm.org/D12735 llvm-svn: 247818
2015-09-17 00:51:30 +08:00
WebAssemblyCFGStackify.cpp
[WebAssembly] Skeleton FastISel support llvm-svn: 245860
2015-08-25 02:44:37 +08:00
WebAssemblyFastISel.cpp
[WebAssembly] Implement irreducible control flow. This implements a very simple conservative transformation that doesn't require more than linear code size growth. There's room for much more optimization in this space. llvm-svn: 262982
2016-03-09 10:01:14 +08:00
WebAssemblyFixIrreducibleControlFlow.cpp
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
2015-06-30 07:51:55 +08:00
WebAssemblyFrameLowering.cpp
WebAssemblyISelDAGToDAG.cpp
WebAssemblyISelLowering.cpp
WebAssembly: basic bitcode → assembly CodeGen test Summary: Add a basic CodeGen bitcode test which (for now) only prints out the function name and nothing else. The current code merely implements the basic needed for the test run to not crash / assert. Getting to that point required: - Basic InstPrinter. - Basic AsmPrinter. - DiagnosticInfoUnsupported (not strictly required, but nice to have, duplicated from AMDGPU/BPF's ISelLowering). - Some SP and register setup in WebAssemblyTargetLowering. - Basic LowerFormalArguments. - GenInstrInfo. - Placeholder LowerFormalArguments. - Placeholder CanLowerReturn and LowerReturn. - Basic DAGToDAGISel::Select, which requiresGenDAGISel.inc as well as GET_INSTRINFO_ENUM with GenInstrInfo.inc. - Remove WebAssemblyFrameLowering::determineCalleeSaves and rely on default. - Implement WebAssemblyFrameLowering::hasFP, same as AArch64's implementation. Follow-up patches will implement a real AsmPrinter, which will require adding MI opcodes specific to WebAssembly. Reviewers: sunfish Subscribers: aemerson, jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D11369 llvm-svn: 242939
2015-07-23 05:28:15 +08:00
WebAssemblyInstrInfo.cpp
[WebAssembly] Implement ReverseBranchCondition, and re-enable MachineBlockPlacement This patch introduces a codegen-only instruction currently named br_unless, which makes it convenient to implement ReverseBranchCondition and re-enable the MachineBlockPlacement pass. Then in a late pass, it lowers br_unless back into br_if. Differential Revision: http://reviews.llvm.org/D14995 llvm-svn: 254826
2015-12-05 11:03:35 +08:00
WebAssemblyLowerBrUnless.cpp
[WebAssembly] Refactor WebAssemblyLowerEmscriptenException pass for setjmp/longjmp This patch changes the code structure of WebAssemblyLowerEmscriptenException pass to support both exception handling and setjmp/longjmp. It also changes the name of the pass and the source file. 1. Change the file/pass name to WebAssemblyLowerEmscriptenExceptions -> WebAssemblyLowerEmscriptenEHSjLj to make it clear that it supports both EH and SjLj 2. List function / global variable names at the top so they can be changed easily 3. Some cosmetic changes Patch by Heejin Ahn Differential Revision: https://reviews.llvm.org/D23588 llvm-svn: 279075
2016-08-18 23:27:25 +08:00
WebAssemblyLowerEmscriptenEHSjLj.cpp
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
2015-06-30 07:51:55 +08:00
WebAssemblyMachineFunctionInfo.cpp
[WebAssembly] Add WebAssemblyMCInstLower.cpp. This isn't used yet; it's just a start towards eventually using MC to do instruction printing, and eventually binary encoding. llvm-svn: 252194
2015-11-06 03:28:16 +08:00
WebAssemblyMCInstLower.cpp
[WebAssembly] Move register stackification and coloring to a late phase. Move the register stackification and coloring passes to run very late, after PEI, tail duplication, and most other passes. This means that all code emitted and expanded by those passes is now exposed to these passes. This also eliminates the need for prologue/epilogue code to be manually stackified, which significantly simplifies the code. This does require running LiveIntervals a second time. It's useful to think of these late passes not as late optimization passes, but as a domain-specific compression algorithm based on knowledge of liveness information. It's used to compress the code after all conventional optimizations are complete, which is why it uses LiveIntervals at a phase when actual optimization passes don't typically need it. Differential Revision: http://reviews.llvm.org/D20075 llvm-svn: 269012
2016-05-10 12:24:02 +08:00
WebAssemblyOptimizeLiveIntervals.cpp
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-26 00:55:01 +08:00
WebAssemblyOptimizeReturned.cpp
WebAssemblyPeephole.cpp
[WebAssembly] Move register stackification and coloring to a late phase. Move the register stackification and coloring passes to run very late, after PEI, tail duplication, and most other passes. This means that all code emitted and expanded by those passes is now exposed to these passes. This also eliminates the need for prologue/epilogue code to be manually stackified, which significantly simplifies the code. This does require running LiveIntervals a second time. It's useful to think of these late passes not as late optimization passes, but as a domain-specific compression algorithm based on knowledge of liveness information. It's used to compress the code after all conventional optimizations are complete, which is why it uses LiveIntervals at a phase when actual optimization passes don't typically need it. Differential Revision: http://reviews.llvm.org/D20075 llvm-svn: 269012
2016-05-10 12:24:02 +08:00
WebAssemblyPrepareForLiveIntervals.cpp
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
2015-06-30 07:51:55 +08:00
WebAssemblyRegisterInfo.cpp
[WebAssembly] Prototype passes for register coloring and register stackifying. These passes are not yet enabled by default. llvm-svn: 253217
2015-11-17 00:18:28 +08:00
WebAssemblyRegColoring.cpp
[WebAssembly] Reapply r252858, with svn add for the new file. Switch to MC for instruction printing. This encompasses several changes which are all interconnected: - Use the MC framework for printing almost all instructions. - AsmStrings are now live. - This introduces an indirection between LLVM vregs and WebAssembly registers, and a new pass, WebAssemblyRegNumbering, for computing a basic the mapping. This addresses some basic issues with argument registers and unused registers. - The way ARGUMENT instructions are handled no longer generates redundant get_local+set_local for every argument. This also changes the assembly syntax somewhat; most notably, MC's printing does not use sigils on label names, so those are no longer present, and push/pop now have a sigil to keep them unambiguous. The usage of set_local/get_local/$push/$pop will continue to evolve significantly. This patch is just one step of a larger change. llvm-svn: 252910
2015-11-13 01:04:33 +08:00
WebAssemblyRegNumbering.cpp
[WebAssembly] Prototype passes for register coloring and register stackifying. These passes are not yet enabled by default. llvm-svn: 253217
2015-11-17 00:18:28 +08:00
WebAssemblyRegStackify.cpp
[WebAssembly] Move register stackification and coloring to a late phase. Move the register stackification and coloring passes to run very late, after PEI, tail duplication, and most other passes. This means that all code emitted and expanded by those passes is now exposed to these passes. This also eliminates the need for prologue/epilogue code to be manually stackified, which significantly simplifies the code. This does require running LiveIntervals a second time. It's useful to think of these late passes not as late optimization passes, but as a domain-specific compression algorithm based on knowledge of liveness information. It's used to compress the code after all conventional optimizations are complete, which is why it uses LiveIntervals at a phase when actual optimization passes don't typically need it. Differential Revision: http://reviews.llvm.org/D20075 llvm-svn: 269012
2016-05-10 12:24:02 +08:00
WebAssemblyReplacePhysRegs.cpp
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
2015-06-30 07:51:55 +08:00
WebAssemblySelectionDAGInfo.cpp
[WebAssembly] Implement unaligned loads and stores. Differential Revision: http://reviews.llvm.org/D16534 llvm-svn: 258779
2016-01-26 11:39:31 +08:00
WebAssemblySetP2AlignOperands.cpp
[WebAssembly] Support for register stackifying with load and store instructions. llvm-svn: 254076
2015-11-26 00:55:01 +08:00
WebAssemblyStoreResults.cpp
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
2015-06-30 07:51:55 +08:00
WebAssemblySubtarget.cpp
WebAssemblyTargetMachine.cpp
[WebAssembly] Convert WebAssemblyTargetObjectFile to TargetLoweringObjectFileELF llvm-svn: 255877
2015-12-17 12:55:44 +08:00
WebAssemblyTargetObjectFile.cpp
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
2015-06-30 07:51:55 +08:00
WebAssemblyTargetTransformInfo.cpp
)
add_dependencies(LLVMWebAssemblyCodeGen intrinsics_gen)
[WebAssembly] Implement a prototype instruction encoder and disassembler. This is using an extremely simple temporary made-up binary format, not the official binary format (which isn't defined yet). llvm-svn: 257440
2016-01-12 11:32:29 +08:00
add_subdirectory(Disassembler)
[WebAssembly] Initial WebAssembly backend This WebAssembly backend is just a skeleton at this time and is not yet functional. llvm-svn: 241022
2015-06-30 07:51:55 +08:00
add_subdirectory(InstPrinter)
add_subdirectory(MCTargetDesc)
[WebAssembly] Minor code cleanups. NFC. llvm-svn: 257128
2016-01-08 09:06:00 +08:00
add_subdirectory(TargetInfo)