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llvm-project/llvm/lib/Target/PowerPC/PPCSchedule.td

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Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
2012-02-18 20:03:15 +08:00
//===-- PPCSchedule.td - PowerPC Scheduling Definitions ----*- tablegen -*-===//
//
Checking in first round of scheduling tablegen files. Not tied in as yet. llvm-svn: 23786
2005-10-19 00:23:40 +08:00
// The LLVM Compiler Infrastructure
//
Remove attribution from file headers, per discussion on llvmdev. llvm-svn: 45418
2007-12-30 04:36:04 +08:00
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. llvm-svn: 150878
2012-02-18 20:03:15 +08:00
//
Checking in first round of scheduling tablegen files. Not tied in as yet. llvm-svn: 23786
2005-10-19 00:23:40 +08:00
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
// Instruction Itinerary classes used for PowerPC
//
Add IIC_ prefix to PPC instruction-class names This adds the IIC_ prefix to the instruction itinerary class names, giving the PPC backend a naming convention for itinerary classes that is more consistent with that used by the X86 and ARM backends. Instruction scheduling in the PPC backend needs a bunch of cleanup and improvement (especially for the ooo cores). This is just a preliminary step. No functionality change intended. llvm-svn: 195890
2013-11-28 07:26:09 +08:00
def IIC_IntSimple : InstrItinClass;
def IIC_IntGeneral : InstrItinClass;
def IIC_IntCompare : InstrItinClass;
[PowerPC] Better scheduling for isel on P7/P8 isel is actually a cracked instruction on the P7/P8, and must start a dispatch group. The scheduling model should reflect this so that we don't bunch too many of them together when possible. Thanks to Bill Schmidt and Pat Haugen for helping to sort this out. llvm-svn: 227758
2015-02-02 01:52:16 +08:00
def IIC_IntISEL : InstrItinClass;
Add IIC_ prefix to PPC instruction-class names This adds the IIC_ prefix to the instruction itinerary class names, giving the PPC backend a naming convention for itinerary classes that is more consistent with that used by the X86 and ARM backends. Instruction scheduling in the PPC backend needs a bunch of cleanup and improvement (especially for the ooo cores). This is just a preliminary step. No functionality change intended. llvm-svn: 195890
2013-11-28 07:26:09 +08:00
def IIC_IntDivD : InstrItinClass;
def IIC_IntDivW : InstrItinClass;
def IIC_IntMFFS : InstrItinClass;
def IIC_IntMFVSCR : InstrItinClass;
def IIC_IntMTFSB0 : InstrItinClass;
def IIC_IntMTSRD : InstrItinClass;
def IIC_IntMulHD : InstrItinClass;
def IIC_IntMulHW : InstrItinClass;
def IIC_IntMulHWU : InstrItinClass;
def IIC_IntMulLI : InstrItinClass;
def IIC_IntRFID : InstrItinClass;
def IIC_IntRotateD : InstrItinClass;
def IIC_IntRotateDI : InstrItinClass;
def IIC_IntRotate : InstrItinClass;
def IIC_IntShift : InstrItinClass;
def IIC_IntTrapD : InstrItinClass;
def IIC_IntTrapW : InstrItinClass;
def IIC_BrB : InstrItinClass;
def IIC_BrCR : InstrItinClass;
def IIC_BrMCR : InstrItinClass;
def IIC_BrMCRX : InstrItinClass;
def IIC_LdStDCBA : InstrItinClass;
def IIC_LdStDCBF : InstrItinClass;
def IIC_LdStDCBI : InstrItinClass;
def IIC_LdStLoad : InstrItinClass;
def IIC_LdStLoadUpd : InstrItinClass;
Split some PPC itinerary classes In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). llvm-svn: 195980
2013-12-01 04:41:13 +08:00
def IIC_LdStLoadUpdX : InstrItinClass;
Add IIC_ prefix to PPC instruction-class names This adds the IIC_ prefix to the instruction itinerary class names, giving the PPC backend a naming convention for itinerary classes that is more consistent with that used by the X86 and ARM backends. Instruction scheduling in the PPC backend needs a bunch of cleanup and improvement (especially for the ooo cores). This is just a preliminary step. No functionality change intended. llvm-svn: 195890
2013-11-28 07:26:09 +08:00
def IIC_LdStStore : InstrItinClass;
def IIC_LdStStoreUpd : InstrItinClass;
def IIC_LdStDSS : InstrItinClass;
def IIC_LdStICBI : InstrItinClass;
def IIC_LdStLD : InstrItinClass;
def IIC_LdStLDU : InstrItinClass;
Split some PPC itinerary classes In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). llvm-svn: 195980
2013-12-01 04:41:13 +08:00
def IIC_LdStLDUX : InstrItinClass;
Add IIC_ prefix to PPC instruction-class names This adds the IIC_ prefix to the instruction itinerary class names, giving the PPC backend a naming convention for itinerary classes that is more consistent with that used by the X86 and ARM backends. Instruction scheduling in the PPC backend needs a bunch of cleanup and improvement (especially for the ooo cores). This is just a preliminary step. No functionality change intended. llvm-svn: 195890
2013-11-28 07:26:09 +08:00
def IIC_LdStLDARX : InstrItinClass;
def IIC_LdStLFD : InstrItinClass;
def IIC_LdStLFDU : InstrItinClass;
Split some PPC itinerary classes In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). llvm-svn: 195980
2013-12-01 04:41:13 +08:00
def IIC_LdStLFDUX : InstrItinClass;
Add IIC_ prefix to PPC instruction-class names This adds the IIC_ prefix to the instruction itinerary class names, giving the PPC backend a naming convention for itinerary classes that is more consistent with that used by the X86 and ARM backends. Instruction scheduling in the PPC backend needs a bunch of cleanup and improvement (especially for the ooo cores). This is just a preliminary step. No functionality change intended. llvm-svn: 195890
2013-11-28 07:26:09 +08:00
def IIC_LdStLHA : InstrItinClass;
def IIC_LdStLHAU : InstrItinClass;
Split some PPC itinerary classes In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). llvm-svn: 195980
2013-12-01 04:41:13 +08:00
def IIC_LdStLHAUX : InstrItinClass;
Add IIC_ prefix to PPC instruction-class names This adds the IIC_ prefix to the instruction itinerary class names, giving the PPC backend a naming convention for itinerary classes that is more consistent with that used by the X86 and ARM backends. Instruction scheduling in the PPC backend needs a bunch of cleanup and improvement (especially for the ooo cores). This is just a preliminary step. No functionality change intended. llvm-svn: 195890
2013-11-28 07:26:09 +08:00
def IIC_LdStLMW : InstrItinClass;
def IIC_LdStLVecX : InstrItinClass;
def IIC_LdStLWA : InstrItinClass;
def IIC_LdStLWARX : InstrItinClass;
def IIC_LdStSLBIA : InstrItinClass;
def IIC_LdStSLBIE : InstrItinClass;
def IIC_LdStSTD : InstrItinClass;
def IIC_LdStSTDCX : InstrItinClass;
def IIC_LdStSTDU : InstrItinClass;
Split some PPC itinerary classes In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). llvm-svn: 195980
2013-12-01 04:41:13 +08:00
def IIC_LdStSTDUX : InstrItinClass;
Add IIC_ prefix to PPC instruction-class names This adds the IIC_ prefix to the instruction itinerary class names, giving the PPC backend a naming convention for itinerary classes that is more consistent with that used by the X86 and ARM backends. Instruction scheduling in the PPC backend needs a bunch of cleanup and improvement (especially for the ooo cores). This is just a preliminary step. No functionality change intended. llvm-svn: 195890
2013-11-28 07:26:09 +08:00
def IIC_LdStSTFD : InstrItinClass;
def IIC_LdStSTFDU : InstrItinClass;
def IIC_LdStSTVEBX : InstrItinClass;
def IIC_LdStSTWCX : InstrItinClass;
def IIC_LdStSync : InstrItinClass;
[Power9] Implement copy-paste, msgsync, slb, and stop instructions This patch implements the following BookII and Book III instructions: - copy copy_first cp_abort paste paste. paste_last - msgsync - slbieg slbsync - stop Total 10 instructions Reviewers: nemanjai hfinkel tjablin amehsan kbarton llvm-svn: 265504
2016-04-06 09:46:45 +08:00
def IIC_LdStCOPY : InstrItinClass;
def IIC_LdStPASTE : InstrItinClass;
Add IIC_ prefix to PPC instruction-class names This adds the IIC_ prefix to the instruction itinerary class names, giving the PPC backend a naming convention for itinerary classes that is more consistent with that used by the X86 and ARM backends. Instruction scheduling in the PPC backend needs a bunch of cleanup and improvement (especially for the ooo cores). This is just a preliminary step. No functionality change intended. llvm-svn: 195890
2013-11-28 07:26:09 +08:00
def IIC_SprISYNC : InstrItinClass;
def IIC_SprMFSR : InstrItinClass;
def IIC_SprMTMSR : InstrItinClass;
def IIC_SprMTSR : InstrItinClass;
def IIC_SprTLBSYNC : InstrItinClass;
def IIC_SprMFCR : InstrItinClass;
Split some PPC itinerary classes In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). llvm-svn: 195980
2013-12-01 04:41:13 +08:00
def IIC_SprMFCRF : InstrItinClass;
Add IIC_ prefix to PPC instruction-class names This adds the IIC_ prefix to the instruction itinerary class names, giving the PPC backend a naming convention for itinerary classes that is more consistent with that used by the X86 and ARM backends. Instruction scheduling in the PPC backend needs a bunch of cleanup and improvement (especially for the ooo cores). This is just a preliminary step. No functionality change intended. llvm-svn: 195890
2013-11-28 07:26:09 +08:00
def IIC_SprMFMSR : InstrItinClass;
def IIC_SprMFSPR : InstrItinClass;
def IIC_SprMFTB : InstrItinClass;
def IIC_SprMTSPR : InstrItinClass;
def IIC_SprMTSRIN : InstrItinClass;
def IIC_SprRFI : InstrItinClass;
def IIC_SprSC : InstrItinClass;
def IIC_FPGeneral : InstrItinClass;
def IIC_FPAddSub : InstrItinClass;
def IIC_FPCompare : InstrItinClass;
def IIC_FPDivD : InstrItinClass;
def IIC_FPDivS : InstrItinClass;
def IIC_FPFused : InstrItinClass;
def IIC_FPRes : InstrItinClass;
Split some PPC itinerary classes In preparation for adding scheduling definitions for the POWER7, split some PPC itinerary classes so that the P7's latencies and hazards can be better described. For the most part, this means differentiating indexed from non-index pre-increment loads and stores. Also, differentiate single from double-precision sqrt. No functionality change intended (except for a more-specific latency for single-precision sqrt on the A2). llvm-svn: 195980
2013-12-01 04:41:13 +08:00
def IIC_FPSqrtD : InstrItinClass;
def IIC_FPSqrtS : InstrItinClass;
Add IIC_ prefix to PPC instruction-class names This adds the IIC_ prefix to the instruction itinerary class names, giving the PPC backend a naming convention for itinerary classes that is more consistent with that used by the X86 and ARM backends. Instruction scheduling in the PPC backend needs a bunch of cleanup and improvement (especially for the ooo cores). This is just a preliminary step. No functionality change intended. llvm-svn: 195890
2013-11-28 07:26:09 +08:00
def IIC_VecGeneral : InstrItinClass;
def IIC_VecFP : InstrItinClass;
def IIC_VecFPCompare : InstrItinClass;
def IIC_VecComplex : InstrItinClass;
def IIC_VecPerm : InstrItinClass;
def IIC_VecFPRound : InstrItinClass;
def IIC_VecVSL : InstrItinClass;
def IIC_VecVSR : InstrItinClass;
def IIC_SprMTMSRD : InstrItinClass;
def IIC_SprSLIE : InstrItinClass;
def IIC_SprSLBIE : InstrItinClass;
[Power9] Implement copy-paste, msgsync, slb, and stop instructions This patch implements the following BookII and Book III instructions: - copy copy_first cp_abort paste paste. paste_last - msgsync - slbieg slbsync - stop Total 10 instructions Reviewers: nemanjai hfinkel tjablin amehsan kbarton llvm-svn: 265504
2016-04-06 09:46:45 +08:00
def IIC_SprSLBIEG : InstrItinClass;
Add IIC_ prefix to PPC instruction-class names This adds the IIC_ prefix to the instruction itinerary class names, giving the PPC backend a naming convention for itinerary classes that is more consistent with that used by the X86 and ARM backends. Instruction scheduling in the PPC backend needs a bunch of cleanup and improvement (especially for the ooo cores). This is just a preliminary step. No functionality change intended. llvm-svn: 195890
2013-11-28 07:26:09 +08:00
def IIC_SprSLBMTE : InstrItinClass;
def IIC_SprSLBMFEE : InstrItinClass;
[PowerPC] Add asm parser/disassembler support for hrfid,nap,slbmfev These few book-III instructions are used by the Linux kernel. Partially fixes PR24796. llvm-svn: 280560
2016-09-03 07:42:01 +08:00
def IIC_SprSLBMFEV : InstrItinClass;
Add IIC_ prefix to PPC instruction-class names This adds the IIC_ prefix to the instruction itinerary class names, giving the PPC backend a naming convention for itinerary classes that is more consistent with that used by the X86 and ARM backends. Instruction scheduling in the PPC backend needs a bunch of cleanup and improvement (especially for the ooo cores). This is just a preliminary step. No functionality change intended. llvm-svn: 195890
2013-11-28 07:26:09 +08:00
def IIC_SprSLBIA : InstrItinClass;
[Power9] Implement copy-paste, msgsync, slb, and stop instructions This patch implements the following BookII and Book III instructions: - copy copy_first cp_abort paste paste. paste_last - msgsync - slbieg slbsync - stop Total 10 instructions Reviewers: nemanjai hfinkel tjablin amehsan kbarton llvm-svn: 265504
2016-04-06 09:46:45 +08:00
def IIC_SprSLBSYNC : InstrItinClass;
tlbia support llvm-svn: 214640
2014-08-03 04:16:29 +08:00
def IIC_SprTLBIA : InstrItinClass;
Add IIC_ prefix to PPC instruction-class names This adds the IIC_ prefix to the instruction itinerary class names, giving the PPC backend a naming convention for itinerary classes that is more consistent with that used by the X86 and ARM backends. Instruction scheduling in the PPC backend needs a bunch of cleanup and improvement (especially for the ooo cores). This is just a preliminary step. No functionality change intended. llvm-svn: 195890
2013-11-28 07:26:09 +08:00
def IIC_SprTLBIEL : InstrItinClass;
def IIC_SprTLBIE : InstrItinClass;
[Power9] Implement copy-paste, msgsync, slb, and stop instructions This patch implements the following BookII and Book III instructions: - copy copy_first cp_abort paste paste. paste_last - msgsync - slbieg slbsync - stop Total 10 instructions Reviewers: nemanjai hfinkel tjablin amehsan kbarton llvm-svn: 265504
2016-04-06 09:46:45 +08:00
def IIC_SprABORT : InstrItinClass;
def IIC_SprMSGSYNC : InstrItinClass;
def IIC_SprSTOP : InstrItinClass;
Add some Book-E instructions to the asm parser and printer. Summary: Adds the following instructions: * mfpmr * mtpmr * icblc * icblq * icbtls Fix the scheduling for mtspr on e5500, which uses CFX0, instead of SFX0/SFX1 as on e500mc. Addresses PR 31538. Differential Revision: https://reviews.llvm.org/D29002 llvm-svn: 293417
2017-01-29 12:55:57 +08:00
def IIC_SprMFPMR : InstrItinClass;
def IIC_SprMTPMR : InstrItinClass;
Checking in first round of scheduling tablegen files. Not tied in as yet. llvm-svn: 23786
2005-10-19 00:23:40 +08:00
//===----------------------------------------------------------------------===//
// Processor instruction itineraries.
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
include "PPCScheduleG3.td"
Add PPC 440 scheduler and some associated tests llvm-svn: 142170
2011-10-17 12:03:49 +08:00
include "PPCSchedule440.td"
Added InstrSchedClass to each of the PowerPC Instructions. Note that when adding new instructions that you should refer to the table at the bottom of PPCSchedule.td. llvm-svn: 23830
2005-10-20 03:51:16 +08:00
include "PPCScheduleG4.td"
include "PPCScheduleG4Plus.td"
include "PPCScheduleG5.td"
Add a scheduling model (with itinerary) for the PPC POWER7 This adds a scheduling model for the POWER7 (P7) core, and enables the machine-instruction scheduler when targeting the P7. Scheduling for the P7, like earlier ooo PPC cores, requires considering both dispatch group hazards, and functional unit resources and latencies. These are both modeled in a combined itinerary. Dispatch group formation is still handled by the post-RA scheduler (which still needs to be updated for the P7, but nevertheless does a pretty good job). One interesting aspect of this change is that I've also enabled to use of AA duing CodeGen for the P7 (just as it is for the embedded cores). The benchmark results seem to support this decision (see below), and while this is normally useful for in-order cores, and not for ooo cores like the P7, I think that the dispatch slot hazards are enough like in-order resources to make the AA useful. Test suite significant performance differences (where negative is a speedup, and positive is a regression) vs. the current situation: MultiSource/Benchmarks/BitBench/drop3/drop3 with AA: N/A without AA: -28.7614% +/- 19.8356% (significantly against AA) MultiSource/Benchmarks/FreeBench/neural/neural with AA: -17.7406% +/- 11.2712% without AA: N/A (significantly in favor of AA) MultiSource/Benchmarks/SciMark2-C/scimark2 with AA: -11.2079% +/- 1.80543% without AA: -11.3263% +/- 2.79651% MultiSource/Benchmarks/TSVC/Symbolics-flt/Symbolics-flt with AA: -41.8649% +/- 17.0053% without AA: -34.5256% +/- 23.7072% MultiSource/Benchmarks/mafft/pairlocalalign with AA: 25.3016% +/- 17.8614% without AA: 38.6629% +/- 14.9391% (significantly in favor of AA) MultiSource/Benchmarks/sim/sim with AA: N/A without AA: 13.4844% +/- 7.18195% (significantly in favor of AA) SingleSource/Benchmarks/BenchmarkGame/Large/fasta with AA: 15.0664% +/- 6.70216% without AA: 12.7747% +/- 8.43043% SingleSource/Benchmarks/BenchmarkGame/puzzle with AA: 82.2713% +/- 26.3567% without AA: 75.7525% +/- 41.1842% SingleSource/Benchmarks/Misc/flops-2 with AA: -37.1621% +/- 20.7964% without AA: -35.2342% +/- 20.2999% (significantly in favor of AA) These are 99.5% confidence intervals from 5 runs per configuration. Regarding the choice to turn on AA during CodeGen, of these results, four seem significantly in favor of using AA, and one seems significantly against. I'm not making this decision based on these numbers alone, but these results seem consistent with results I have from other tests, and so I think that, on balance, using AA is a win. llvm-svn: 195981
2013-12-01 04:55:12 +08:00
include "PPCScheduleP7.td"
Add TableGen info for Power8. This is based on the Power7 version, with units added and renamed to match P8. Differential Revision: http://reviews.llvm.org/D6358 llvm-svn: 223257
2014-12-04 02:46:30 +08:00
include "PPCScheduleP8.td"
[Power9] Processor Model for Scheduling PWR9 processor model for instruction scheduling. A subsequent patch will migrate PWR9 to Post RA MIScheduler. https://reviews.llvm.org/D24525 llvm-svn: 290102
2016-12-19 21:35:45 +08:00
include "PPCScheduleP9.td"
Add instruction itinerary for the PPC64 A2 core. This adds a full itinerary for IBM's PPC64 A2 embedded core. These cores form the basis for the CPUs in the new IBM BG/Q supercomputer. llvm-svn: 153842
2012-04-02 03:22:40 +08:00
include "PPCScheduleA2.td"
Add PowerPC e500(v2) core scheduler and directives. Differential Revision: https://reviews.llvm.org/D44828 llvm-svn: 337345
2018-07-18 12:24:49 +08:00
include "PPCScheduleE500.td"
Add PPC Freescale e500mc and e5500 subtargets. Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to the PowerPC backend. Patch by Tobias von Koch. llvm-svn: 162764
2012-08-29 00:12:39 +08:00
include "PPCScheduleE500mc.td"
include "PPCScheduleE5500.td"