maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/ARM/hidden-vis-3.ll

18 lines
485 B
LLVM
Raw Normal View History

ARM Darwin default relocation model is PIC. This matches clang, so default options in llc and friends are now closer to clang's defaults. llvm-svn: 140863
2011-10-01 01:41:35 +08:00
; RUN: llc < %s -relocation-model=dynamic-no-pic -mtriple=arm-apple-darwin9 | FileCheck %s
Clean up some ARM GV asm printing out; minor fixes to match what gcc does. llvm-svn: 60621
2008-12-06 10:00:55 +08:00
@x = external hidden global i32 ; <i32*> [#uses=1]
@y = extern_weak hidden global i32 ; <i32*> [#uses=1]
define i32 @t() nounwind readonly {
entry:
Start function numbering at 0. llvm-svn: 101638
2010-04-18 00:29:15 +08:00
; CHECK: LCPI0_0:
Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172. llvm-svn: 80904
2009-09-03 15:04:02 +08:00
; CHECK-NEXT: .long _x
Start function numbering at 0. llvm-svn: 101638
2010-04-18 00:29:15 +08:00
; CHECK: LCPI0_1:
Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172. llvm-svn: 80904
2009-09-03 15:04:02 +08:00
; CHECK-NEXT: .long _y
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i32, i32* @x, align 4 ; <i32> [#uses=1]
%1 = load i32, i32* @y, align 4 ; <i32> [#uses=1]
Clean up some ARM GV asm printing out; minor fixes to match what gcc does. llvm-svn: 60621
2008-12-06 10:00:55 +08:00
%2 = add i32 %1, %0 ; <i32> [#uses=1]
ret i32 %2
}