2013-02-20 00:38:32 +08:00
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//===-- X86AsmPrinter.h - X86 implementation of AsmPrinter ------*- C++ -*-===//
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2005-07-02 06:44:09 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2005-07-02 06:44:09 +08:00
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//
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//===----------------------------------------------------------------------===//
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2014-08-14 00:26:38 +08:00
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#ifndef LLVM_LIB_TARGET_X86_X86ASMPRINTER_H
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#define LLVM_LIB_TARGET_X86_X86ASMPRINTER_H
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2005-07-02 06:44:09 +08:00
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2014-03-19 14:53:25 +08:00
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#include "X86Subtarget.h"
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2008-06-28 19:08:27 +08:00
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#include "llvm/CodeGen/AsmPrinter.h"
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2015-06-16 02:44:08 +08:00
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#include "llvm/CodeGen/FaultMaps.h"
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2013-11-01 06:11:56 +08:00
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#include "llvm/CodeGen/StackMaps.h"
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2017-10-25 05:29:14 +08:00
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#include "llvm/MC/MCCodeEmitter.h"
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2014-03-19 14:53:25 +08:00
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#include "llvm/Target/TargetMachine.h"
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2005-07-02 06:44:09 +08:00
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2014-07-25 04:40:55 +08:00
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// Implemented in X86MCInstLower.cpp
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namespace {
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class X86MCInstLower;
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}
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2005-07-02 06:44:09 +08:00
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namespace llvm {
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2009-06-24 13:46:28 +08:00
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class MCStreamer;
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2014-05-04 08:03:41 +08:00
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class MCSymbol;
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2008-06-28 19:08:27 +08:00
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2010-05-12 04:16:09 +08:00
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class LLVM_LIBRARY_VISIBILITY X86AsmPrinter : public AsmPrinter {
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2008-06-28 19:08:27 +08:00
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const X86Subtarget *Subtarget;
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2013-11-01 06:11:56 +08:00
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StackMaps SM;
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2015-06-16 02:44:08 +08:00
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FaultMaps FM;
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2016-04-19 13:24:47 +08:00
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std::unique_ptr<MCCodeEmitter> CodeEmitter;
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[codeview] Implement FPO data assembler directives
Summary:
This adds a set of new directives that describe 32-bit x86 prologues.
The directives are limited and do not expose the full complexity of
codeview FPO data. They are merely a convenience for the compiler to
generate more readable assembly so we don't need to generate tons of
labels in CodeGen. If our prologue emission changes in the future, we
can change the set of available directives to suit our needs. These are
modelled after the .seh_ directives, which use a different format that
interacts with exception handling.
The directives are:
.cv_fpo_proc _foo
.cv_fpo_pushreg ebp/ebx/etc
.cv_fpo_setframe ebp/esi/etc
.cv_fpo_stackalloc 200
.cv_fpo_endprologue
.cv_fpo_endproc
.cv_fpo_data _foo
I tried to follow the implementation of ARM EHABI CFI directives by
sinking most directives out of MCStreamer and into X86TargetStreamer.
This helps avoid polluting non-X86 code with WinCOFF specific logic.
I used cdb to confirm that this can show locals in parent CSRs in a few
cases, most importantly the one where we use ESI as a frame pointer,
i.e. the one in http://crbug.com/756153#c28
Once we have cdb integration in debuginfo-tests, we can add integration
tests there.
Reviewers: majnemer, hans
Subscribers: aemerson, mgorny, kristof.beyls, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D38776
llvm-svn: 315513
2017-10-12 05:24:33 +08:00
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bool EmitFPOData = false;
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Introduce the "retpoline" x86 mitigation technique for variant #2 of the speculative execution vulnerabilities disclosed today, specifically identified by CVE-2017-5715, "Branch Target Injection", and is one of the two halves to Spectre..
Summary:
First, we need to explain the core of the vulnerability. Note that this
is a very incomplete description, please see the Project Zero blog post
for details:
https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html
The basis for branch target injection is to direct speculative execution
of the processor to some "gadget" of executable code by poisoning the
prediction of indirect branches with the address of that gadget. The
gadget in turn contains an operation that provides a side channel for
reading data. Most commonly, this will look like a load of secret data
followed by a branch on the loaded value and then a load of some
predictable cache line. The attacker then uses timing of the processors
cache to determine which direction the branch took *in the speculative
execution*, and in turn what one bit of the loaded value was. Due to the
nature of these timing side channels and the branch predictor on Intel
processors, this allows an attacker to leak data only accessible to
a privileged domain (like the kernel) back into an unprivileged domain.
The goal is simple: avoid generating code which contains an indirect
branch that could have its prediction poisoned by an attacker. In many
cases, the compiler can simply use directed conditional branches and
a small search tree. LLVM already has support for lowering switches in
this way and the first step of this patch is to disable jump-table
lowering of switches and introduce a pass to rewrite explicit indirectbr
sequences into a switch over integers.
However, there is no fully general alternative to indirect calls. We
introduce a new construct we call a "retpoline" to implement indirect
calls in a non-speculatable way. It can be thought of loosely as
a trampoline for indirect calls which uses the RET instruction on x86.
Further, we arrange for a specific call->ret sequence which ensures the
processor predicts the return to go to a controlled, known location. The
retpoline then "smashes" the return address pushed onto the stack by the
call with the desired target of the original indirect call. The result
is a predicted return to the next instruction after a call (which can be
used to trap speculative execution within an infinite loop) and an
actual indirect branch to an arbitrary address.
On 64-bit x86 ABIs, this is especially easily done in the compiler by
using a guaranteed scratch register to pass the target into this device.
For 32-bit ABIs there isn't a guaranteed scratch register and so several
different retpoline variants are introduced to use a scratch register if
one is available in the calling convention and to otherwise use direct
stack push/pop sequences to pass the target address.
This "retpoline" mitigation is fully described in the following blog
post: https://support.google.com/faqs/answer/7625886
We also support a target feature that disables emission of the retpoline
thunk by the compiler to allow for custom thunks if users want them.
These are particularly useful in environments like kernels that
routinely do hot-patching on boot and want to hot-patch their thunk to
different code sequences. They can write this custom thunk and use
`-mretpoline-external-thunk` *in addition* to `-mretpoline`. In this
case, on x86-64 thu thunk names must be:
```
__llvm_external_retpoline_r11
```
or on 32-bit:
```
__llvm_external_retpoline_eax
__llvm_external_retpoline_ecx
__llvm_external_retpoline_edx
__llvm_external_retpoline_push
```
And the target of the retpoline is passed in the named register, or in
the case of the `push` suffix on the top of the stack via a `pushl`
instruction.
There is one other important source of indirect branches in x86 ELF
binaries: the PLT. These patches also include support for LLD to
generate PLT entries that perform a retpoline-style indirection.
The only other indirect branches remaining that we are aware of are from
precompiled runtimes (such as crt0.o and similar). The ones we have
found are not really attackable, and so we have not focused on them
here, but eventually these runtimes should also be replicated for
retpoline-ed configurations for completeness.
For kernels or other freestanding or fully static executables, the
compiler switch `-mretpoline` is sufficient to fully mitigate this
particular attack. For dynamic executables, you must compile *all*
libraries with `-mretpoline` and additionally link the dynamic
executable and all shared libraries with LLD and pass `-z retpolineplt`
(or use similar functionality from some other linker). We strongly
recommend also using `-z now` as non-lazy binding allows the
retpoline-mitigated PLT to be substantially smaller.
When manually apply similar transformations to `-mretpoline` to the
Linux kernel we observed very small performance hits to applications
running typical workloads, and relatively minor hits (approximately 2%)
even for extremely syscall-heavy applications. This is largely due to
the small number of indirect branches that occur in performance
sensitive paths of the kernel.
When using these patches on statically linked applications, especially
C++ applications, you should expect to see a much more dramatic
performance hit. For microbenchmarks that are switch, indirect-, or
virtual-call heavy we have seen overheads ranging from 10% to 50%.
However, real-world workloads exhibit substantially lower performance
impact. Notably, techniques such as PGO and ThinLTO dramatically reduce
the impact of hot indirect calls (by speculatively promoting them to
direct calls) and allow optimized search trees to be used to lower
switches. If you need to deploy these techniques in C++ applications, we
*strongly* recommend that you ensure all hot call targets are statically
linked (avoiding PLT indirection) and use both PGO and ThinLTO. Well
tuned servers using all of these techniques saw 5% - 10% overhead from
the use of retpoline.
We will add detailed documentation covering these components in
subsequent patches, but wanted to make the core functionality available
as soon as possible. Happy for more code review, but we'd really like to
get these patches landed and backported ASAP for obvious reasons. We're
planning to backport this to both 6.0 and 5.0 release streams and get
a 5.0 release with just this cherry picked ASAP for distros and vendors.
This patch is the work of a number of people over the past month: Eric, Reid,
Rui, and myself. I'm mailing it out as a single commit due to the time
sensitive nature of landing this and the need to backport it. Huge thanks to
everyone who helped out here, and everyone at Intel who helped out in
discussions about how to craft this. Also, credit goes to Paul Turner (at
Google, but not an LLVM contributor) for much of the underlying retpoline
design.
Reviewers: echristo, rnk, ruiu, craig.topper, DavidKreitzer
Subscribers: sanjoy, emaste, mcrosier, mgorny, mehdi_amini, hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D41723
llvm-svn: 323155
2018-01-23 06:05:25 +08:00
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bool NeedsRetpoline = false;
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2013-11-01 06:11:56 +08:00
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2014-07-25 04:40:55 +08:00
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// This utility class tracks the length of a stackmap instruction's 'shadow'.
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// It is used by the X86AsmPrinter to ensure that the stackmap shadow
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// invariants (i.e. no other stackmaps, patchpoints, or control flow within
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// the shadow) are met, while outputting a minimal number of NOPs for padding.
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//
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// To minimise the number of NOPs used, the shadow tracker counts the number
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// of instruction bytes output since the last stackmap. Only if there are too
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// few instruction bytes to cover the shadow are NOPs used for padding.
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class StackMapShadowTracker {
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public:
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2016-04-20 02:48:16 +08:00
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void startFunction(MachineFunction &MF) {
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this->MF = &MF;
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}
|
2016-04-19 13:24:47 +08:00
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void count(MCInst &Inst, const MCSubtargetInfo &STI,
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MCCodeEmitter *CodeEmitter);
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2014-07-25 10:29:19 +08:00
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// Called to signal the start of a shadow of RequiredSize bytes.
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2014-07-25 04:40:55 +08:00
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void reset(unsigned RequiredSize) {
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RequiredShadowSize = RequiredSize;
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CurrentShadowSize = 0;
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2014-07-25 10:29:19 +08:00
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InShadow = true;
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2014-07-25 04:40:55 +08:00
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}
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2014-07-25 10:29:19 +08:00
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// Called before every stackmap/patchpoint, and at the end of basic blocks,
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// to emit any necessary padding-NOPs.
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2014-07-25 04:40:55 +08:00
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void emitShadowPadding(MCStreamer &OutStreamer, const MCSubtargetInfo &STI);
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private:
|
2015-02-20 16:01:55 +08:00
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const MachineFunction *MF;
|
2016-04-20 02:48:16 +08:00
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bool InShadow = false;
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2014-07-25 10:29:19 +08:00
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// RequiredShadowSize holds the length of the shadow specified in the most
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// recently encountered STACKMAP instruction.
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// CurrentShadowSize counts the number of bytes encoded since the most
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// recently encountered STACKMAP, stopping when that number is greater than
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// or equal to RequiredShadowSize.
|
2016-04-20 02:48:16 +08:00
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unsigned RequiredShadowSize = 0, CurrentShadowSize = 0;
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2014-07-25 04:40:55 +08:00
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};
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StackMapShadowTracker SMShadowTracker;
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// All instructions emitted by the X86AsmPrinter should use this helper
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// method.
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//
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// This helper function invokes the SMShadowTracker on each instruction before
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// outputting it to the OutStream. This allows the shadow tracker to minimise
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// the number of NOPs used for stackmap padding.
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void EmitAndCountInstruction(MCInst &Inst);
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void LowerSTACKMAP(const MachineInstr &MI);
|
2015-04-22 14:02:31 +08:00
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void LowerPATCHPOINT(const MachineInstr &MI, X86MCInstLower &MCIL);
|
2015-05-07 07:53:26 +08:00
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void LowerSTATEPOINT(const MachineInstr &MI, X86MCInstLower &MCIL);
|
2017-02-08 03:19:49 +08:00
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void LowerFAULTING_OP(const MachineInstr &MI, X86MCInstLower &MCIL);
|
2016-04-19 13:24:47 +08:00
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void LowerPATCHABLE_OP(const MachineInstr &MI, X86MCInstLower &MCIL);
|
2014-07-25 04:40:55 +08:00
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void LowerTlsAddr(X86MCInstLower &MCInstLowering, const MachineInstr &MI);
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XRay: Add entry and exit sleds
Summary:
In this patch we implement the following parts of XRay:
- Supporting a function attribute named 'function-instrument' which currently only supports 'xray-always'. We should be able to use this attribute for other instrumentation approaches.
- Supporting a function attribute named 'xray-instruction-threshold' used to determine whether a function is instrumented with a minimum number of instructions (IR instruction counts).
- X86-specific nop sleds as described in the white paper.
- A machine function pass that adds the different instrumentation marker instructions at a very late stage.
- A way of identifying which return opcode is considered "normal" for each architecture.
There are some caveats here:
1) We don't handle PATCHABLE_RET in platforms other than x86_64 yet -- this means if IR used PATCHABLE_RET directly instead of a normal ret, instruction lowering for that platform might do the wrong thing. We think this should be handled at instruction selection time to by default be unpacked for platforms where XRay is not availble yet.
2) The generated section for X86 is different from what is described from the white paper for the sole reason that LLVM allows us to do this neatly. We're taking the opportunity to deviate from the white paper from this perspective to allow us to get richer information from the runtime library.
Reviewers: sanjoy, eugenis, kcc, pcc, echristo, rnk
Subscribers: niravd, majnemer, atrick, rnk, emaste, bmakam, mcrosier, mehdi_amini, llvm-commits
Differential Revision: http://reviews.llvm.org/D19904
llvm-svn: 275367
2016-07-14 12:06:33 +08:00
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// XRay-specific lowering for X86.
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void LowerPATCHABLE_FUNCTION_ENTER(const MachineInstr &MI,
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X86MCInstLower &MCIL);
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void LowerPATCHABLE_RET(const MachineInstr &MI, X86MCInstLower &MCIL);
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void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
|
[XRay] Custom event logging intrinsic
This patch introduces an LLVM intrinsic and a target opcode for custom event
logging in XRay. Initially, its use case will be to allow users of XRay to log
some type of string ("poor man's printf"). The target opcode compiles to a noop
sled large enough to enable calling through to a runtime-determined relative
function call. At runtime, when X-Ray is enabled, the sled is replaced by
compiler-rt with a trampoline to the logic for creating the custom log entries.
Future patches will implement the compiler-rt parts and clang-side support for
emitting the IR corresponding to this intrinsic.
Reviewers: timshen, dberris
Subscribers: igorb, pelikan, rSerge, timshen, echristo, dberris, llvm-commits
Differential Revision: https://reviews.llvm.org/D27503
llvm-svn: 302405
2017-05-08 13:45:21 +08:00
|
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void LowerPATCHABLE_EVENT_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
|
2018-04-18 05:30:29 +08:00
|
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void LowerPATCHABLE_TYPED_EVENT_CALL(const MachineInstr &MI,
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X86MCInstLower &MCIL);
|
XRay: Add entry and exit sleds
Summary:
In this patch we implement the following parts of XRay:
- Supporting a function attribute named 'function-instrument' which currently only supports 'xray-always'. We should be able to use this attribute for other instrumentation approaches.
- Supporting a function attribute named 'xray-instruction-threshold' used to determine whether a function is instrumented with a minimum number of instructions (IR instruction counts).
- X86-specific nop sleds as described in the white paper.
- A machine function pass that adds the different instrumentation marker instructions at a very late stage.
- A way of identifying which return opcode is considered "normal" for each architecture.
There are some caveats here:
1) We don't handle PATCHABLE_RET in platforms other than x86_64 yet -- this means if IR used PATCHABLE_RET directly instead of a normal ret, instruction lowering for that platform might do the wrong thing. We think this should be handled at instruction selection time to by default be unpacked for platforms where XRay is not availble yet.
2) The generated section for X86 is different from what is described from the white paper for the sole reason that LLVM allows us to do this neatly. We're taking the opportunity to deviate from the white paper from this perspective to allow us to get richer information from the runtime library.
Reviewers: sanjoy, eugenis, kcc, pcc, echristo, rnk
Subscribers: niravd, majnemer, atrick, rnk, emaste, bmakam, mcrosier, mehdi_amini, llvm-commits
Differential Revision: http://reviews.llvm.org/D19904
llvm-svn: 275367
2016-07-14 12:06:33 +08:00
|
|
|
|
2017-02-01 01:00:27 +08:00
|
|
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void LowerFENTRY_CALL(const MachineInstr &MI, X86MCInstLower &MCIL);
|
|
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|
|
[codeview] Implement FPO data assembler directives
Summary:
This adds a set of new directives that describe 32-bit x86 prologues.
The directives are limited and do not expose the full complexity of
codeview FPO data. They are merely a convenience for the compiler to
generate more readable assembly so we don't need to generate tons of
labels in CodeGen. If our prologue emission changes in the future, we
can change the set of available directives to suit our needs. These are
modelled after the .seh_ directives, which use a different format that
interacts with exception handling.
The directives are:
.cv_fpo_proc _foo
.cv_fpo_pushreg ebp/ebx/etc
.cv_fpo_setframe ebp/esi/etc
.cv_fpo_stackalloc 200
.cv_fpo_endprologue
.cv_fpo_endproc
.cv_fpo_data _foo
I tried to follow the implementation of ARM EHABI CFI directives by
sinking most directives out of MCStreamer and into X86TargetStreamer.
This helps avoid polluting non-X86 code with WinCOFF specific logic.
I used cdb to confirm that this can show locals in parent CSRs in a few
cases, most importantly the one where we use ESI as a frame pointer,
i.e. the one in http://crbug.com/756153#c28
Once we have cdb integration in debuginfo-tests, we can add integration
tests there.
Reviewers: majnemer, hans
Subscribers: aemerson, mgorny, kristof.beyls, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D38776
llvm-svn: 315513
2017-10-12 05:24:33 +08:00
|
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// Choose between emitting .seh_ directives and .cv_fpo_ directives.
|
|
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void EmitSEHInstruction(const MachineInstr *MI);
|
|
|
|
|
XRay: Add entry and exit sleds
Summary:
In this patch we implement the following parts of XRay:
- Supporting a function attribute named 'function-instrument' which currently only supports 'xray-always'. We should be able to use this attribute for other instrumentation approaches.
- Supporting a function attribute named 'xray-instruction-threshold' used to determine whether a function is instrumented with a minimum number of instructions (IR instruction counts).
- X86-specific nop sleds as described in the white paper.
- A machine function pass that adds the different instrumentation marker instructions at a very late stage.
- A way of identifying which return opcode is considered "normal" for each architecture.
There are some caveats here:
1) We don't handle PATCHABLE_RET in platforms other than x86_64 yet -- this means if IR used PATCHABLE_RET directly instead of a normal ret, instruction lowering for that platform might do the wrong thing. We think this should be handled at instruction selection time to by default be unpacked for platforms where XRay is not availble yet.
2) The generated section for X86 is different from what is described from the white paper for the sole reason that LLVM allows us to do this neatly. We're taking the opportunity to deviate from the white paper from this perspective to allow us to get richer information from the runtime library.
Reviewers: sanjoy, eugenis, kcc, pcc, echristo, rnk
Subscribers: niravd, majnemer, atrick, rnk, emaste, bmakam, mcrosier, mehdi_amini, llvm-commits
Differential Revision: http://reviews.llvm.org/D19904
llvm-svn: 275367
2016-07-14 12:06:33 +08:00
|
|
|
public:
|
2017-10-12 07:53:12 +08:00
|
|
|
X86AsmPrinter(TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer);
|
2005-07-02 06:44:09 +08:00
|
|
|
|
2016-10-01 10:56:57 +08:00
|
|
|
StringRef getPassName() const override {
|
2016-11-11 02:39:31 +08:00
|
|
|
return "X86 Assembly Printer";
|
2005-07-02 06:44:09 +08:00
|
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|
}
|
2012-08-02 02:39:17 +08:00
|
|
|
|
2009-09-13 04:34:57 +08:00
|
|
|
const X86Subtarget &getSubtarget() const { return *Subtarget; }
|
2005-07-02 06:44:09 +08:00
|
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|
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2014-03-10 13:29:18 +08:00
|
|
|
void EmitStartOfAsmFile(Module &M) override;
|
2010-03-13 10:10:00 +08:00
|
|
|
|
2014-03-10 13:29:18 +08:00
|
|
|
void EmitEndOfAsmFile(Module &M) override;
|
2012-08-02 02:39:17 +08:00
|
|
|
|
2014-03-10 13:29:18 +08:00
|
|
|
void EmitInstruction(const MachineInstr *MI) override;
|
2012-08-02 02:39:17 +08:00
|
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|
|
2014-07-25 04:40:55 +08:00
|
|
|
void EmitBasicBlockEnd(const MachineBasicBlock &MBB) override {
|
2017-10-24 14:16:03 +08:00
|
|
|
AsmPrinter::EmitBasicBlockEnd(MBB);
|
2015-04-25 03:11:51 +08:00
|
|
|
SMShadowTracker.emitShadowPadding(*OutStreamer, getSubtargetInfo());
|
2014-07-25 04:40:55 +08:00
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}
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2014-03-10 13:29:18 +08:00
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bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &OS) override;
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bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
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unsigned AsmVariant, const char *ExtraCode,
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raw_ostream &OS) override;
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2012-10-09 11:50:37 +08:00
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2014-09-17 17:25:36 +08:00
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bool doInitialization(Module &M) override {
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SMShadowTracker.reset(0);
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SM.reset();
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2017-10-17 19:44:34 +08:00
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FM.reset();
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2014-09-17 17:25:36 +08:00
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return AsmPrinter::doInitialization(M);
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}
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2014-03-10 13:29:18 +08:00
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bool runOnMachineFunction(MachineFunction &F) override;
|
[codeview] Implement FPO data assembler directives
Summary:
This adds a set of new directives that describe 32-bit x86 prologues.
The directives are limited and do not expose the full complexity of
codeview FPO data. They are merely a convenience for the compiler to
generate more readable assembly so we don't need to generate tons of
labels in CodeGen. If our prologue emission changes in the future, we
can change the set of available directives to suit our needs. These are
modelled after the .seh_ directives, which use a different format that
interacts with exception handling.
The directives are:
.cv_fpo_proc _foo
.cv_fpo_pushreg ebp/ebx/etc
.cv_fpo_setframe ebp/esi/etc
.cv_fpo_stackalloc 200
.cv_fpo_endprologue
.cv_fpo_endproc
.cv_fpo_data _foo
I tried to follow the implementation of ARM EHABI CFI directives by
sinking most directives out of MCStreamer and into X86TargetStreamer.
This helps avoid polluting non-X86 code with WinCOFF specific logic.
I used cdb to confirm that this can show locals in parent CSRs in a few
cases, most importantly the one where we use ESI as a frame pointer,
i.e. the one in http://crbug.com/756153#c28
Once we have cdb integration in debuginfo-tests, we can add integration
tests there.
Reviewers: majnemer, hans
Subscribers: aemerson, mgorny, kristof.beyls, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D38776
llvm-svn: 315513
2017-10-12 05:24:33 +08:00
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void EmitFunctionBodyStart() override;
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void EmitFunctionBodyEnd() override;
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2005-07-02 06:44:09 +08:00
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};
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} // end namespace llvm
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#endif
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