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llvm-project/clang/test/CodeGen/riscv-inline-asm.c

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[RISCV][NFC] Add missing test files for D54091 llvm-svn: 363056
2019-06-11 20:49:15 +08:00
// RUN: %clang_cc1 -triple riscv32 -O2 -emit-llvm %s -o - \
// RUN: | FileCheck %s
// RUN: %clang_cc1 -triple riscv64 -O2 -emit-llvm %s -o - \
// RUN: | FileCheck %s
// Test RISC-V specific inline assembly constraints.
void test_I() {
Revert "[CodeGenModule] Assume dso_local for -fpic -fno-semantic-interposition" This reverts commit 789a46f2d742e11edaade28cb59a0f4d2a1d770e. Accidentally committed.
2020-02-04 02:09:39 +08:00
// CHECK-LABEL: define void @test_I()
[RISCV][NFC] Add missing test files for D54091 llvm-svn: 363056
2019-06-11 20:49:15 +08:00
// CHECK: call void asm sideeffect "", "I"(i32 2047)
asm volatile ("" :: "I"(2047));
// CHECK: call void asm sideeffect "", "I"(i32 -2048)
asm volatile ("" :: "I"(-2048));
}
void test_J() {
Revert "[CodeGenModule] Assume dso_local for -fpic -fno-semantic-interposition" This reverts commit 789a46f2d742e11edaade28cb59a0f4d2a1d770e. Accidentally committed.
2020-02-04 02:09:39 +08:00
// CHECK-LABEL: define void @test_J()
[RISCV][NFC] Add missing test files for D54091 llvm-svn: 363056
2019-06-11 20:49:15 +08:00
// CHECK: call void asm sideeffect "", "J"(i32 0)
asm volatile ("" :: "J"(0));
}
void test_K() {
Revert "[CodeGenModule] Assume dso_local for -fpic -fno-semantic-interposition" This reverts commit 789a46f2d742e11edaade28cb59a0f4d2a1d770e. Accidentally committed.
2020-02-04 02:09:39 +08:00
// CHECK-LABEL: define void @test_K()
[RISCV][NFC] Add missing test files for D54091 llvm-svn: 363056
2019-06-11 20:49:15 +08:00
// CHECK: call void asm sideeffect "", "K"(i32 31)
asm volatile ("" :: "K"(31));
// CHECK: call void asm sideeffect "", "K"(i32 0)
asm volatile ("" :: "K"(0));
}
[RISCV] Support 'f' Inline Assembly Constraint Summary: This adds the 'f' inline assembly constraint, as supported by GCC. An 'f'-constrained operand is passed in a floating point register. Exactly which kind of floating-point register (32-bit or 64-bit) is decided based on the operand type and the available standard extensions (-f and -d, respectively). This patch adds support in both the clang frontend, and LLVM itself. Reviewers: asb, lewis-revill Reviewed By: asb Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D65500 llvm-svn: 367403
2019-07-31 17:45:55 +08:00
float f;
double d;
void test_f() {
Revert "[CodeGenModule] Assume dso_local for -fpic -fno-semantic-interposition" This reverts commit 789a46f2d742e11edaade28cb59a0f4d2a1d770e. Accidentally committed.
2020-02-04 02:09:39 +08:00
// CHECK-LABEL: define void @test_f()
[RISCV] Support 'f' Inline Assembly Constraint Summary: This adds the 'f' inline assembly constraint, as supported by GCC. An 'f'-constrained operand is passed in a floating point register. Exactly which kind of floating-point register (32-bit or 64-bit) is decided based on the operand type and the available standard extensions (-f and -d, respectively). This patch adds support in both the clang frontend, and LLVM itself. Reviewers: asb, lewis-revill Reviewed By: asb Subscribers: hiraditya, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D65500 llvm-svn: 367403
2019-07-31 17:45:55 +08:00
// CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load float, float* @f
// CHECK: call void asm sideeffect "", "f"(float [[FLT_ARG]])
asm volatile ("" :: "f"(f));
// CHECK: [[FLT_ARG:%[a-zA-Z_0-9]+]] = load double, double* @d
// CHECK: call void asm sideeffect "", "f"(double [[FLT_ARG]])
asm volatile ("" :: "f"(d));
}
[RISCV] Add inline asm constraint A for RISC-V This allows the constraint A to be used in inline asm for RISC-V, which allows an address held in a register to be used. This patch adds the minimal amount of code required to get operands with the right constraints to compile. Differential Revision: https://reviews.llvm.org/D54295 llvm-svn: 369093
2019-08-16 18:23:56 +08:00
void test_A(int *p) {
Revert "[CodeGenModule] Assume dso_local for -fpic -fno-semantic-interposition" This reverts commit 789a46f2d742e11edaade28cb59a0f4d2a1d770e. Accidentally committed.
2020-02-04 02:09:39 +08:00
// CHECK-LABEL: define void @test_A(i32* %p)
[RISCV] Add inline asm constraint A for RISC-V This allows the constraint A to be used in inline asm for RISC-V, which allows an address held in a register to be used. This patch adds the minimal amount of code required to get operands with the right constraints to compile. Differential Revision: https://reviews.llvm.org/D54295 llvm-svn: 369093
2019-08-16 18:23:56 +08:00
// CHECK: call void asm sideeffect "", "*A"(i32* %p)
asm volatile("" :: "A"(*p));
}