2017-07-29 08:56:56 +08:00
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//===- HexagonOptAddrMode.cpp ---------------------------------------------===//
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2016-04-29 23:49:13 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This implements a Hexagon-specific pass to optimize addressing mode for
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// load/store instructions.
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//===----------------------------------------------------------------------===//
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2016-12-16 09:00:40 +08:00
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#include "HexagonInstrInfo.h"
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#include "HexagonSubtarget.h"
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#include "MCTargetDesc/HexagonBaseInfo.h"
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2016-04-29 23:49:13 +08:00
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#include "RDFGraph.h"
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#include "RDFLiveness.h"
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2017-07-29 08:56:56 +08:00
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#include "RDFRegisters.h"
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#include "llvm/ADT/DenseMap.h"
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2016-04-29 23:49:13 +08:00
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#include "llvm/ADT/DenseSet.h"
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2016-12-16 09:00:40 +08:00
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#include "llvm/ADT/StringRef.h"
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2016-04-29 23:49:13 +08:00
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineDominanceFrontier.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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2016-12-16 09:00:40 +08:00
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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2016-04-29 23:49:13 +08:00
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2016-12-16 09:00:40 +08:00
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#include "llvm/CodeGen/MachineOperand.h"
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2018-03-24 03:30:34 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2017-11-17 09:07:10 +08:00
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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2016-12-16 09:00:40 +08:00
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Pass.h"
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2016-04-29 23:49:13 +08:00
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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2016-12-16 09:00:40 +08:00
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#include "llvm/Support/ErrorHandling.h"
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2016-04-29 23:49:13 +08:00
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#include "llvm/Support/raw_ostream.h"
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2016-12-16 09:00:40 +08:00
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#include <cassert>
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#include <cstdint>
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2016-04-29 23:49:13 +08:00
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2017-07-14 04:26:45 +08:00
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#define DEBUG_TYPE "opt-addr-mode"
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2017-07-29 08:56:56 +08:00
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using namespace llvm;
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using namespace rdf;
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2016-04-29 23:49:13 +08:00
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static cl::opt<int> CodeGrowthLimit("hexagon-amode-growth-limit",
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cl::Hidden, cl::init(0), cl::desc("Code growth limit for address mode "
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"optimization"));
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namespace llvm {
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2017-07-29 08:56:56 +08:00
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2016-04-29 23:49:13 +08:00
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FunctionPass *createHexagonOptAddrMode();
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2017-04-19 23:15:51 +08:00
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void initializeHexagonOptAddrModePass(PassRegistry&);
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2017-07-29 08:56:56 +08:00
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2016-12-16 09:00:40 +08:00
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} // end namespace llvm
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2016-04-29 23:49:13 +08:00
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namespace {
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2016-04-29 23:49:13 +08:00
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class HexagonOptAddrMode : public MachineFunctionPass {
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public:
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static char ID;
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2016-12-16 09:00:40 +08:00
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2017-07-29 08:56:56 +08:00
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HexagonOptAddrMode() : MachineFunctionPass(ID) {}
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2016-12-16 09:00:40 +08:00
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2016-10-01 10:56:57 +08:00
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StringRef getPassName() const override {
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2016-04-29 23:49:13 +08:00
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return "Optimize addressing mode of load/store";
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}
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2016-12-16 09:00:40 +08:00
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2016-04-29 23:49:13 +08:00
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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MachineFunctionPass::getAnalysisUsage(AU);
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AU.addRequired<MachineDominatorTree>();
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AU.addRequired<MachineDominanceFrontier>();
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AU.setPreservesAll();
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}
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2016-12-16 09:00:40 +08:00
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2016-04-29 23:49:13 +08:00
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bool runOnMachineFunction(MachineFunction &MF) override;
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private:
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2017-07-29 08:56:56 +08:00
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using MISetType = DenseSet<MachineInstr *>;
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using InstrEvalMap = DenseMap<MachineInstr *, bool>;
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2018-03-24 03:30:34 +08:00
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MachineRegisterInfo *MRI = nullptr;
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const HexagonInstrInfo *HII = nullptr;
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const HexagonRegisterInfo *HRI = nullptr;
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MachineDominatorTree *MDT = nullptr;
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DataFlowGraph *DFG = nullptr;
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DataFlowGraph::DefStackMap DefM;
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Liveness *LV = nullptr;
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2016-04-29 23:49:13 +08:00
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MISetType Deleted;
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bool processBlock(NodeAddr<BlockNode *> BA);
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bool xformUseMI(MachineInstr *TfrMI, MachineInstr *UseMI,
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NodeAddr<UseNode *> UseN, unsigned UseMOnum);
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2018-03-24 03:30:34 +08:00
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bool processAddUses(NodeAddr<StmtNode *> AddSN, MachineInstr *AddMI,
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const NodeList &UNodeList);
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bool updateAddUses(MachineInstr *AddMI, MachineInstr *UseMI);
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2016-04-29 23:49:13 +08:00
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bool analyzeUses(unsigned DefR, const NodeList &UNodeList,
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InstrEvalMap &InstrEvalResult, short &SizeInc);
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2016-07-30 05:49:42 +08:00
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bool hasRepForm(MachineInstr &MI, unsigned TfrDefR);
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bool canRemoveAddasl(NodeAddr<StmtNode *> AddAslSN, MachineInstr &MI,
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2016-04-29 23:49:13 +08:00
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const NodeList &UNodeList);
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2018-03-24 03:30:34 +08:00
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bool isSafeToExtLR(NodeAddr<StmtNode *> SN, MachineInstr *MI,
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unsigned LRExtReg, const NodeList &UNodeList);
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2016-04-29 23:49:13 +08:00
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void getAllRealUses(NodeAddr<StmtNode *> SN, NodeList &UNodeList);
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bool allValidCandidates(NodeAddr<StmtNode *> SA, NodeList &UNodeList);
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2016-07-30 05:49:42 +08:00
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short getBaseWithLongOffset(const MachineInstr &MI) const;
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2016-04-29 23:49:13 +08:00
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bool changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
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unsigned ImmOpNum);
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bool changeLoad(MachineInstr *OldMI, MachineOperand ImmOp, unsigned ImmOpNum);
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bool changeAddAsl(NodeAddr<UseNode *> AddAslUN, MachineInstr *AddAslMI,
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const MachineOperand &ImmOp, unsigned ImmOpNum);
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2018-03-24 03:30:34 +08:00
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bool isValidOffset(MachineInstr *MI, int Offset);
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2016-04-29 23:49:13 +08:00
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};
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2016-12-16 09:00:40 +08:00
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} // end anonymous namespace
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2016-04-29 23:49:13 +08:00
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char HexagonOptAddrMode::ID = 0;
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2017-04-19 23:15:51 +08:00
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INITIALIZE_PASS_BEGIN(HexagonOptAddrMode, "amode-opt",
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2016-04-29 23:49:13 +08:00
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"Optimize addressing mode", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree)
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INITIALIZE_PASS_DEPENDENCY(MachineDominanceFrontier)
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2017-04-19 23:15:51 +08:00
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INITIALIZE_PASS_END(HexagonOptAddrMode, "amode-opt", "Optimize addressing mode",
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2016-04-29 23:49:13 +08:00
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false, false)
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2016-07-30 05:49:42 +08:00
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bool HexagonOptAddrMode::hasRepForm(MachineInstr &MI, unsigned TfrDefR) {
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const MCInstrDesc &MID = MI.getDesc();
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2016-04-29 23:49:13 +08:00
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2016-07-30 05:49:42 +08:00
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if ((!MID.mayStore() && !MID.mayLoad()) || HII->isPredicated(MI))
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return false;
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if (MID.mayStore()) {
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2016-07-30 05:49:42 +08:00
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MachineOperand StOp = MI.getOperand(MI.getNumOperands() - 1);
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2016-04-29 23:49:13 +08:00
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if (StOp.isReg() && StOp.getReg() == TfrDefR)
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return false;
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}
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if (HII->getAddrMode(MI) == HexagonII::BaseRegOffset)
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// Tranform to Absolute plus register offset.
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2017-10-06 04:01:38 +08:00
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return (HII->changeAddrMode_rr_ur(MI) >= 0);
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2016-04-29 23:49:13 +08:00
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else if (HII->getAddrMode(MI) == HexagonII::BaseImmOffset)
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// Tranform to absolute addressing mode.
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2017-10-06 04:01:38 +08:00
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return (HII->changeAddrMode_io_abs(MI) >= 0);
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2016-04-29 23:49:13 +08:00
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return false;
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}
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// Check if addasl instruction can be removed. This is possible only
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// if it's feeding to only load/store instructions with base + register
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// offset as these instruction can be tranformed to use 'absolute plus
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// shifted register offset'.
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// ex:
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// Rs = ##foo
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// Rx = addasl(Rs, Rt, #2)
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// Rd = memw(Rx + #28)
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// Above three instructions can be replaced with Rd = memw(Rt<<#2 + ##foo+28)
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bool HexagonOptAddrMode::canRemoveAddasl(NodeAddr<StmtNode *> AddAslSN,
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2016-07-30 05:49:42 +08:00
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MachineInstr &MI,
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2016-04-29 23:49:13 +08:00
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const NodeList &UNodeList) {
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// check offset size in addasl. if 'offset > 3' return false
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2016-07-30 05:49:42 +08:00
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const MachineOperand &OffsetOp = MI.getOperand(3);
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2016-04-29 23:49:13 +08:00
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if (!OffsetOp.isImm() || OffsetOp.getImm() > 3)
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return false;
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2016-07-30 05:49:42 +08:00
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unsigned OffsetReg = MI.getOperand(2).getReg();
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2016-04-29 23:49:13 +08:00
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RegisterRef OffsetRR;
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NodeId OffsetRegRD = 0;
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for (NodeAddr<UseNode *> UA : AddAslSN.Addr->members_if(DFG->IsUse, *DFG)) {
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2016-10-15 01:57:55 +08:00
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RegisterRef RR = UA.Addr->getRegRef(*DFG);
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2016-04-29 23:49:13 +08:00
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if (OffsetReg == RR.Reg) {
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OffsetRR = RR;
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OffsetRegRD = UA.Addr->getReachingDef();
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}
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}
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for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
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NodeAddr<UseNode *> UA = *I;
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NodeAddr<InstrNode *> IA = UA.Addr->getOwner(*DFG);
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2017-04-19 23:14:30 +08:00
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if (UA.Addr->getFlags() & NodeAttrs::PhiRef)
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return false;
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NodeAddr<RefNode*> AA = LV->getNearestAliasedRef(OffsetRR, IA);
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if ((DFG->IsDef(AA) && AA.Id != OffsetRegRD) ||
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AA.Addr->getReachingDef() != OffsetRegRD)
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2016-04-29 23:49:13 +08:00
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return false;
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2016-07-30 05:49:42 +08:00
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MachineInstr &UseMI = *NodeAddr<StmtNode *>(IA).Addr->getCode();
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2016-04-29 23:49:13 +08:00
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NodeAddr<DefNode *> OffsetRegDN = DFG->addr<DefNode *>(OffsetRegRD);
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// Reaching Def to an offset register can't be a phi.
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if ((OffsetRegDN.Addr->getFlags() & NodeAttrs::PhiRef) &&
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2016-07-30 05:49:42 +08:00
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MI.getParent() != UseMI.getParent())
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2016-04-29 23:49:13 +08:00
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return false;
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2016-07-30 05:49:42 +08:00
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const MCInstrDesc &UseMID = UseMI.getDesc();
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2016-04-29 23:49:13 +08:00
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if ((!UseMID.mayLoad() && !UseMID.mayStore()) ||
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HII->getAddrMode(UseMI) != HexagonII::BaseImmOffset ||
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getBaseWithLongOffset(UseMI) < 0)
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return false;
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// Addasl output can't be a store value.
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2016-07-30 05:49:42 +08:00
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if (UseMID.mayStore() && UseMI.getOperand(2).isReg() &&
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UseMI.getOperand(2).getReg() == MI.getOperand(0).getReg())
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2016-04-29 23:49:13 +08:00
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return false;
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2016-07-30 05:49:42 +08:00
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for (auto &Mo : UseMI.operands())
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2016-04-29 23:49:13 +08:00
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if (Mo.isFI())
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return false;
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}
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return true;
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}
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bool HexagonOptAddrMode::allValidCandidates(NodeAddr<StmtNode *> SA,
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NodeList &UNodeList) {
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for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
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NodeAddr<UseNode *> UN = *I;
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2016-10-15 01:57:55 +08:00
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RegisterRef UR = UN.Addr->getRegRef(*DFG);
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2016-04-29 23:49:13 +08:00
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NodeSet Visited, Defs;
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2017-03-02 03:30:42 +08:00
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const auto &P = LV->getAllReachingDefsRec(UR, UN, Visited, Defs);
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if (!P.second) {
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2018-05-14 20:53:11 +08:00
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LLVM_DEBUG({
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2017-03-02 03:30:42 +08:00
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dbgs() << "*** Unable to collect all reaching defs for use ***\n"
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<< PrintNode<UseNode*>(UN, *DFG) << '\n'
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<< "The program's complexity may exceed the limits.\n";
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});
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return false;
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}
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const auto &ReachingDefs = P.first;
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2016-04-29 23:49:13 +08:00
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if (ReachingDefs.size() > 1) {
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2018-05-14 20:53:11 +08:00
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LLVM_DEBUG({
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2016-05-24 01:31:30 +08:00
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dbgs() << "*** Multiple Reaching Defs found!!! ***\n";
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for (auto DI : ReachingDefs) {
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NodeAddr<UseNode *> DA = DFG->addr<UseNode *>(DI);
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NodeAddr<StmtNode *> TempIA = DA.Addr->getOwner(*DFG);
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dbgs() << "\t\t[Reaching Def]: "
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<< Print<NodeAddr<InstrNode *>>(TempIA, *DFG) << "\n";
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}
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});
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2016-04-29 23:49:13 +08:00
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return false;
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}
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}
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return true;
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}
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void HexagonOptAddrMode::getAllRealUses(NodeAddr<StmtNode *> SA,
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NodeList &UNodeList) {
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for (NodeAddr<DefNode *> DA : SA.Addr->members_if(DFG->IsDef, *DFG)) {
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2018-05-14 20:53:11 +08:00
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LLVM_DEBUG(dbgs() << "\t\t[DefNode]: "
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<< Print<NodeAddr<DefNode *>>(DA, *DFG) << "\n");
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2017-02-17 02:45:23 +08:00
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RegisterRef DR = DFG->getPRI().normalize(DA.Addr->getRegRef(*DFG));
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2016-10-20 00:30:56 +08:00
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2016-04-29 23:49:13 +08:00
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auto UseSet = LV->getAllReachedUses(DR, DA);
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for (auto UI : UseSet) {
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NodeAddr<UseNode *> UA = DFG->addr<UseNode *>(UI);
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2018-05-14 20:53:11 +08:00
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LLVM_DEBUG({
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2016-05-24 01:31:30 +08:00
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NodeAddr<StmtNode *> TempIA = UA.Addr->getOwner(*DFG);
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dbgs() << "\t\t\t[Reached Use]: "
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<< Print<NodeAddr<InstrNode *>>(TempIA, *DFG) << "\n";
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});
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2016-04-29 23:49:13 +08:00
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if (UA.Addr->getFlags() & NodeAttrs::PhiRef) {
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NodeAddr<PhiNode *> PA = UA.Addr->getOwner(*DFG);
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NodeId id = PA.Id;
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const Liveness::RefMap &phiUse = LV->getRealUses(id);
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2018-05-14 20:53:11 +08:00
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|
LLVM_DEBUG(dbgs() << "\t\t\t\tphi real Uses"
|
|
|
|
<< Print<Liveness::RefMap>(phiUse, *DFG) << "\n");
|
2016-12-16 09:00:40 +08:00
|
|
|
if (!phiUse.empty()) {
|
2016-04-29 23:49:13 +08:00
|
|
|
for (auto I : phiUse) {
|
2017-04-15 01:25:13 +08:00
|
|
|
if (!DFG->getPRI().alias(RegisterRef(I.first), DR))
|
2016-04-29 23:49:13 +08:00
|
|
|
continue;
|
|
|
|
auto phiUseSet = I.second;
|
|
|
|
for (auto phiUI : phiUseSet) {
|
2016-10-20 00:30:56 +08:00
|
|
|
NodeAddr<UseNode *> phiUA = DFG->addr<UseNode *>(phiUI.first);
|
2016-04-29 23:49:13 +08:00
|
|
|
UNodeList.push_back(phiUA);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
UNodeList.push_back(UA);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-03-24 03:30:34 +08:00
|
|
|
bool HexagonOptAddrMode::isSafeToExtLR(NodeAddr<StmtNode *> SN,
|
|
|
|
MachineInstr *MI, unsigned LRExtReg,
|
|
|
|
const NodeList &UNodeList) {
|
|
|
|
RegisterRef LRExtRR;
|
|
|
|
NodeId LRExtRegRD = 0;
|
|
|
|
// Iterate through all the UseNodes in SN and find the reaching def
|
|
|
|
// for the LRExtReg.
|
|
|
|
for (NodeAddr<UseNode *> UA : SN.Addr->members_if(DFG->IsUse, *DFG)) {
|
|
|
|
RegisterRef RR = UA.Addr->getRegRef(*DFG);
|
|
|
|
if (LRExtReg == RR.Reg) {
|
|
|
|
LRExtRR = RR;
|
|
|
|
LRExtRegRD = UA.Addr->getReachingDef();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
|
|
|
|
NodeAddr<UseNode *> UA = *I;
|
|
|
|
NodeAddr<InstrNode *> IA = UA.Addr->getOwner(*DFG);
|
|
|
|
// The reaching def of LRExtRR at load/store node should be same as the
|
|
|
|
// one reaching at the SN.
|
|
|
|
if (UA.Addr->getFlags() & NodeAttrs::PhiRef)
|
|
|
|
return false;
|
|
|
|
NodeAddr<RefNode*> AA = LV->getNearestAliasedRef(LRExtRR, IA);
|
|
|
|
if ((DFG->IsDef(AA) && AA.Id != LRExtRegRD) ||
|
|
|
|
AA.Addr->getReachingDef() != LRExtRegRD) {
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(
|
|
|
|
dbgs() << "isSafeToExtLR: Returning false; another reaching def\n");
|
2018-03-24 03:30:34 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
MachineInstr *UseMI = NodeAddr<StmtNode *>(IA).Addr->getCode();
|
|
|
|
NodeAddr<DefNode *> LRExtRegDN = DFG->addr<DefNode *>(LRExtRegRD);
|
|
|
|
// Reaching Def to LRExtReg can't be a phi.
|
|
|
|
if ((LRExtRegDN.Addr->getFlags() & NodeAttrs::PhiRef) &&
|
|
|
|
MI->getParent() != UseMI->getParent())
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool HexagonOptAddrMode::isValidOffset(MachineInstr *MI, int Offset) {
|
|
|
|
unsigned AlignMask = 0;
|
|
|
|
switch (HII->getMemAccessSize(*MI)) {
|
|
|
|
case HexagonII::MemAccessSize::DoubleWordAccess:
|
|
|
|
AlignMask = 0x7;
|
|
|
|
break;
|
|
|
|
case HexagonII::MemAccessSize::WordAccess:
|
|
|
|
AlignMask = 0x3;
|
|
|
|
break;
|
|
|
|
case HexagonII::MemAccessSize::HalfWordAccess:
|
|
|
|
AlignMask = 0x1;
|
|
|
|
break;
|
|
|
|
case HexagonII::MemAccessSize::ByteAccess:
|
|
|
|
AlignMask = 0x0;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
if ((AlignMask & Offset) != 0)
|
|
|
|
return false;
|
|
|
|
return HII->isValidOffset(MI->getOpcode(), Offset, HRI, false);
|
|
|
|
}
|
|
|
|
|
|
|
|
bool HexagonOptAddrMode::processAddUses(NodeAddr<StmtNode *> AddSN,
|
|
|
|
MachineInstr *AddMI,
|
|
|
|
const NodeList &UNodeList) {
|
|
|
|
|
|
|
|
unsigned AddDefR = AddMI->getOperand(0).getReg();
|
|
|
|
for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
|
|
|
|
NodeAddr<UseNode *> UN = *I;
|
|
|
|
NodeAddr<StmtNode *> SN = UN.Addr->getOwner(*DFG);
|
|
|
|
MachineInstr *MI = SN.Addr->getCode();
|
|
|
|
const MCInstrDesc &MID = MI->getDesc();
|
|
|
|
if ((!MID.mayLoad() && !MID.mayStore()) ||
|
|
|
|
HII->getAddrMode(*MI) != HexagonII::BaseImmOffset ||
|
|
|
|
HII->isHVXVec(*MI))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
MachineOperand BaseOp = MID.mayLoad() ? MI->getOperand(1)
|
|
|
|
: MI->getOperand(0);
|
|
|
|
|
|
|
|
if (!BaseOp.isReg() || BaseOp.getReg() != AddDefR)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
MachineOperand OffsetOp = MID.mayLoad() ? MI->getOperand(2)
|
|
|
|
: MI->getOperand(1);
|
|
|
|
if (!OffsetOp.isImm())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
int64_t newOffset = OffsetOp.getImm() + AddMI->getOperand(2).getImm();
|
|
|
|
if (!isValidOffset(MI, newOffset))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Since we'll be extending the live range of Rt in the following example,
|
|
|
|
// make sure that is safe. another definition of Rt doesn't exist between 'add'
|
|
|
|
// and load/store instruction.
|
|
|
|
//
|
|
|
|
// Ex: Rx= add(Rt,#10)
|
|
|
|
// memw(Rx+#0) = Rs
|
|
|
|
// will be replaced with => memw(Rt+#10) = Rs
|
|
|
|
unsigned BaseReg = AddMI->getOperand(1).getReg();
|
|
|
|
if (!isSafeToExtLR(AddSN, AddMI, BaseReg, UNodeList))
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Update all the uses of 'add' with the appropriate base and offset
|
|
|
|
// values.
|
|
|
|
bool Changed = false;
|
|
|
|
for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
|
|
|
|
NodeAddr<UseNode *> UseN = *I;
|
|
|
|
assert(!(UseN.Addr->getFlags() & NodeAttrs::PhiRef) &&
|
|
|
|
"Found a PhiRef node as a real reached use!!");
|
|
|
|
|
|
|
|
NodeAddr<StmtNode *> OwnerN = UseN.Addr->getOwner(*DFG);
|
|
|
|
MachineInstr *UseMI = OwnerN.Addr->getCode();
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "\t\t[MI <BB#" << UseMI->getParent()->getNumber()
|
|
|
|
<< ">]: " << *UseMI << "\n");
|
2018-03-24 03:30:34 +08:00
|
|
|
Changed |= updateAddUses(AddMI, UseMI);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (Changed)
|
|
|
|
Deleted.insert(AddMI);
|
|
|
|
|
|
|
|
return Changed;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool HexagonOptAddrMode::updateAddUses(MachineInstr *AddMI,
|
|
|
|
MachineInstr *UseMI) {
|
|
|
|
const MachineOperand ImmOp = AddMI->getOperand(2);
|
|
|
|
const MachineOperand AddRegOp = AddMI->getOperand(1);
|
|
|
|
unsigned newReg = AddRegOp.getReg();
|
|
|
|
const MCInstrDesc &MID = UseMI->getDesc();
|
|
|
|
|
|
|
|
MachineOperand &BaseOp = MID.mayLoad() ? UseMI->getOperand(1)
|
|
|
|
: UseMI->getOperand(0);
|
|
|
|
MachineOperand &OffsetOp = MID.mayLoad() ? UseMI->getOperand(2)
|
|
|
|
: UseMI->getOperand(1);
|
|
|
|
BaseOp.setReg(newReg);
|
|
|
|
BaseOp.setIsUndef(AddRegOp.isUndef());
|
|
|
|
BaseOp.setImplicit(AddRegOp.isImplicit());
|
|
|
|
OffsetOp.setImm(ImmOp.getImm() + OffsetOp.getImm());
|
|
|
|
MRI->clearKillFlags(newReg);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2016-04-29 23:49:13 +08:00
|
|
|
bool HexagonOptAddrMode::analyzeUses(unsigned tfrDefR,
|
|
|
|
const NodeList &UNodeList,
|
|
|
|
InstrEvalMap &InstrEvalResult,
|
|
|
|
short &SizeInc) {
|
|
|
|
bool KeepTfr = false;
|
|
|
|
bool HasRepInstr = false;
|
|
|
|
InstrEvalResult.clear();
|
|
|
|
|
|
|
|
for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
|
|
|
|
bool CanBeReplaced = false;
|
|
|
|
NodeAddr<UseNode *> UN = *I;
|
|
|
|
NodeAddr<StmtNode *> SN = UN.Addr->getOwner(*DFG);
|
2016-07-30 05:49:42 +08:00
|
|
|
MachineInstr &MI = *SN.Addr->getCode();
|
|
|
|
const MCInstrDesc &MID = MI.getDesc();
|
2016-04-29 23:49:13 +08:00
|
|
|
if ((MID.mayLoad() || MID.mayStore())) {
|
|
|
|
if (!hasRepForm(MI, tfrDefR)) {
|
|
|
|
KeepTfr = true;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
SizeInc++;
|
|
|
|
CanBeReplaced = true;
|
2016-07-30 05:49:42 +08:00
|
|
|
} else if (MI.getOpcode() == Hexagon::S2_addasl_rrri) {
|
2016-04-29 23:49:13 +08:00
|
|
|
NodeList AddaslUseList;
|
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "\nGetting ReachedUses for === " << MI << "\n");
|
2016-04-29 23:49:13 +08:00
|
|
|
getAllRealUses(SN, AddaslUseList);
|
|
|
|
// Process phi nodes.
|
|
|
|
if (allValidCandidates(SN, AddaslUseList) &&
|
|
|
|
canRemoveAddasl(SN, MI, AddaslUseList)) {
|
|
|
|
SizeInc += AddaslUseList.size();
|
|
|
|
SizeInc -= 1; // Reduce size by 1 as addasl itself can be removed.
|
|
|
|
CanBeReplaced = true;
|
|
|
|
} else
|
|
|
|
SizeInc++;
|
|
|
|
} else
|
|
|
|
// Currently, only load/store and addasl are handled.
|
|
|
|
// Some other instructions to consider -
|
|
|
|
// A2_add -> A2_addi
|
|
|
|
// M4_mpyrr_addr -> M4_mpyrr_addi
|
|
|
|
KeepTfr = true;
|
|
|
|
|
2016-07-30 05:49:42 +08:00
|
|
|
InstrEvalResult[&MI] = CanBeReplaced;
|
2016-04-29 23:49:13 +08:00
|
|
|
HasRepInstr |= CanBeReplaced;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Reduce total size by 2 if original tfr can be deleted.
|
|
|
|
if (!KeepTfr)
|
|
|
|
SizeInc -= 2;
|
|
|
|
|
|
|
|
return HasRepInstr;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool HexagonOptAddrMode::changeLoad(MachineInstr *OldMI, MachineOperand ImmOp,
|
|
|
|
unsigned ImmOpNum) {
|
|
|
|
bool Changed = false;
|
|
|
|
MachineBasicBlock *BB = OldMI->getParent();
|
|
|
|
auto UsePos = MachineBasicBlock::iterator(OldMI);
|
|
|
|
MachineBasicBlock::instr_iterator InsertPt = UsePos.getInstrIterator();
|
|
|
|
++InsertPt;
|
|
|
|
unsigned OpStart;
|
|
|
|
unsigned OpEnd = OldMI->getNumOperands();
|
|
|
|
MachineInstrBuilder MIB;
|
|
|
|
|
|
|
|
if (ImmOpNum == 1) {
|
2016-07-30 05:49:42 +08:00
|
|
|
if (HII->getAddrMode(*OldMI) == HexagonII::BaseRegOffset) {
|
2017-10-06 04:01:38 +08:00
|
|
|
short NewOpCode = HII->changeAddrMode_rr_ur(*OldMI);
|
2016-04-29 23:49:13 +08:00
|
|
|
assert(NewOpCode >= 0 && "Invalid New opcode\n");
|
|
|
|
MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
|
2017-01-13 17:58:52 +08:00
|
|
|
MIB.add(OldMI->getOperand(0));
|
|
|
|
MIB.add(OldMI->getOperand(2));
|
|
|
|
MIB.add(OldMI->getOperand(3));
|
|
|
|
MIB.add(ImmOp);
|
2016-04-29 23:49:13 +08:00
|
|
|
OpStart = 4;
|
|
|
|
Changed = true;
|
2018-12-11 05:56:04 +08:00
|
|
|
} else if (HII->getAddrMode(*OldMI) == HexagonII::BaseImmOffset &&
|
|
|
|
OldMI->getOperand(2).isImm()) {
|
2017-10-06 04:01:38 +08:00
|
|
|
short NewOpCode = HII->changeAddrMode_io_abs(*OldMI);
|
2016-04-29 23:49:13 +08:00
|
|
|
assert(NewOpCode >= 0 && "Invalid New opcode\n");
|
|
|
|
MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode))
|
2017-01-13 17:58:52 +08:00
|
|
|
.add(OldMI->getOperand(0));
|
2016-04-29 23:49:13 +08:00
|
|
|
const GlobalValue *GV = ImmOp.getGlobal();
|
|
|
|
int64_t Offset = ImmOp.getOffset() + OldMI->getOperand(2).getImm();
|
|
|
|
|
|
|
|
MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags());
|
|
|
|
OpStart = 3;
|
|
|
|
Changed = true;
|
|
|
|
} else
|
|
|
|
Changed = false;
|
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
|
|
|
|
LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
|
2018-12-11 05:56:04 +08:00
|
|
|
} else if (ImmOpNum == 2) {
|
|
|
|
if (OldMI->getOperand(3).isImm() && OldMI->getOperand(3).getImm() == 0) {
|
|
|
|
short NewOpCode = HII->changeAddrMode_rr_io(*OldMI);
|
|
|
|
assert(NewOpCode >= 0 && "Invalid New opcode\n");
|
|
|
|
MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
|
|
|
|
MIB.add(OldMI->getOperand(0));
|
|
|
|
MIB.add(OldMI->getOperand(1));
|
|
|
|
MIB.add(ImmOp);
|
|
|
|
OpStart = 4;
|
|
|
|
Changed = true;
|
|
|
|
LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
|
|
|
|
LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
|
|
|
|
}
|
2016-04-29 23:49:13 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
if (Changed)
|
|
|
|
for (unsigned i = OpStart; i < OpEnd; ++i)
|
2017-01-13 17:58:52 +08:00
|
|
|
MIB.add(OldMI->getOperand(i));
|
2016-04-29 23:49:13 +08:00
|
|
|
|
|
|
|
return Changed;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool HexagonOptAddrMode::changeStore(MachineInstr *OldMI, MachineOperand ImmOp,
|
|
|
|
unsigned ImmOpNum) {
|
|
|
|
bool Changed = false;
|
|
|
|
unsigned OpStart;
|
|
|
|
unsigned OpEnd = OldMI->getNumOperands();
|
|
|
|
MachineBasicBlock *BB = OldMI->getParent();
|
|
|
|
auto UsePos = MachineBasicBlock::iterator(OldMI);
|
|
|
|
MachineBasicBlock::instr_iterator InsertPt = UsePos.getInstrIterator();
|
|
|
|
++InsertPt;
|
|
|
|
MachineInstrBuilder MIB;
|
|
|
|
if (ImmOpNum == 0) {
|
2016-07-30 05:49:42 +08:00
|
|
|
if (HII->getAddrMode(*OldMI) == HexagonII::BaseRegOffset) {
|
2017-10-06 04:01:38 +08:00
|
|
|
short NewOpCode = HII->changeAddrMode_rr_ur(*OldMI);
|
2016-04-29 23:49:13 +08:00
|
|
|
assert(NewOpCode >= 0 && "Invalid New opcode\n");
|
|
|
|
MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
|
2017-01-13 17:58:52 +08:00
|
|
|
MIB.add(OldMI->getOperand(1));
|
|
|
|
MIB.add(OldMI->getOperand(2));
|
|
|
|
MIB.add(ImmOp);
|
|
|
|
MIB.add(OldMI->getOperand(3));
|
2016-04-29 23:49:13 +08:00
|
|
|
OpStart = 4;
|
2016-07-30 05:49:42 +08:00
|
|
|
} else if (HII->getAddrMode(*OldMI) == HexagonII::BaseImmOffset) {
|
2017-10-06 04:01:38 +08:00
|
|
|
short NewOpCode = HII->changeAddrMode_io_abs(*OldMI);
|
2016-04-29 23:49:13 +08:00
|
|
|
assert(NewOpCode >= 0 && "Invalid New opcode\n");
|
|
|
|
MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
|
|
|
|
const GlobalValue *GV = ImmOp.getGlobal();
|
|
|
|
int64_t Offset = ImmOp.getOffset() + OldMI->getOperand(1).getImm();
|
|
|
|
MIB.addGlobalAddress(GV, Offset, ImmOp.getTargetFlags());
|
2017-01-13 17:58:52 +08:00
|
|
|
MIB.add(OldMI->getOperand(2));
|
2016-04-29 23:49:13 +08:00
|
|
|
OpStart = 3;
|
|
|
|
}
|
|
|
|
Changed = true;
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
|
|
|
|
LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
|
2016-04-29 23:49:13 +08:00
|
|
|
} else if (ImmOpNum == 1 && OldMI->getOperand(2).getImm() == 0) {
|
2017-10-06 04:01:38 +08:00
|
|
|
short NewOpCode = HII->changeAddrMode_rr_io(*OldMI);
|
2016-04-29 23:49:13 +08:00
|
|
|
assert(NewOpCode >= 0 && "Invalid New opcode\n");
|
|
|
|
MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
|
2017-01-13 17:58:52 +08:00
|
|
|
MIB.add(OldMI->getOperand(0));
|
|
|
|
MIB.add(ImmOp);
|
2017-10-20 00:59:22 +08:00
|
|
|
OpStart = 3;
|
2016-04-29 23:49:13 +08:00
|
|
|
Changed = true;
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "[Changing]: " << *OldMI << "\n");
|
|
|
|
LLVM_DEBUG(dbgs() << "[TO]: " << *MIB << "\n");
|
2016-04-29 23:49:13 +08:00
|
|
|
}
|
|
|
|
if (Changed)
|
|
|
|
for (unsigned i = OpStart; i < OpEnd; ++i)
|
2017-01-13 17:58:52 +08:00
|
|
|
MIB.add(OldMI->getOperand(i));
|
2016-04-29 23:49:13 +08:00
|
|
|
|
|
|
|
return Changed;
|
|
|
|
}
|
|
|
|
|
2016-07-30 05:49:42 +08:00
|
|
|
short HexagonOptAddrMode::getBaseWithLongOffset(const MachineInstr &MI) const {
|
2016-04-29 23:49:13 +08:00
|
|
|
if (HII->getAddrMode(MI) == HexagonII::BaseImmOffset) {
|
2017-10-06 04:01:38 +08:00
|
|
|
short TempOpCode = HII->changeAddrMode_io_rr(MI);
|
|
|
|
return HII->changeAddrMode_rr_ur(TempOpCode);
|
|
|
|
}
|
|
|
|
return HII->changeAddrMode_rr_ur(MI);
|
2016-04-29 23:49:13 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
bool HexagonOptAddrMode::changeAddAsl(NodeAddr<UseNode *> AddAslUN,
|
|
|
|
MachineInstr *AddAslMI,
|
|
|
|
const MachineOperand &ImmOp,
|
|
|
|
unsigned ImmOpNum) {
|
|
|
|
NodeAddr<StmtNode *> SA = AddAslUN.Addr->getOwner(*DFG);
|
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "Processing addasl :" << *AddAslMI << "\n");
|
2016-04-29 23:49:13 +08:00
|
|
|
|
|
|
|
NodeList UNodeList;
|
|
|
|
getAllRealUses(SA, UNodeList);
|
|
|
|
|
|
|
|
for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
|
|
|
|
NodeAddr<UseNode *> UseUN = *I;
|
|
|
|
assert(!(UseUN.Addr->getFlags() & NodeAttrs::PhiRef) &&
|
|
|
|
"Can't transform this 'AddAsl' instruction!");
|
|
|
|
|
|
|
|
NodeAddr<StmtNode *> UseIA = UseUN.Addr->getOwner(*DFG);
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "[InstrNode]: "
|
|
|
|
<< Print<NodeAddr<InstrNode *>>(UseIA, *DFG) << "\n");
|
2016-04-29 23:49:13 +08:00
|
|
|
MachineInstr *UseMI = UseIA.Addr->getCode();
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "[MI <" << printMBBReference(*UseMI->getParent())
|
|
|
|
<< ">]: " << *UseMI << "\n");
|
2016-04-29 23:49:13 +08:00
|
|
|
const MCInstrDesc &UseMID = UseMI->getDesc();
|
2016-07-30 05:49:42 +08:00
|
|
|
assert(HII->getAddrMode(*UseMI) == HexagonII::BaseImmOffset);
|
2016-04-29 23:49:13 +08:00
|
|
|
|
|
|
|
auto UsePos = MachineBasicBlock::iterator(UseMI);
|
|
|
|
MachineBasicBlock::instr_iterator InsertPt = UsePos.getInstrIterator();
|
2016-07-30 05:49:42 +08:00
|
|
|
short NewOpCode = getBaseWithLongOffset(*UseMI);
|
2016-04-29 23:49:13 +08:00
|
|
|
assert(NewOpCode >= 0 && "Invalid New opcode\n");
|
|
|
|
|
|
|
|
unsigned OpStart;
|
|
|
|
unsigned OpEnd = UseMI->getNumOperands();
|
|
|
|
|
|
|
|
MachineBasicBlock *BB = UseMI->getParent();
|
|
|
|
MachineInstrBuilder MIB =
|
|
|
|
BuildMI(*BB, InsertPt, UseMI->getDebugLoc(), HII->get(NewOpCode));
|
|
|
|
// change mem(Rs + # ) -> mem(Rt << # + ##)
|
|
|
|
if (UseMID.mayLoad()) {
|
2017-01-13 17:58:52 +08:00
|
|
|
MIB.add(UseMI->getOperand(0));
|
|
|
|
MIB.add(AddAslMI->getOperand(2));
|
|
|
|
MIB.add(AddAslMI->getOperand(3));
|
2016-04-29 23:49:13 +08:00
|
|
|
const GlobalValue *GV = ImmOp.getGlobal();
|
2017-04-19 23:15:51 +08:00
|
|
|
MIB.addGlobalAddress(GV, UseMI->getOperand(2).getImm()+ImmOp.getOffset(),
|
2016-04-29 23:49:13 +08:00
|
|
|
ImmOp.getTargetFlags());
|
|
|
|
OpStart = 3;
|
|
|
|
} else if (UseMID.mayStore()) {
|
2017-01-13 17:58:52 +08:00
|
|
|
MIB.add(AddAslMI->getOperand(2));
|
|
|
|
MIB.add(AddAslMI->getOperand(3));
|
2016-04-29 23:49:13 +08:00
|
|
|
const GlobalValue *GV = ImmOp.getGlobal();
|
2017-04-19 23:15:51 +08:00
|
|
|
MIB.addGlobalAddress(GV, UseMI->getOperand(1).getImm()+ImmOp.getOffset(),
|
2016-04-29 23:49:13 +08:00
|
|
|
ImmOp.getTargetFlags());
|
2017-01-13 17:58:52 +08:00
|
|
|
MIB.add(UseMI->getOperand(2));
|
2016-04-29 23:49:13 +08:00
|
|
|
OpStart = 3;
|
|
|
|
} else
|
|
|
|
llvm_unreachable("Unhandled instruction");
|
|
|
|
|
|
|
|
for (unsigned i = OpStart; i < OpEnd; ++i)
|
2017-01-13 17:58:52 +08:00
|
|
|
MIB.add(UseMI->getOperand(i));
|
2016-04-29 23:49:13 +08:00
|
|
|
|
|
|
|
Deleted.insert(UseMI);
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool HexagonOptAddrMode::xformUseMI(MachineInstr *TfrMI, MachineInstr *UseMI,
|
|
|
|
NodeAddr<UseNode *> UseN,
|
|
|
|
unsigned UseMOnum) {
|
|
|
|
const MachineOperand ImmOp = TfrMI->getOperand(1);
|
|
|
|
const MCInstrDesc &MID = UseMI->getDesc();
|
|
|
|
unsigned Changed = false;
|
|
|
|
if (MID.mayLoad())
|
|
|
|
Changed = changeLoad(UseMI, ImmOp, UseMOnum);
|
|
|
|
else if (MID.mayStore())
|
|
|
|
Changed = changeStore(UseMI, ImmOp, UseMOnum);
|
|
|
|
else if (UseMI->getOpcode() == Hexagon::S2_addasl_rrri)
|
|
|
|
Changed = changeAddAsl(UseN, UseMI, ImmOp, UseMOnum);
|
|
|
|
|
|
|
|
if (Changed)
|
|
|
|
Deleted.insert(UseMI);
|
|
|
|
|
|
|
|
return Changed;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) {
|
|
|
|
bool Changed = false;
|
|
|
|
|
|
|
|
for (auto IA : BA.Addr->members(*DFG)) {
|
|
|
|
if (!DFG->IsCode<NodeAttrs::Stmt>(IA))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
NodeAddr<StmtNode *> SA = IA;
|
|
|
|
MachineInstr *MI = SA.Addr->getCode();
|
2018-03-24 03:30:34 +08:00
|
|
|
if ((MI->getOpcode() != Hexagon::A2_tfrsi ||
|
|
|
|
!MI->getOperand(1).isGlobal()) &&
|
|
|
|
(MI->getOpcode() != Hexagon::A2_addi ||
|
|
|
|
!MI->getOperand(2).isImm() || HII->isConstExtended(*MI)))
|
|
|
|
continue;
|
2016-04-29 23:49:13 +08:00
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "[Analyzing " << HII->getName(MI->getOpcode())
|
|
|
|
<< "]: " << *MI << "\n\t[InstrNode]: "
|
|
|
|
<< Print<NodeAddr<InstrNode *>>(IA, *DFG) << '\n');
|
2016-04-29 23:49:13 +08:00
|
|
|
|
|
|
|
NodeList UNodeList;
|
|
|
|
getAllRealUses(SA, UNodeList);
|
|
|
|
|
|
|
|
if (!allValidCandidates(SA, UNodeList))
|
|
|
|
continue;
|
|
|
|
|
2018-03-24 03:30:34 +08:00
|
|
|
// Analyze all uses of 'add'. If the output of 'add' is used as an address
|
|
|
|
// in the base+immediate addressing mode load/store instructions, see if
|
|
|
|
// they can be updated to use the immediate value as an offet. Thus,
|
|
|
|
// providing us the opportunity to eliminate 'add'.
|
|
|
|
// Ex: Rx= add(Rt,#12)
|
|
|
|
// memw(Rx+#0) = Rs
|
|
|
|
// This can be replaced with memw(Rt+#12) = Rs
|
|
|
|
//
|
|
|
|
// This transformation is only performed if all uses can be updated and
|
|
|
|
// the offset isn't required to be constant extended.
|
|
|
|
if (MI->getOpcode() == Hexagon::A2_addi) {
|
|
|
|
Changed |= processAddUses(SA, MI, UNodeList);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
2016-04-29 23:49:13 +08:00
|
|
|
short SizeInc = 0;
|
|
|
|
unsigned DefR = MI->getOperand(0).getReg();
|
|
|
|
InstrEvalMap InstrEvalResult;
|
|
|
|
|
|
|
|
// Analyze all uses and calculate increase in size. Perform the optimization
|
|
|
|
// only if there is no increase in size.
|
|
|
|
if (!analyzeUses(DefR, UNodeList, InstrEvalResult, SizeInc))
|
|
|
|
continue;
|
|
|
|
if (SizeInc > CodeGrowthLimit)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
bool KeepTfr = false;
|
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "\t[Total reached uses] : " << UNodeList.size()
|
|
|
|
<< "\n");
|
|
|
|
LLVM_DEBUG(dbgs() << "\t[Processing Reached Uses] ===\n");
|
2016-04-29 23:49:13 +08:00
|
|
|
for (auto I = UNodeList.rbegin(), E = UNodeList.rend(); I != E; ++I) {
|
|
|
|
NodeAddr<UseNode *> UseN = *I;
|
|
|
|
assert(!(UseN.Addr->getFlags() & NodeAttrs::PhiRef) &&
|
|
|
|
"Found a PhiRef node as a real reached use!!");
|
|
|
|
|
|
|
|
NodeAddr<StmtNode *> OwnerN = UseN.Addr->getOwner(*DFG);
|
|
|
|
MachineInstr *UseMI = OwnerN.Addr->getCode();
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "\t\t[MI <" << printMBBReference(*UseMI->getParent())
|
|
|
|
<< ">]: " << *UseMI << "\n");
|
2016-04-29 23:49:13 +08:00
|
|
|
|
|
|
|
int UseMOnum = -1;
|
|
|
|
unsigned NumOperands = UseMI->getNumOperands();
|
|
|
|
for (unsigned j = 0; j < NumOperands - 1; ++j) {
|
|
|
|
const MachineOperand &op = UseMI->getOperand(j);
|
|
|
|
if (op.isReg() && op.isUse() && DefR == op.getReg())
|
|
|
|
UseMOnum = j;
|
|
|
|
}
|
2018-03-24 03:30:34 +08:00
|
|
|
// It is possible that the register will not be found in any operand.
|
|
|
|
// This could happen, for example, when DefR = R4, but the used
|
|
|
|
// register is D2.
|
2016-04-29 23:49:13 +08:00
|
|
|
|
2018-12-11 05:56:04 +08:00
|
|
|
// Change UseMI if replacement is possible. If any replacement failed,
|
|
|
|
// or wasn't attempted, make sure to keep the TFR.
|
|
|
|
bool Xformed = false;
|
2018-03-24 03:30:34 +08:00
|
|
|
if (UseMOnum >= 0 && InstrEvalResult[UseMI])
|
2018-12-11 05:56:04 +08:00
|
|
|
Xformed = xformUseMI(MI, UseMI, UseN, UseMOnum);
|
|
|
|
Changed |= Xformed;
|
|
|
|
KeepTfr |= !Xformed;
|
2016-04-29 23:49:13 +08:00
|
|
|
}
|
|
|
|
if (!KeepTfr)
|
|
|
|
Deleted.insert(MI);
|
|
|
|
}
|
|
|
|
return Changed;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool HexagonOptAddrMode::runOnMachineFunction(MachineFunction &MF) {
|
2017-12-16 06:22:58 +08:00
|
|
|
if (skipFunction(MF.getFunction()))
|
2017-04-14 23:26:34 +08:00
|
|
|
return false;
|
|
|
|
|
2016-04-29 23:49:13 +08:00
|
|
|
bool Changed = false;
|
|
|
|
auto &HST = MF.getSubtarget<HexagonSubtarget>();
|
2018-03-24 03:30:34 +08:00
|
|
|
MRI = &MF.getRegInfo();
|
2016-04-29 23:49:13 +08:00
|
|
|
HII = HST.getInstrInfo();
|
2018-03-24 03:30:34 +08:00
|
|
|
HRI = HST.getRegisterInfo();
|
2016-04-29 23:49:13 +08:00
|
|
|
const auto &MDF = getAnalysis<MachineDominanceFrontier>();
|
|
|
|
MDT = &getAnalysis<MachineDominatorTree>();
|
|
|
|
const TargetOperandInfo TOI(*HII);
|
|
|
|
|
2018-03-24 03:30:34 +08:00
|
|
|
DataFlowGraph G(MF, *HII, *HRI, *MDT, MDF, TOI);
|
2017-06-29 23:55:59 +08:00
|
|
|
// Need to keep dead phis because we can propagate uses of registers into
|
|
|
|
// nodes dominated by those would-be phis.
|
|
|
|
G.build(BuildOptions::KeepDeadPhis);
|
2016-04-29 23:49:13 +08:00
|
|
|
DFG = &G;
|
|
|
|
|
2018-03-24 03:30:34 +08:00
|
|
|
Liveness L(*MRI, *DFG);
|
2016-04-29 23:49:13 +08:00
|
|
|
L.computePhiInfo();
|
|
|
|
LV = &L;
|
|
|
|
|
|
|
|
Deleted.clear();
|
|
|
|
NodeAddr<FuncNode *> FA = DFG->getFunc();
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "==== [RefMap#]=====:\n "
|
|
|
|
<< Print<NodeAddr<FuncNode *>>(FA, *DFG) << "\n");
|
2016-04-29 23:49:13 +08:00
|
|
|
|
|
|
|
for (NodeAddr<BlockNode *> BA : FA.Addr->members(*DFG))
|
|
|
|
Changed |= processBlock(BA);
|
|
|
|
|
|
|
|
for (auto MI : Deleted)
|
|
|
|
MI->eraseFromParent();
|
|
|
|
|
|
|
|
if (Changed) {
|
|
|
|
G.build();
|
|
|
|
L.computeLiveIns();
|
|
|
|
L.resetLiveIns();
|
|
|
|
L.resetKills();
|
|
|
|
}
|
|
|
|
|
|
|
|
return Changed;
|
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Public Constructor Functions
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
FunctionPass *llvm::createHexagonOptAddrMode() {
|
|
|
|
return new HexagonOptAddrMode();
|
|
|
|
}
|