2018-02-24 07:49:32 +08:00
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//===-------------- BPFMIPeephole.cpp - MI Peephole Cleanups -------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass performs peephole optimizations to cleanup ugly code sequences at
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// MachineInstruction layer.
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//
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2018-03-13 14:47:06 +08:00
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// Currently, there are two optimizations implemented:
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// - One pre-RA MachineSSA pass to eliminate type promotion sequences, those
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// zero extend 32-bit subregisters to 64-bit registers, if the compiler
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// could prove the subregisters is defined by 32-bit operations in which
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// case the upper half of the underlying 64-bit registers were zeroed
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// implicitly.
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2018-02-24 07:49:32 +08:00
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//
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2018-03-13 14:47:06 +08:00
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// - One post-RA PreEmit pass to do final cleanup on some redundant
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// instructions generated due to bad RA on subregister.
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2018-02-24 07:49:32 +08:00
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//===----------------------------------------------------------------------===//
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#include "BPF.h"
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#include "BPFInstrInfo.h"
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#include "BPFTargetMachine.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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2018-03-13 14:47:03 +08:00
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#define DEBUG_TYPE "bpf-mi-zext-elim"
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2018-02-24 07:49:32 +08:00
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2018-03-13 14:47:03 +08:00
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STATISTIC(ZExtElemNum, "Number of zero extension shifts eliminated");
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2018-02-24 07:49:32 +08:00
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namespace {
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struct BPFMIPeephole : public MachineFunctionPass {
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static char ID;
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const BPFInstrInfo *TII;
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MachineFunction *MF;
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MachineRegisterInfo *MRI;
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BPFMIPeephole() : MachineFunctionPass(ID) {
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initializeBPFMIPeepholePass(*PassRegistry::getPassRegistry());
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}
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private:
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// Initialize class variables.
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void initialize(MachineFunction &MFParm);
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2018-03-13 14:47:03 +08:00
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bool isMovFrom32Def(MachineInstr *MovMI);
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bool eliminateZExtSeq(void);
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2018-02-24 07:49:32 +08:00
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public:
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// Main entry point for this pass.
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bool runOnMachineFunction(MachineFunction &MF) override {
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if (skipFunction(MF.getFunction()))
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return false;
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initialize(MF);
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2018-03-13 14:47:03 +08:00
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return eliminateZExtSeq();
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2018-02-24 07:49:32 +08:00
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}
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};
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// Initialize class variables.
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void BPFMIPeephole::initialize(MachineFunction &MFParm) {
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MF = &MFParm;
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MRI = &MF->getRegInfo();
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TII = MF->getSubtarget<BPFSubtarget>().getInstrInfo();
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2018-05-14 20:53:11 +08:00
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LLVM_DEBUG(dbgs() << "*** BPF MachineSSA peephole pass ***\n\n");
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2018-02-24 07:49:32 +08:00
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}
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2018-03-13 14:47:03 +08:00
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bool BPFMIPeephole::isMovFrom32Def(MachineInstr *MovMI)
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{
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MachineInstr *DefInsn = MRI->getVRegDef(MovMI->getOperand(1).getReg());
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2018-02-24 07:49:32 +08:00
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2018-05-14 20:53:11 +08:00
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LLVM_DEBUG(dbgs() << " Def of Mov Src:");
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LLVM_DEBUG(DefInsn->dump());
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2018-03-13 14:47:07 +08:00
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2018-03-13 14:47:04 +08:00
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if (!DefInsn)
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2018-03-13 14:47:03 +08:00
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return false;
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2018-02-24 07:49:32 +08:00
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2018-03-13 14:47:04 +08:00
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if (DefInsn->isPHI()) {
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for (unsigned i = 1, e = DefInsn->getNumOperands(); i < e; i += 2) {
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MachineOperand &opnd = DefInsn->getOperand(i);
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if (!opnd.isReg())
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return false;
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MachineInstr *PhiDef = MRI->getVRegDef(opnd.getReg());
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// quick check on PHI incoming definitions.
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if (!PhiDef || PhiDef->isPHI() || PhiDef->getOpcode() == BPF::COPY)
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return false;
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}
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}
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2018-03-13 14:47:03 +08:00
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if (DefInsn->getOpcode() == BPF::COPY) {
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MachineOperand &opnd = DefInsn->getOperand(1);
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bpf: Tighten subregister definition check
The current subregister definition check stops after the MOV_32_64
instruction.
This means we are thinking all the following instruction sequences
are safe to be eliminated:
MOV_32_64 rB, wA
SLL_ri rB, rB, 32
SRL_ri rB, rB, 32
However, this is *not* true. The source subregister wA of MOV_32_64 could
come from a implicit truncation of 64-bit register in which case the high
bits of the 64-bit register is not zeroed, therefore we can't eliminate
above sequence.
For example, for i32_val, we shouldn't do the elimination:
long long bar ();
int foo (int b, int c)
{
unsigned int i32_val = (unsigned int) bar();
if (i32_val < 10)
return b;
else
return c;
}
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Signed-off-by: Yonghong Song <yhs@fb.com>
llvm-svn: 327365
2018-03-13 14:47:00 +08:00
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if (!opnd.isReg())
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2018-03-13 14:47:03 +08:00
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return false;
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bpf: Tighten subregister definition check
The current subregister definition check stops after the MOV_32_64
instruction.
This means we are thinking all the following instruction sequences
are safe to be eliminated:
MOV_32_64 rB, wA
SLL_ri rB, rB, 32
SRL_ri rB, rB, 32
However, this is *not* true. The source subregister wA of MOV_32_64 could
come from a implicit truncation of 64-bit register in which case the high
bits of the 64-bit register is not zeroed, therefore we can't eliminate
above sequence.
For example, for i32_val, we shouldn't do the elimination:
long long bar ();
int foo (int b, int c)
{
unsigned int i32_val = (unsigned int) bar();
if (i32_val < 10)
return b;
else
return c;
}
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Signed-off-by: Yonghong Song <yhs@fb.com>
llvm-svn: 327365
2018-03-13 14:47:00 +08:00
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unsigned Reg = opnd.getReg();
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if ((TargetRegisterInfo::isVirtualRegister(Reg) &&
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2018-03-13 14:47:03 +08:00
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MRI->getRegClass(Reg) == &BPF::GPRRegClass))
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return false;
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bpf: Tighten subregister definition check
The current subregister definition check stops after the MOV_32_64
instruction.
This means we are thinking all the following instruction sequences
are safe to be eliminated:
MOV_32_64 rB, wA
SLL_ri rB, rB, 32
SRL_ri rB, rB, 32
However, this is *not* true. The source subregister wA of MOV_32_64 could
come from a implicit truncation of 64-bit register in which case the high
bits of the 64-bit register is not zeroed, therefore we can't eliminate
above sequence.
For example, for i32_val, we shouldn't do the elimination:
long long bar ();
int foo (int b, int c)
{
unsigned int i32_val = (unsigned int) bar();
if (i32_val < 10)
return b;
else
return c;
}
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Signed-off-by: Yonghong Song <yhs@fb.com>
llvm-svn: 327365
2018-03-13 14:47:00 +08:00
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}
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2018-05-14 20:53:11 +08:00
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LLVM_DEBUG(dbgs() << " One ZExt elim sequence identified.\n");
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2018-03-13 14:47:07 +08:00
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2018-03-13 14:47:03 +08:00
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return true;
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2018-02-24 07:49:32 +08:00
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}
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2018-03-13 14:47:03 +08:00
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bool BPFMIPeephole::eliminateZExtSeq(void) {
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MachineInstr* ToErase = nullptr;
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2018-02-24 07:49:32 +08:00
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bool Eliminated = false;
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for (MachineBasicBlock &MBB : *MF) {
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for (MachineInstr &MI : MBB) {
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2018-03-13 14:47:03 +08:00
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// If the previous instruction was marked for elimination, remove it now.
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if (ToErase) {
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ToErase->eraseFromParent();
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ToErase = nullptr;
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}
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// Eliminate the 32-bit to 64-bit zero extension sequence when possible.
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//
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// MOV_32_64 rB, wA
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// SLL_ri rB, rB, 32
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// SRL_ri rB, rB, 32
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if (MI.getOpcode() == BPF::SRL_ri &&
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MI.getOperand(2).getImm() == 32) {
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unsigned DstReg = MI.getOperand(0).getReg();
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unsigned ShfReg = MI.getOperand(1).getReg();
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MachineInstr *SllMI = MRI->getVRegDef(ShfReg);
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2018-05-14 20:53:11 +08:00
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LLVM_DEBUG(dbgs() << "Starting SRL found:");
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LLVM_DEBUG(MI.dump());
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2018-03-13 14:47:07 +08:00
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2018-03-13 14:47:03 +08:00
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if (!SllMI ||
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SllMI->isPHI() ||
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SllMI->getOpcode() != BPF::SLL_ri ||
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SllMI->getOperand(2).getImm() != 32)
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continue;
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2018-05-14 20:53:11 +08:00
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LLVM_DEBUG(dbgs() << " SLL found:");
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LLVM_DEBUG(SllMI->dump());
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2018-03-13 14:47:07 +08:00
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2018-03-13 14:47:03 +08:00
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MachineInstr *MovMI = MRI->getVRegDef(SllMI->getOperand(1).getReg());
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if (!MovMI ||
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MovMI->isPHI() ||
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MovMI->getOpcode() != BPF::MOV_32_64)
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continue;
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2018-05-14 20:53:11 +08:00
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LLVM_DEBUG(dbgs() << " Type cast Mov found:");
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LLVM_DEBUG(MovMI->dump());
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2018-03-13 14:47:07 +08:00
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2018-03-13 14:47:04 +08:00
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unsigned SubReg = MovMI->getOperand(1).getReg();
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2018-03-13 14:47:07 +08:00
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if (!isMovFrom32Def(MovMI)) {
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2018-05-14 20:53:11 +08:00
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LLVM_DEBUG(dbgs()
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<< " One ZExt elim sequence failed qualifying elim.\n");
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2018-03-13 14:47:03 +08:00
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continue;
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2018-03-13 14:47:07 +08:00
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}
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2018-03-13 14:47:03 +08:00
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BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::SUBREG_TO_REG), DstReg)
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.addImm(0).addReg(SubReg).addImm(BPF::sub_32);
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SllMI->eraseFromParent();
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MovMI->eraseFromParent();
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// MI is the right shift, we can't erase it in it's own iteration.
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// Mark it to ToErase, and erase in the next iteration.
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ToErase = &MI;
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ZExtElemNum++;
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Eliminated = true;
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2018-02-24 07:49:32 +08:00
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}
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}
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}
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return Eliminated;
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}
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} // end default namespace
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2018-03-13 14:47:06 +08:00
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INITIALIZE_PASS(BPFMIPeephole, DEBUG_TYPE,
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"BPF MachineSSA Peephole Optimization", false, false)
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2018-02-24 07:49:32 +08:00
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char BPFMIPeephole::ID = 0;
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FunctionPass* llvm::createBPFMIPeepholePass() { return new BPFMIPeephole(); }
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2018-03-13 14:47:06 +08:00
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STATISTIC(RedundantMovElemNum, "Number of redundant moves eliminated");
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namespace {
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struct BPFMIPreEmitPeephole : public MachineFunctionPass {
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static char ID;
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MachineFunction *MF;
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const TargetRegisterInfo *TRI;
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BPFMIPreEmitPeephole() : MachineFunctionPass(ID) {
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initializeBPFMIPreEmitPeepholePass(*PassRegistry::getPassRegistry());
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}
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private:
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// Initialize class variables.
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void initialize(MachineFunction &MFParm);
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bool eliminateRedundantMov(void);
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public:
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// Main entry point for this pass.
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bool runOnMachineFunction(MachineFunction &MF) override {
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if (skipFunction(MF.getFunction()))
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return false;
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initialize(MF);
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return eliminateRedundantMov();
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}
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};
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// Initialize class variables.
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void BPFMIPreEmitPeephole::initialize(MachineFunction &MFParm) {
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MF = &MFParm;
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TRI = MF->getSubtarget<BPFSubtarget>().getRegisterInfo();
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2018-05-14 20:53:11 +08:00
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LLVM_DEBUG(dbgs() << "*** BPF PreEmit peephole pass ***\n\n");
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2018-03-13 14:47:06 +08:00
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}
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bool BPFMIPreEmitPeephole::eliminateRedundantMov(void) {
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MachineInstr* ToErase = nullptr;
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bool Eliminated = false;
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for (MachineBasicBlock &MBB : *MF) {
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for (MachineInstr &MI : MBB) {
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// If the previous instruction was marked for elimination, remove it now.
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if (ToErase) {
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2018-05-14 20:53:11 +08:00
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LLVM_DEBUG(dbgs() << " Redundant Mov Eliminated:");
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LLVM_DEBUG(ToErase->dump());
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2018-03-13 14:47:06 +08:00
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ToErase->eraseFromParent();
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ToErase = nullptr;
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}
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// Eliminate identical move:
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//
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// MOV rA, rA
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//
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// This is particularly possible to happen when sub-register support
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// enabled. The special type cast insn MOV_32_64 involves different
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// register class on src (i32) and dst (i64), RA could generate useless
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// instruction due to this.
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if (MI.getOpcode() == BPF::MOV_32_64) {
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unsigned dst = MI.getOperand(0).getReg();
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unsigned dst_sub = TRI->getSubReg(dst, BPF::sub_32);
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unsigned src = MI.getOperand(1).getReg();
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if (dst_sub != src)
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continue;
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ToErase = &MI;
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RedundantMovElemNum++;
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Eliminated = true;
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}
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}
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}
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return Eliminated;
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}
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} // end default namespace
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INITIALIZE_PASS(BPFMIPreEmitPeephole, "bpf-mi-pemit-peephole",
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"BPF PreEmit Peephole Optimization", false, false)
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char BPFMIPreEmitPeephole::ID = 0;
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FunctionPass* llvm::createBPFMIPreEmitPeepholePass()
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{
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return new BPFMIPreEmitPeephole();
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}
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