2013-12-28 21:04:29 +08:00
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; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=corei7 -mattr=-sse4.1 < %s | FileCheck %s
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2013-12-28 04:20:28 +08:00
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; Verify that we don't emit packed vector shifts instructions if the
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; condition used by the vector select is a vector of constants.
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define <4 x float> @test1(<4 x float> %a, <4 x float> %b) {
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2014-10-03 09:57:38 +08:00
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; CHECK-LABEL: test1:
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; CHECK: # BB#0:
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm1
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: orps %xmm1, %xmm0
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; CHECK-NEXT: retq
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2013-12-28 04:20:28 +08:00
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%1 = select <4 x i1> <i1 true, i1 false, i1 true, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <4 x float> @test2(<4 x float> %a, <4 x float> %b) {
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2014-10-03 09:57:38 +08:00
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; CHECK-LABEL: test2:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm0, %xmm1
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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2013-12-28 04:20:28 +08:00
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%1 = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <4 x float> @test3(<4 x float> %a, <4 x float> %b) {
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2014-10-03 09:57:38 +08:00
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; CHECK-LABEL: test3:
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; CHECK: # BB#0:
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; CHECK-NEXT: movsd %xmm1, %xmm0
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; CHECK-NEXT: retq
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2013-12-28 04:20:28 +08:00
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%1 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <4 x float> @test4(<4 x float> %a, <4 x float> %b) {
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2014-10-03 09:57:38 +08:00
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; CHECK-LABEL: test4:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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2013-12-28 04:20:28 +08:00
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%1 = select <4 x i1> <i1 false, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <4 x float> @test5(<4 x float> %a, <4 x float> %b) {
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2014-10-03 09:57:38 +08:00
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; CHECK-LABEL: test5:
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; CHECK: # BB#0:
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; CHECK-NEXT: retq
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2013-12-28 04:20:28 +08:00
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%1 = select <4 x i1> <i1 true, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <8 x i16> @test6(<8 x i16> %a, <8 x i16> %b) {
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2014-10-03 09:57:38 +08:00
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; CHECK-LABEL: test6:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps {{.*#+}} xmm1 = [0,65535,0,65535,0,65535,0,65535]
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; CHECK-NEXT: andps %xmm0, %xmm1
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: orps %xmm1, %xmm0
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; CHECK-NEXT: retq
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2013-12-28 04:20:28 +08:00
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%1 = select <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>, <8 x i16> %a, <8 x i16> %a
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ret <8 x i16> %1
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}
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define <8 x i16> @test7(<8 x i16> %a, <8 x i16> %b) {
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2014-10-03 09:57:38 +08:00
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; CHECK-LABEL: test7:
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; CHECK: # BB#0:
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm1
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: orps %xmm1, %xmm0
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; CHECK-NEXT: retq
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2013-12-28 04:20:28 +08:00
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%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <8 x i16> @test8(<8 x i16> %a, <8 x i16> %b) {
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2014-10-03 09:57:38 +08:00
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; CHECK-LABEL: test8:
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; CHECK: # BB#0:
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm1
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; CHECK-NEXT: andps {{.*}}(%rip), %xmm0
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; CHECK-NEXT: orps %xmm1, %xmm0
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; CHECK-NEXT: retq
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2013-12-28 04:20:28 +08:00
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <8 x i16> @test9(<8 x i16> %a, <8 x i16> %b) {
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2014-10-03 09:57:38 +08:00
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; CHECK-LABEL: test9:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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2013-12-28 04:20:28 +08:00
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <8 x i16> @test10(<8 x i16> %a, <8 x i16> %b) {
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2014-10-03 09:57:38 +08:00
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; CHECK-LABEL: test10:
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; CHECK: # BB#0:
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; CHECK-NEXT: retq
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2013-12-28 04:20:28 +08:00
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%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <8 x i16> @test11(<8 x i16> %a, <8 x i16> %b) {
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2014-10-03 09:57:38 +08:00
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; CHECK-LABEL: test11:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps {{.*#+}} xmm2 = <0,65535,65535,0,u,65535,65535,u>
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; CHECK-NEXT: andps %xmm2, %xmm0
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; CHECK-NEXT: andnps %xmm1, %xmm2
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2014-11-05 14:43:02 +08:00
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; CHECK-NEXT: orps %xmm2, %xmm0
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2014-10-03 09:57:38 +08:00
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; CHECK-NEXT: retq
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2013-12-28 04:20:28 +08:00
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%1 = select <8 x i1> <i1 false, i1 true, i1 true, i1 false, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <8 x i16> @test12(<8 x i16> %a, <8 x i16> %b) {
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2014-10-03 09:57:38 +08:00
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; CHECK-LABEL: test12:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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2013-12-28 04:20:28 +08:00
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%1 = select <8 x i1> <i1 false, i1 false, i1 undef, i1 false, i1 false, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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define <8 x i16> @test13(<8 x i16> %a, <8 x i16> %b) {
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2014-10-03 09:57:38 +08:00
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; CHECK-LABEL: test13:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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2013-12-28 04:20:28 +08:00
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%1 = select <8 x i1> <i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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2014-01-09 02:33:04 +08:00
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; Fold (vselect (build_vector AllOnes), N1, N2) -> N1
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define <4 x float> @test14(<4 x float> %a, <4 x float> %b) {
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2014-10-03 09:57:38 +08:00
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; CHECK-LABEL: test14:
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; CHECK: # BB#0:
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; CHECK-NEXT: retq
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2014-01-09 02:33:04 +08:00
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%1 = select <4 x i1> <i1 true, i1 undef, i1 true, i1 undef>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <8 x i16> @test15(<8 x i16> %a, <8 x i16> %b) {
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2014-10-03 09:57:38 +08:00
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; CHECK-LABEL: test15:
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; CHECK: # BB#0:
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; CHECK-NEXT: retq
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2014-01-09 02:33:04 +08:00
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%1 = select <8 x i1> <i1 true, i1 true, i1 true, i1 undef, i1 undef, i1 true, i1 true, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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; Fold (vselect (build_vector AllZeros), N1, N2) -> N2
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define <4 x float> @test16(<4 x float> %a, <4 x float> %b) {
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2014-10-03 09:57:38 +08:00
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; CHECK-LABEL: test16:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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2014-01-09 02:33:04 +08:00
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%1 = select <4 x i1> <i1 false, i1 undef, i1 false, i1 undef>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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2014-10-03 09:57:38 +08:00
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}
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2014-01-09 02:33:04 +08:00
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define <8 x i16> @test17(<8 x i16> %a, <8 x i16> %b) {
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2014-10-03 09:57:38 +08:00
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; CHECK-LABEL: test17:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps %xmm1, %xmm0
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; CHECK-NEXT: retq
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2014-01-09 02:33:04 +08:00
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%1 = select <8 x i1> <i1 false, i1 false, i1 false, i1 undef, i1 undef, i1 false, i1 false, i1 undef>, <8 x i16> %a, <8 x i16> %b
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ret <8 x i16> %1
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}
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2013-12-28 04:20:28 +08:00
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[X86] Teach how to combine a vselect into a movss/movsd
Add target specific rules for combining vselect dag nodes into movss/movsd
when possible.
If the vector type of the vselect dag node in input is either MVT::v4i13 or
MVT::v4f32, then try to fold according to rules:
1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B)
2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A)
If the vector type of the vselect dag node in input is either MVT::v2i64 or
MVT::v2f64 (and we have SSE2), then try to fold according to rules:
3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B)
4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A)
llvm-svn: 199683
2014-01-21 03:35:22 +08:00
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define <4 x float> @test18(<4 x float> %a, <4 x float> %b) {
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2014-10-03 09:57:38 +08:00
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; CHECK-LABEL: test18:
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; CHECK: # BB#0:
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; CHECK-NEXT: movss %xmm1, %xmm0
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; CHECK-NEXT: retq
|
[X86] Teach how to combine a vselect into a movss/movsd
Add target specific rules for combining vselect dag nodes into movss/movsd
when possible.
If the vector type of the vselect dag node in input is either MVT::v4i13 or
MVT::v4f32, then try to fold according to rules:
1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B)
2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A)
If the vector type of the vselect dag node in input is either MVT::v2i64 or
MVT::v2f64 (and we have SSE2), then try to fold according to rules:
3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B)
4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A)
llvm-svn: 199683
2014-01-21 03:35:22 +08:00
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%1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x float> %a, <4 x float> %b
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ret <4 x float> %1
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}
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define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) {
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2014-10-03 09:57:38 +08:00
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; CHECK-LABEL: test19:
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; CHECK: # BB#0:
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; CHECK-NEXT: movss %xmm1, %xmm0
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; CHECK-NEXT: retq
|
[X86] Teach how to combine a vselect into a movss/movsd
Add target specific rules for combining vselect dag nodes into movss/movsd
when possible.
If the vector type of the vselect dag node in input is either MVT::v4i13 or
MVT::v4f32, then try to fold according to rules:
1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B)
2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A)
If the vector type of the vselect dag node in input is either MVT::v2i64 or
MVT::v2f64 (and we have SSE2), then try to fold according to rules:
3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B)
4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A)
llvm-svn: 199683
2014-01-21 03:35:22 +08:00
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|
%1 = select <4 x i1> <i1 false, i1 true, i1 true, i1 true>, <4 x i32> %a, <4 x i32> %b
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|
ret <4 x i32> %1
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|
}
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define <2 x double> @test20(<2 x double> %a, <2 x double> %b) {
|
2014-10-03 09:57:38 +08:00
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|
; CHECK-LABEL: test20:
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; CHECK: # BB#0:
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|
; CHECK-NEXT: movsd %xmm1, %xmm0
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; CHECK-NEXT: retq
|
[X86] Teach how to combine a vselect into a movss/movsd
Add target specific rules for combining vselect dag nodes into movss/movsd
when possible.
If the vector type of the vselect dag node in input is either MVT::v4i13 or
MVT::v4f32, then try to fold according to rules:
1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B)
2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A)
If the vector type of the vselect dag node in input is either MVT::v2i64 or
MVT::v2f64 (and we have SSE2), then try to fold according to rules:
3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B)
4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A)
llvm-svn: 199683
2014-01-21 03:35:22 +08:00
|
|
|
%1 = select <2 x i1> <i1 false, i1 true>, <2 x double> %a, <2 x double> %b
|
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|
|
ret <2 x double> %1
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|
}
|
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|
define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) {
|
2014-10-03 09:57:38 +08:00
|
|
|
; CHECK-LABEL: test21:
|
|
|
|
|
; CHECK: # BB#0:
|
|
|
|
|
; CHECK-NEXT: movsd %xmm1, %xmm0
|
|
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach how to combine a vselect into a movss/movsd
Add target specific rules for combining vselect dag nodes into movss/movsd
when possible.
If the vector type of the vselect dag node in input is either MVT::v4i13 or
MVT::v4f32, then try to fold according to rules:
1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B)
2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A)
If the vector type of the vselect dag node in input is either MVT::v2i64 or
MVT::v2f64 (and we have SSE2), then try to fold according to rules:
3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B)
4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A)
llvm-svn: 199683
2014-01-21 03:35:22 +08:00
|
|
|
%1 = select <2 x i1> <i1 false, i1 true>, <2 x i64> %a, <2 x i64> %b
|
|
|
|
|
ret <2 x i64> %1
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <4 x float> @test22(<4 x float> %a, <4 x float> %b) {
|
2014-10-03 09:57:38 +08:00
|
|
|
; CHECK-LABEL: test22:
|
|
|
|
|
; CHECK: # BB#0:
|
|
|
|
|
; CHECK-NEXT: movss %xmm0, %xmm1
|
|
|
|
|
; CHECK-NEXT: movaps %xmm1, %xmm0
|
|
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach how to combine a vselect into a movss/movsd
Add target specific rules for combining vselect dag nodes into movss/movsd
when possible.
If the vector type of the vselect dag node in input is either MVT::v4i13 or
MVT::v4f32, then try to fold according to rules:
1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B)
2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A)
If the vector type of the vselect dag node in input is either MVT::v2i64 or
MVT::v2f64 (and we have SSE2), then try to fold according to rules:
3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B)
4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A)
llvm-svn: 199683
2014-01-21 03:35:22 +08:00
|
|
|
%1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x float> %a, <4 x float> %b
|
|
|
|
|
ret <4 x float> %1
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <4 x i32> @test23(<4 x i32> %a, <4 x i32> %b) {
|
2014-10-03 09:57:38 +08:00
|
|
|
; CHECK-LABEL: test23:
|
|
|
|
|
; CHECK: # BB#0:
|
|
|
|
|
; CHECK-NEXT: movss %xmm0, %xmm1
|
|
|
|
|
; CHECK-NEXT: movaps %xmm1, %xmm0
|
|
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach how to combine a vselect into a movss/movsd
Add target specific rules for combining vselect dag nodes into movss/movsd
when possible.
If the vector type of the vselect dag node in input is either MVT::v4i13 or
MVT::v4f32, then try to fold according to rules:
1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B)
2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A)
If the vector type of the vselect dag node in input is either MVT::v2i64 or
MVT::v2f64 (and we have SSE2), then try to fold according to rules:
3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B)
4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A)
llvm-svn: 199683
2014-01-21 03:35:22 +08:00
|
|
|
%1 = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i32> %a, <4 x i32> %b
|
|
|
|
|
ret <4 x i32> %1
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <2 x double> @test24(<2 x double> %a, <2 x double> %b) {
|
2014-10-03 09:57:38 +08:00
|
|
|
; CHECK-LABEL: test24:
|
|
|
|
|
; CHECK: # BB#0:
|
|
|
|
|
; CHECK-NEXT: movsd %xmm0, %xmm1
|
|
|
|
|
; CHECK-NEXT: movaps %xmm1, %xmm0
|
|
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach how to combine a vselect into a movss/movsd
Add target specific rules for combining vselect dag nodes into movss/movsd
when possible.
If the vector type of the vselect dag node in input is either MVT::v4i13 or
MVT::v4f32, then try to fold according to rules:
1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B)
2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A)
If the vector type of the vselect dag node in input is either MVT::v2i64 or
MVT::v2f64 (and we have SSE2), then try to fold according to rules:
3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B)
4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A)
llvm-svn: 199683
2014-01-21 03:35:22 +08:00
|
|
|
%1 = select <2 x i1> <i1 true, i1 false>, <2 x double> %a, <2 x double> %b
|
|
|
|
|
ret <2 x double> %1
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <2 x i64> @test25(<2 x i64> %a, <2 x i64> %b) {
|
2014-10-03 09:57:38 +08:00
|
|
|
; CHECK-LABEL: test25:
|
|
|
|
|
; CHECK: # BB#0:
|
|
|
|
|
; CHECK-NEXT: movsd %xmm0, %xmm1
|
|
|
|
|
; CHECK-NEXT: movaps %xmm1, %xmm0
|
|
|
|
|
; CHECK-NEXT: retq
|
[X86] Teach how to combine a vselect into a movss/movsd
Add target specific rules for combining vselect dag nodes into movss/movsd
when possible.
If the vector type of the vselect dag node in input is either MVT::v4i13 or
MVT::v4f32, then try to fold according to rules:
1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B)
2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A)
If the vector type of the vselect dag node in input is either MVT::v2i64 or
MVT::v2f64 (and we have SSE2), then try to fold according to rules:
3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B)
4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A)
llvm-svn: 199683
2014-01-21 03:35:22 +08:00
|
|
|
%1 = select <2 x i1> <i1 true, i1 false>, <2 x i64> %a, <2 x i64> %b
|
|
|
|
|
ret <2 x i64> %1
|
|
|
|
|
}
|
|
|
|
|
|
2014-05-31 07:03:11 +08:00
|
|
|
define <4 x float> @select_of_shuffles_0(<2 x float> %a0, <2 x float> %b0, <2 x float> %a1, <2 x float> %b1) {
|
2014-10-03 09:57:38 +08:00
|
|
|
; CHECK-LABEL: select_of_shuffles_0:
|
|
|
|
|
; CHECK: # BB#0:
|
[x86] Enable the new vector shuffle lowering by default.
Update the entire regression test suite for the new shuffles. Remove
most of the old testing which was devoted to the old shuffle lowering
path and is no longer relevant really. Also remove a few other random
tests that only really exercised shuffles and only incidently or without
any interesting aspects to them.
Benchmarking that I have done shows a few small regressions with this on
LNT, zero measurable regressions on real, large applications, and for
several benchmarks where the loop vectorizer fires in the hot path it
shows 5% to 40% improvements for SSE2 and SSE3 code running on Sandy
Bridge machines. Running on AMD machines shows even more dramatic
improvements.
When using newer ISA vector extensions the gains are much more modest,
but the code is still better on the whole. There are a few regressions
being tracked (PR21137, PR21138, PR21139) but by and large this is
expected to be a win for x86 generated code performance.
It is also more correct than the code it replaces. I have fuzz tested
this extensively with ISA extensions up through AVX2 and found no
crashes or miscompiles (yet...). The old lowering had a few miscompiles
and crashers after a somewhat smaller amount of fuzz testing.
There is one significant area where the new code path lags behind and
that is in AVX-512 support. However, there was *extremely little*
support for that already and so this isn't a significant step backwards
and the new framework will probably make it easier to implement lowering
that uses the full power of AVX-512's table-based shuffle+blend (IMO).
Many thanks to Quentin, Andrea, Robert, and others for benchmarking
assistance. Thanks to Adam and others for help with AVX-512. Thanks to
Hal, Eric, and *many* others for answering my incessant questions about
how the backend actually works. =]
I will leave the old code path in the tree until the 3 PRs above are at
least resolved to folks' satisfaction. Then I will rip it (and 1000s of
lines of code) out. =] I don't expect this flag to stay around for very
long. It may not survive next week.
llvm-svn: 219046
2014-10-04 11:52:55 +08:00
|
|
|
; CHECK-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm2[0]
|
|
|
|
|
; CHECK-NEXT: unpcklpd {{.*#+}} xmm1 = xmm1[0],xmm3[0]
|
2014-10-03 09:57:38 +08:00
|
|
|
; CHECK-NEXT: subps %xmm1, %xmm0
|
|
|
|
|
; CHECK-NEXT: retq
|
2014-05-31 07:03:11 +08:00
|
|
|
%1 = shufflevector <2 x float> %a0, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
|
|
|
|
|
%2 = shufflevector <2 x float> %a1, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
|
|
|
|
|
%3 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %2, <4 x float> %1
|
|
|
|
|
%4 = shufflevector <2 x float> %b0, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
|
|
|
|
|
%5 = shufflevector <2 x float> %b1, <2 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
|
|
|
|
|
%6 = select <4 x i1> <i1 false, i1 false, i1 true, i1 true>, <4 x float> %5, <4 x float> %4
|
|
|
|
|
%7 = fsub <4 x float> %3, %6
|
|
|
|
|
ret <4 x float> %7
|
|
|
|
|
}
|
2014-08-21 21:28:02 +08:00
|
|
|
|
|
|
|
|
; PR20677
|
|
|
|
|
define <16 x double> @select_illegal(<16 x double> %a, <16 x double> %b) {
|
2014-10-03 09:57:38 +08:00
|
|
|
; CHECK-LABEL: select_illegal:
|
|
|
|
|
; CHECK: # BB#0:
|
|
|
|
|
; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm4
|
|
|
|
|
; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm5
|
|
|
|
|
; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm6
|
|
|
|
|
; CHECK-NEXT: movaps {{[0-9]+}}(%rsp), %xmm7
|
|
|
|
|
; CHECK-NEXT: movaps %xmm7, 112(%rdi)
|
|
|
|
|
; CHECK-NEXT: movaps %xmm6, 96(%rdi)
|
|
|
|
|
; CHECK-NEXT: movaps %xmm5, 80(%rdi)
|
|
|
|
|
; CHECK-NEXT: movaps %xmm4, 64(%rdi)
|
|
|
|
|
; CHECK-NEXT: movaps %xmm3, 48(%rdi)
|
|
|
|
|
; CHECK-NEXT: movaps %xmm2, 32(%rdi)
|
|
|
|
|
; CHECK-NEXT: movaps %xmm1, 16(%rdi)
|
|
|
|
|
; CHECK-NEXT: movaps %xmm0, (%rdi)
|
|
|
|
|
; CHECK-NEXT: retq
|
2014-08-21 21:28:02 +08:00
|
|
|
%sel = select <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x double> %a, <16 x double> %b
|
|
|
|
|
ret <16 x double> %sel
|
|
|
|
|
}
|