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llvm-project/llvm/test/CodeGen/X86/gather-addresses.ll

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Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
; RUN: llc -mtriple=x86_64-linux -mcpu=nehalem < %s | FileCheck %s --check-prefix=LIN
; RUN: llc -mtriple=x86_64-win32 -mcpu=nehalem < %s | FileCheck %s --check-prefix=WIN
Add an rdar number to this test. llvm-svn: 98654
2010-03-17 03:08:20 +08:00
; rdar://7398554
Recognize code for doing vector gather/scatter index calculations with 32-bit indices. Instead of shuffling each element out of the index vector, when all indices are needed, just store the input vector to the stack and load the elements out. llvm-svn: 98588
2010-03-16 07:23:03 +08:00
; When doing vector gather-scatter index calculation with 32-bit indices,
; bounce the vector off of cache rather than shuffling each individual
; element out of the index vector.
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
2013-10-16 07:33:07 +08:00
; CHECK: foo:
; LIN: movaps (%rsi), %xmm0
; LIN: andps (%rdx), %xmm0
; LIN: movaps %xmm0, -24(%rsp)
; LIN: movslq -24(%rsp), %[[REG1:r.+]]
; LIN: movslq -20(%rsp), %[[REG2:r.+]]
; LIN: movslq -16(%rsp), %[[REG3:r.+]]
; LIN: movslq -12(%rsp), %[[REG4:r.+]]
; LIN: movsd (%rdi,%[[REG1]],8), %xmm0
; LIN: movhpd (%rdi,%[[REG2]],8), %xmm0
; LIN: movsd (%rdi,%[[REG3]],8), %xmm1
; LIN: movhpd (%rdi,%[[REG4]],8), %xmm1
; WIN: movaps (%rdx), %xmm0
; WIN: andps (%r8), %xmm0
; WIN: movaps %xmm0, (%rsp)
; WIN: movslq (%rsp), %[[REG1:r.+]]
; WIN: movslq 4(%rsp), %[[REG2:r.+]]
; WIN: movslq 8(%rsp), %[[REG3:r.+]]
; WIN: movslq 12(%rsp), %[[REG4:r.+]]
; WIN: movsd (%rcx,%[[REG1]],8), %xmm0
; WIN: movhpd (%rcx,%[[REG2]],8), %xmm0
; WIN: movsd (%rcx,%[[REG3]],8), %xmm1
; WIN: movhpd (%rcx,%[[REG4]],8), %xmm1
Recognize code for doing vector gather/scatter index calculations with 32-bit indices. Instead of shuffling each element out of the index vector, when all indices are needed, just store the input vector to the stack and load the elements out. llvm-svn: 98588
2010-03-16 07:23:03 +08:00
define <4 x double> @foo(double* %p, <4 x i32>* %i, <4 x i32>* %h) nounwind {
%a = load <4 x i32>* %i
%b = load <4 x i32>* %h
%j = and <4 x i32> %a, %b
%d0 = extractelement <4 x i32> %j, i32 0
%d1 = extractelement <4 x i32> %j, i32 1
%d2 = extractelement <4 x i32> %j, i32 2
%d3 = extractelement <4 x i32> %j, i32 3
%q0 = getelementptr double* %p, i32 %d0
%q1 = getelementptr double* %p, i32 %d1
%q2 = getelementptr double* %p, i32 %d2
%q3 = getelementptr double* %p, i32 %d3
%r0 = load double* %q0
%r1 = load double* %q1
%r2 = load double* %q2
%r3 = load double* %q3
%v0 = insertelement <4 x double> undef, double %r0, i32 0
%v1 = insertelement <4 x double> %v0, double %r1, i32 1
%v2 = insertelement <4 x double> %v1, double %r2, i32 2
%v3 = insertelement <4 x double> %v2, double %r3, i32 3
ret <4 x double> %v3
}