forked from OSchip/llvm-project
204 lines
7.0 KiB
LLVM
204 lines
7.0 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I-FPELIM %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs -frame-pointer=all < %s \
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; RUN: | FileCheck -check-prefix=RV64I-WITHFP %s
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; As well as calling convention details, we check that ra and fp are
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; consistently stored to fp-8 and fp-16.
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; Any tests that would have identical output for some combination of the lp64*
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; ABIs belong in calling-conv-*-common.ll. This file contains tests that will
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; have different output across those ABIs. i.e. where some arguments would be
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; passed according to the floating point ABI.
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; TODO: softened float values can be passed anyext.
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define i64 @callee_float_in_regs(i64 %a, float %b) nounwind {
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; RV64I-FPELIM-LABEL: callee_float_in_regs:
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; RV64I-FPELIM: # %bb.0:
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; RV64I-FPELIM-NEXT: addi sp, sp, -16
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; RV64I-FPELIM-NEXT: sd ra, 8(sp)
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; RV64I-FPELIM-NEXT: sd s1, 0(sp)
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; RV64I-FPELIM-NEXT: mv s1, a0
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; RV64I-FPELIM-NEXT: slli a0, a1, 32
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; RV64I-FPELIM-NEXT: srli a0, a0, 32
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; RV64I-FPELIM-NEXT: call __fixsfdi
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; RV64I-FPELIM-NEXT: add a0, s1, a0
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; RV64I-FPELIM-NEXT: ld s1, 0(sp)
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; RV64I-FPELIM-NEXT: ld ra, 8(sp)
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; RV64I-FPELIM-NEXT: addi sp, sp, 16
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; RV64I-FPELIM-NEXT: ret
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;
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; RV64I-WITHFP-LABEL: callee_float_in_regs:
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; RV64I-WITHFP: # %bb.0:
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; RV64I-WITHFP-NEXT: addi sp, sp, -32
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; RV64I-WITHFP-NEXT: sd ra, 24(sp)
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; RV64I-WITHFP-NEXT: sd s0, 16(sp)
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; RV64I-WITHFP-NEXT: sd s1, 8(sp)
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; RV64I-WITHFP-NEXT: addi s0, sp, 32
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; RV64I-WITHFP-NEXT: mv s1, a0
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; RV64I-WITHFP-NEXT: slli a0, a1, 32
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; RV64I-WITHFP-NEXT: srli a0, a0, 32
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; RV64I-WITHFP-NEXT: call __fixsfdi
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; RV64I-WITHFP-NEXT: add a0, s1, a0
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; RV64I-WITHFP-NEXT: ld s1, 8(sp)
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; RV64I-WITHFP-NEXT: ld s0, 16(sp)
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; RV64I-WITHFP-NEXT: ld ra, 24(sp)
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; RV64I-WITHFP-NEXT: addi sp, sp, 32
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; RV64I-WITHFP-NEXT: ret
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%b_fptosi = fptosi float %b to i64
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%1 = add i64 %a, %b_fptosi
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ret i64 %1
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}
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define i64 @caller_float_in_regs() nounwind {
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; RV64I-FPELIM-LABEL: caller_float_in_regs:
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; RV64I-FPELIM: # %bb.0:
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; RV64I-FPELIM-NEXT: addi sp, sp, -16
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; RV64I-FPELIM-NEXT: sd ra, 8(sp)
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; RV64I-FPELIM-NEXT: addi a0, zero, 1
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; RV64I-FPELIM-NEXT: lui a1, 262144
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; RV64I-FPELIM-NEXT: call callee_float_in_regs
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; RV64I-FPELIM-NEXT: ld ra, 8(sp)
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; RV64I-FPELIM-NEXT: addi sp, sp, 16
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; RV64I-FPELIM-NEXT: ret
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;
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; RV64I-WITHFP-LABEL: caller_float_in_regs:
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; RV64I-WITHFP: # %bb.0:
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; RV64I-WITHFP-NEXT: addi sp, sp, -16
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; RV64I-WITHFP-NEXT: sd ra, 8(sp)
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; RV64I-WITHFP-NEXT: sd s0, 0(sp)
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; RV64I-WITHFP-NEXT: addi s0, sp, 16
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; RV64I-WITHFP-NEXT: addi a0, zero, 1
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; RV64I-WITHFP-NEXT: lui a1, 262144
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; RV64I-WITHFP-NEXT: call callee_float_in_regs
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; RV64I-WITHFP-NEXT: ld s0, 0(sp)
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; RV64I-WITHFP-NEXT: ld ra, 8(sp)
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; RV64I-WITHFP-NEXT: addi sp, sp, 16
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; RV64I-WITHFP-NEXT: ret
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%1 = call i64 @callee_float_in_regs(i64 1, float 2.0)
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ret i64 %1
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}
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define i64 @callee_float_on_stack(i128 %a, i128 %b, i128 %c, i128 %d, float %e) nounwind {
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; RV64I-FPELIM-LABEL: callee_float_on_stack:
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; RV64I-FPELIM: # %bb.0:
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; RV64I-FPELIM-NEXT: lw a0, 0(sp)
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; RV64I-FPELIM-NEXT: ret
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;
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; RV64I-WITHFP-LABEL: callee_float_on_stack:
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; RV64I-WITHFP: # %bb.0:
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; RV64I-WITHFP-NEXT: addi sp, sp, -16
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; RV64I-WITHFP-NEXT: sd ra, 8(sp)
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; RV64I-WITHFP-NEXT: sd s0, 0(sp)
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; RV64I-WITHFP-NEXT: addi s0, sp, 16
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; RV64I-WITHFP-NEXT: lw a0, 0(s0)
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; RV64I-WITHFP-NEXT: ld s0, 0(sp)
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; RV64I-WITHFP-NEXT: ld ra, 8(sp)
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; RV64I-WITHFP-NEXT: addi sp, sp, 16
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; RV64I-WITHFP-NEXT: ret
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%1 = trunc i128 %d to i64
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%2 = bitcast float %e to i32
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%3 = sext i32 %2 to i64
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%4 = add i64 %1, %3
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ret i64 %3
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}
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define i64 @caller_float_on_stack() nounwind {
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; RV64I-FPELIM-LABEL: caller_float_on_stack:
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; RV64I-FPELIM: # %bb.0:
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; RV64I-FPELIM-NEXT: addi sp, sp, -16
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; RV64I-FPELIM-NEXT: sd ra, 8(sp)
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; RV64I-FPELIM-NEXT: lui a0, 264704
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; RV64I-FPELIM-NEXT: sd a0, 0(sp)
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; RV64I-FPELIM-NEXT: addi a0, zero, 1
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; RV64I-FPELIM-NEXT: mv a1, zero
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; RV64I-FPELIM-NEXT: addi a2, zero, 2
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; RV64I-FPELIM-NEXT: mv a3, zero
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; RV64I-FPELIM-NEXT: addi a4, zero, 3
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; RV64I-FPELIM-NEXT: mv a5, zero
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; RV64I-FPELIM-NEXT: addi a6, zero, 4
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; RV64I-FPELIM-NEXT: mv a7, zero
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; RV64I-FPELIM-NEXT: call callee_float_on_stack
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; RV64I-FPELIM-NEXT: ld ra, 8(sp)
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; RV64I-FPELIM-NEXT: addi sp, sp, 16
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; RV64I-FPELIM-NEXT: ret
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;
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; RV64I-WITHFP-LABEL: caller_float_on_stack:
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; RV64I-WITHFP: # %bb.0:
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; RV64I-WITHFP-NEXT: addi sp, sp, -32
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; RV64I-WITHFP-NEXT: sd ra, 24(sp)
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; RV64I-WITHFP-NEXT: sd s0, 16(sp)
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; RV64I-WITHFP-NEXT: addi s0, sp, 32
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; RV64I-WITHFP-NEXT: lui a0, 264704
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; RV64I-WITHFP-NEXT: sd a0, 0(sp)
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; RV64I-WITHFP-NEXT: addi a0, zero, 1
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; RV64I-WITHFP-NEXT: mv a1, zero
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; RV64I-WITHFP-NEXT: addi a2, zero, 2
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; RV64I-WITHFP-NEXT: mv a3, zero
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; RV64I-WITHFP-NEXT: addi a4, zero, 3
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; RV64I-WITHFP-NEXT: mv a5, zero
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; RV64I-WITHFP-NEXT: addi a6, zero, 4
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; RV64I-WITHFP-NEXT: mv a7, zero
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; RV64I-WITHFP-NEXT: call callee_float_on_stack
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; RV64I-WITHFP-NEXT: ld s0, 16(sp)
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; RV64I-WITHFP-NEXT: ld ra, 24(sp)
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; RV64I-WITHFP-NEXT: addi sp, sp, 32
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; RV64I-WITHFP-NEXT: ret
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%1 = call i64 @callee_float_on_stack(i128 1, i128 2, i128 3, i128 4, float 5.0)
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ret i64 %1
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}
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define float @callee_tiny_scalar_ret() nounwind {
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; RV64I-FPELIM-LABEL: callee_tiny_scalar_ret:
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; RV64I-FPELIM: # %bb.0:
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; RV64I-FPELIM-NEXT: lui a0, 260096
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; RV64I-FPELIM-NEXT: ret
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;
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; RV64I-WITHFP-LABEL: callee_tiny_scalar_ret:
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; RV64I-WITHFP: # %bb.0:
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; RV64I-WITHFP-NEXT: addi sp, sp, -16
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; RV64I-WITHFP-NEXT: sd ra, 8(sp)
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; RV64I-WITHFP-NEXT: sd s0, 0(sp)
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; RV64I-WITHFP-NEXT: addi s0, sp, 16
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; RV64I-WITHFP-NEXT: lui a0, 260096
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; RV64I-WITHFP-NEXT: ld s0, 0(sp)
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; RV64I-WITHFP-NEXT: ld ra, 8(sp)
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; RV64I-WITHFP-NEXT: addi sp, sp, 16
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; RV64I-WITHFP-NEXT: ret
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ret float 1.0
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}
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; The sign extension of the float return is necessary, as softened floats are
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; passed anyext.
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define i64 @caller_tiny_scalar_ret() nounwind {
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; RV64I-FPELIM-LABEL: caller_tiny_scalar_ret:
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; RV64I-FPELIM: # %bb.0:
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; RV64I-FPELIM-NEXT: addi sp, sp, -16
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; RV64I-FPELIM-NEXT: sd ra, 8(sp)
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; RV64I-FPELIM-NEXT: call callee_tiny_scalar_ret
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; RV64I-FPELIM-NEXT: sext.w a0, a0
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; RV64I-FPELIM-NEXT: ld ra, 8(sp)
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; RV64I-FPELIM-NEXT: addi sp, sp, 16
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; RV64I-FPELIM-NEXT: ret
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;
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; RV64I-WITHFP-LABEL: caller_tiny_scalar_ret:
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; RV64I-WITHFP: # %bb.0:
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; RV64I-WITHFP-NEXT: addi sp, sp, -16
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; RV64I-WITHFP-NEXT: sd ra, 8(sp)
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; RV64I-WITHFP-NEXT: sd s0, 0(sp)
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; RV64I-WITHFP-NEXT: addi s0, sp, 16
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; RV64I-WITHFP-NEXT: call callee_tiny_scalar_ret
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; RV64I-WITHFP-NEXT: sext.w a0, a0
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; RV64I-WITHFP-NEXT: ld s0, 0(sp)
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; RV64I-WITHFP-NEXT: ld ra, 8(sp)
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; RV64I-WITHFP-NEXT: addi sp, sp, 16
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; RV64I-WITHFP-NEXT: ret
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%1 = call float @callee_tiny_scalar_ret()
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%2 = bitcast float %1 to i32
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%3 = sext i32 %2 to i64
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ret i64 %3
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}
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