2015-01-13 06:19:22 +08:00
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//===-- llvm/CodeGen/DwarfExpression.cpp - Dwarf Debug Framework ----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains support for writing dwarf debug info into asm files.
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//
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//===----------------------------------------------------------------------===//
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#include "DwarfExpression.h"
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2015-01-13 07:36:56 +08:00
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#include "DwarfDebug.h"
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2015-01-13 06:19:22 +08:00
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#include "llvm/ADT/SmallBitVector.h"
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2015-01-13 07:36:56 +08:00
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#include "llvm/CodeGen/AsmPrinter.h"
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2015-01-13 06:19:22 +08:00
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#include "llvm/Support/Dwarf.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Target/TargetSubtargetInfo.h"
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using namespace llvm;
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2015-01-13 08:04:06 +08:00
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void DwarfExpression::AddReg(int DwarfReg, const char *Comment) {
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2015-01-13 06:19:22 +08:00
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assert(DwarfReg >= 0 && "invalid negative dwarf register number");
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if (DwarfReg < 32) {
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EmitOp(dwarf::DW_OP_reg0 + DwarfReg, Comment);
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} else {
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EmitOp(dwarf::DW_OP_regx, Comment);
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EmitUnsigned(DwarfReg);
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}
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}
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void DwarfExpression::AddRegIndirect(int DwarfReg, int Offset, bool Deref) {
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assert(DwarfReg >= 0 && "invalid negative dwarf register number");
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if (DwarfReg < 32) {
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EmitOp(dwarf::DW_OP_breg0 + DwarfReg);
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} else {
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EmitOp(dwarf::DW_OP_bregx);
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EmitUnsigned(DwarfReg);
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}
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EmitSigned(Offset);
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if (Deref)
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EmitOp(dwarf::DW_OP_deref);
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}
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2015-01-13 08:04:06 +08:00
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void DwarfExpression::AddOpPiece(unsigned SizeInBits, unsigned OffsetInBits) {
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2015-01-13 06:19:22 +08:00
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assert(SizeInBits > 0 && "piece has size zero");
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const unsigned SizeOfByte = 8;
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if (OffsetInBits > 0 || SizeInBits % SizeOfByte) {
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EmitOp(dwarf::DW_OP_bit_piece);
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EmitUnsigned(SizeInBits);
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EmitUnsigned(OffsetInBits);
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} else {
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EmitOp(dwarf::DW_OP_piece);
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unsigned ByteSize = SizeInBits / SizeOfByte;
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EmitUnsigned(ByteSize);
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}
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}
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void DwarfExpression::AddShr(unsigned ShiftBy) {
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EmitOp(dwarf::DW_OP_constu);
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EmitUnsigned(ShiftBy);
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EmitOp(dwarf::DW_OP_shr);
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}
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2016-05-21 03:35:17 +08:00
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bool DwarfExpression::AddMachineRegIndirect(const TargetRegisterInfo &TRI,
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unsigned MachineReg, int Offset) {
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if (isFrameRegister(TRI, MachineReg)) {
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2015-01-13 06:19:26 +08:00
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// If variable offset is based in frame register then use fbreg.
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EmitOp(dwarf::DW_OP_fbreg);
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EmitSigned(Offset);
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2015-03-04 04:12:52 +08:00
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return true;
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2015-01-13 06:19:26 +08:00
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}
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2015-03-04 04:12:52 +08:00
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int DwarfReg = TRI.getDwarfRegNum(MachineReg, false);
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if (DwarfReg < 0)
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return false;
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AddRegIndirect(DwarfReg, Offset);
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2015-01-13 06:19:26 +08:00
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return true;
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}
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2016-05-21 03:35:17 +08:00
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bool DwarfExpression::AddMachineRegPiece(const TargetRegisterInfo &TRI,
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unsigned MachineReg,
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2015-01-13 06:19:22 +08:00
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unsigned PieceSizeInBits,
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unsigned PieceOffsetInBits) {
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2015-03-03 06:02:33 +08:00
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if (!TRI.isPhysicalRegister(MachineReg))
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2015-01-26 03:04:08 +08:00
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return false;
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2015-03-03 06:02:33 +08:00
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int Reg = TRI.getDwarfRegNum(MachineReg, false);
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2015-01-13 06:19:22 +08:00
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// If this is a valid register number, emit it.
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if (Reg >= 0) {
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AddReg(Reg);
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2015-01-13 06:37:16 +08:00
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if (PieceSizeInBits)
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AddOpPiece(PieceSizeInBits, PieceOffsetInBits);
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2015-01-14 09:01:28 +08:00
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return true;
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2015-01-13 06:19:22 +08:00
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}
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// Walk up the super-register chain until we find a valid number.
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// For example, EAX on x86_64 is a 32-bit piece of RAX with offset 0.
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2015-03-03 06:02:33 +08:00
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for (MCSuperRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
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Reg = TRI.getDwarfRegNum(*SR, false);
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2015-01-13 06:19:22 +08:00
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if (Reg >= 0) {
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2015-03-03 06:02:33 +08:00
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unsigned Idx = TRI.getSubRegIndex(*SR, MachineReg);
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unsigned Size = TRI.getSubRegIdxSize(Idx);
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unsigned RegOffset = TRI.getSubRegIdxOffset(Idx);
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2015-01-13 06:19:22 +08:00
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AddReg(Reg, "super-register");
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if (PieceOffsetInBits == RegOffset) {
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AddOpPiece(Size, RegOffset);
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} else {
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// If this is part of a variable in a sub-register at a
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// non-zero offset, we need to manually shift the value into
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// place, since the DW_OP_piece describes the part of the
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// variable, not the position of the subregister.
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if (RegOffset)
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AddShr(RegOffset);
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AddOpPiece(Size, PieceOffsetInBits);
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}
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2015-01-14 09:01:28 +08:00
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return true;
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2015-01-13 06:19:22 +08:00
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}
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}
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// Otherwise, attempt to find a covering set of sub-register numbers.
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// For example, Q0 on ARM is a composition of D0+D1.
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//
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// Keep track of the current position so we can emit the more
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// efficient DW_OP_piece.
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unsigned CurPos = PieceOffsetInBits;
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// The size of the register in bits, assuming 8 bits per byte.
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2015-03-03 06:02:33 +08:00
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unsigned RegSize = TRI.getMinimalPhysRegClass(MachineReg)->getSize() * 8;
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2015-01-13 06:19:22 +08:00
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// Keep track of the bits in the register we already emitted, so we
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// can avoid emitting redundant aliasing subregs.
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SmallBitVector Coverage(RegSize, false);
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2015-03-03 06:02:33 +08:00
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for (MCSubRegIterator SR(MachineReg, &TRI); SR.isValid(); ++SR) {
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unsigned Idx = TRI.getSubRegIndex(MachineReg, *SR);
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unsigned Size = TRI.getSubRegIdxSize(Idx);
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unsigned Offset = TRI.getSubRegIdxOffset(Idx);
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Reg = TRI.getDwarfRegNum(*SR, false);
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2015-01-13 06:19:22 +08:00
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// Intersection between the bits we already emitted and the bits
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// covered by this subregister.
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SmallBitVector Intersection(RegSize, false);
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Intersection.set(Offset, Offset + Size);
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Intersection ^= Coverage;
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// If this sub-register has a DWARF number and we haven't covered
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// its range, emit a DWARF piece for it.
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if (Reg >= 0 && Intersection.any()) {
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AddReg(Reg, "sub-register");
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AddOpPiece(Size, Offset == CurPos ? 0 : Offset);
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CurPos = Offset + Size;
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// Mark it as emitted.
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Coverage.set(Offset, Offset + Size);
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}
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}
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2015-01-14 09:01:28 +08:00
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return CurPos > PieceOffsetInBits;
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2015-01-13 06:19:22 +08:00
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}
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2015-01-13 08:04:06 +08:00
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2016-04-08 08:38:37 +08:00
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void DwarfExpression::AddStackValue() {
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if (DwarfVersion >= 4)
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EmitOp(dwarf::DW_OP_stack_value);
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}
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2015-01-13 08:04:06 +08:00
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void DwarfExpression::AddSignedConstant(int Value) {
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EmitOp(dwarf::DW_OP_consts);
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EmitSigned(Value);
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2016-04-08 08:38:37 +08:00
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AddStackValue();
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2015-01-13 08:04:06 +08:00
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}
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void DwarfExpression::AddUnsignedConstant(unsigned Value) {
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EmitOp(dwarf::DW_OP_constu);
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EmitUnsigned(Value);
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2016-04-08 08:38:37 +08:00
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AddStackValue();
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}
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2016-06-09 03:09:22 +08:00
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void DwarfExpression::AddUnsignedConstant(const APInt &Value) {
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2016-04-08 08:38:37 +08:00
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unsigned Size = Value.getBitWidth();
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const uint64_t *Data = Value.getRawData();
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// Chop it up into 64-bit pieces, because that's the maximum that
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// AddUnsignedConstant takes.
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unsigned Offset = 0;
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while (Offset < Size) {
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AddUnsignedConstant(*Data++);
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if (Offset == 0 && Size <= 64)
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break;
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AddOpPiece(std::min(Size-Offset, 64u), Offset);
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Offset += 64;
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}
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2015-01-13 08:04:06 +08:00
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}
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Debug Info: Move the complex expression handling (=the remainder) of
emitDebugLocValue() into DwarfExpression.
Ought to be NFC, but it actually uncovered a bug in the debug-loc-asan.ll
testcase. The testcase checks that the address of variable "y" is stored
at [RSP+16], which also lines up with the comment.
It also check(ed) that the *value* of "y" is stored in RDI before that,
but that is actually incorrect, since RDI is the very value that is
stored in [RSP+16]. Here's the assembler output:
movb 2147450880(%rcx), %r8b
#DEBUG_VALUE: bar:y <- RDI
cmpb $0, %r8b
movq %rax, 32(%rsp) # 8-byte Spill
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
.Ltmp3:
#DEBUG_VALUE: bar:y <- [RSP+16]
Fixed the comment to spell out the correct register and the check to
expect an address rather than a value.
Note that the range that is emitted for the RDI location was and is still
wrong, it claims to begin at the function prologue, but really it should
start where RDI is first assigned.
llvm-svn: 225851
2015-01-14 07:39:11 +08:00
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static unsigned getOffsetOrZero(unsigned OffsetInBits,
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unsigned PieceOffsetInBits) {
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if (OffsetInBits == PieceOffsetInBits)
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return 0;
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assert(OffsetInBits >= PieceOffsetInBits && "overlapping pieces");
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return OffsetInBits;
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}
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2016-05-21 03:35:17 +08:00
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bool DwarfExpression::AddMachineRegExpression(const TargetRegisterInfo &TRI,
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const DIExpression *Expr,
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Debug Info: Move the complex expression handling (=the remainder) of
emitDebugLocValue() into DwarfExpression.
Ought to be NFC, but it actually uncovered a bug in the debug-loc-asan.ll
testcase. The testcase checks that the address of variable "y" is stored
at [RSP+16], which also lines up with the comment.
It also check(ed) that the *value* of "y" is stored in RDI before that,
but that is actually incorrect, since RDI is the very value that is
stored in [RSP+16]. Here's the assembler output:
movb 2147450880(%rcx), %r8b
#DEBUG_VALUE: bar:y <- RDI
cmpb $0, %r8b
movq %rax, 32(%rsp) # 8-byte Spill
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
.Ltmp3:
#DEBUG_VALUE: bar:y <- [RSP+16]
Fixed the comment to spell out the correct register and the check to
expect an address rather than a value.
Note that the range that is emitted for the RDI location was and is still
wrong, it claims to begin at the function prologue, but really it should
start where RDI is first assigned.
llvm-svn: 225851
2015-01-14 07:39:11 +08:00
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unsigned MachineReg,
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unsigned PieceOffsetInBits) {
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2015-04-07 11:45:57 +08:00
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auto I = Expr->expr_op_begin();
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auto E = Expr->expr_op_end();
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2015-03-05 01:39:33 +08:00
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if (I == E)
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2016-05-21 03:35:17 +08:00
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return AddMachineRegPiece(TRI, MachineReg);
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2015-01-22 08:00:59 +08:00
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2015-03-05 01:39:33 +08:00
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// Pattern-match combinations for which more efficient representations exist
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// first.
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2015-01-22 08:00:59 +08:00
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bool ValidReg = false;
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2015-04-07 11:45:57 +08:00
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switch (I->getOp()) {
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2015-02-10 07:57:15 +08:00
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case dwarf::DW_OP_bit_piece: {
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2015-04-07 11:45:57 +08:00
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unsigned OffsetInBits = I->getArg(0);
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unsigned SizeInBits = I->getArg(1);
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2015-01-22 08:00:59 +08:00
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// Piece always comes at the end of the expression.
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2016-05-21 03:35:17 +08:00
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return AddMachineRegPiece(TRI, MachineReg, SizeInBits,
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2015-01-22 08:00:59 +08:00
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getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
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}
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2015-10-01 03:55:43 +08:00
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case dwarf::DW_OP_plus:
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case dwarf::DW_OP_minus: {
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// [DW_OP_reg,Offset,DW_OP_plus, DW_OP_deref] --> [DW_OP_breg, Offset].
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// [DW_OP_reg,Offset,DW_OP_minus,DW_OP_deref] --> [DW_OP_breg,-Offset].
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2015-04-07 11:45:57 +08:00
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auto N = I.getNext();
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if (N != E && N->getOp() == dwarf::DW_OP_deref) {
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2015-06-10 02:01:51 +08:00
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unsigned Offset = I->getArg(0);
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2015-10-01 03:55:43 +08:00
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ValidReg = AddMachineRegIndirect(
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2016-05-21 03:35:17 +08:00
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TRI, MachineReg, I->getOp() == dwarf::DW_OP_plus ? Offset : -Offset);
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2015-01-22 08:00:59 +08:00
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std::advance(I, 2);
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2015-06-10 02:01:51 +08:00
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break;
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} else
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2016-05-21 03:35:17 +08:00
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ValidReg = AddMachineRegPiece(TRI, MachineReg);
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2015-03-05 01:39:33 +08:00
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}
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case dwarf::DW_OP_deref: {
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// [DW_OP_reg,DW_OP_deref] --> [DW_OP_breg].
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2016-05-21 03:35:17 +08:00
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ValidReg = AddMachineRegIndirect(TRI, MachineReg);
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2015-03-05 01:39:33 +08:00
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++I;
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break;
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}
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2015-01-22 08:00:59 +08:00
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default:
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llvm_unreachable("unsupported operand");
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}
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2015-01-14 09:01:28 +08:00
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if (!ValidReg)
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return false;
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Debug Info: Move the complex expression handling (=the remainder) of
emitDebugLocValue() into DwarfExpression.
Ought to be NFC, but it actually uncovered a bug in the debug-loc-asan.ll
testcase. The testcase checks that the address of variable "y" is stored
at [RSP+16], which also lines up with the comment.
It also check(ed) that the *value* of "y" is stored in RDI before that,
but that is actually incorrect, since RDI is the very value that is
stored in [RSP+16]. Here's the assembler output:
movb 2147450880(%rcx), %r8b
#DEBUG_VALUE: bar:y <- RDI
cmpb $0, %r8b
movq %rax, 32(%rsp) # 8-byte Spill
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
.Ltmp3:
#DEBUG_VALUE: bar:y <- [RSP+16]
Fixed the comment to spell out the correct register and the check to
expect an address rather than a value.
Note that the range that is emitted for the RDI location was and is still
wrong, it claims to begin at the function prologue, but really it should
start where RDI is first assigned.
llvm-svn: 225851
2015-01-14 07:39:11 +08:00
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// Emit remaining elements of the expression.
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2015-03-05 01:39:33 +08:00
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AddExpression(I, E, PieceOffsetInBits);
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2015-01-14 09:01:28 +08:00
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return true;
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Debug Info: Move the complex expression handling (=the remainder) of
emitDebugLocValue() into DwarfExpression.
Ought to be NFC, but it actually uncovered a bug in the debug-loc-asan.ll
testcase. The testcase checks that the address of variable "y" is stored
at [RSP+16], which also lines up with the comment.
It also check(ed) that the *value* of "y" is stored in RDI before that,
but that is actually incorrect, since RDI is the very value that is
stored in [RSP+16]. Here's the assembler output:
movb 2147450880(%rcx), %r8b
#DEBUG_VALUE: bar:y <- RDI
cmpb $0, %r8b
movq %rax, 32(%rsp) # 8-byte Spill
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
.Ltmp3:
#DEBUG_VALUE: bar:y <- [RSP+16]
Fixed the comment to spell out the correct register and the check to
expect an address rather than a value.
Note that the range that is emitted for the RDI location was and is still
wrong, it claims to begin at the function prologue, but really it should
start where RDI is first assigned.
llvm-svn: 225851
2015-01-14 07:39:11 +08:00
|
|
|
}
|
|
|
|
|
2015-04-30 00:38:44 +08:00
|
|
|
void DwarfExpression::AddExpression(DIExpression::expr_op_iterator I,
|
|
|
|
DIExpression::expr_op_iterator E,
|
Debug Info: Move the complex expression handling (=the remainder) of
emitDebugLocValue() into DwarfExpression.
Ought to be NFC, but it actually uncovered a bug in the debug-loc-asan.ll
testcase. The testcase checks that the address of variable "y" is stored
at [RSP+16], which also lines up with the comment.
It also check(ed) that the *value* of "y" is stored in RDI before that,
but that is actually incorrect, since RDI is the very value that is
stored in [RSP+16]. Here's the assembler output:
movb 2147450880(%rcx), %r8b
#DEBUG_VALUE: bar:y <- RDI
cmpb $0, %r8b
movq %rax, 32(%rsp) # 8-byte Spill
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
.Ltmp3:
#DEBUG_VALUE: bar:y <- [RSP+16]
Fixed the comment to spell out the correct register and the check to
expect an address rather than a value.
Note that the range that is emitted for the RDI location was and is still
wrong, it claims to begin at the function prologue, but really it should
start where RDI is first assigned.
llvm-svn: 225851
2015-01-14 07:39:11 +08:00
|
|
|
unsigned PieceOffsetInBits) {
|
2015-02-18 06:30:56 +08:00
|
|
|
for (; I != E; ++I) {
|
2015-04-07 11:45:57 +08:00
|
|
|
switch (I->getOp()) {
|
2015-02-10 07:57:15 +08:00
|
|
|
case dwarf::DW_OP_bit_piece: {
|
2015-04-07 11:45:57 +08:00
|
|
|
unsigned OffsetInBits = I->getArg(0);
|
|
|
|
unsigned SizeInBits = I->getArg(1);
|
Debug Info: Move the complex expression handling (=the remainder) of
emitDebugLocValue() into DwarfExpression.
Ought to be NFC, but it actually uncovered a bug in the debug-loc-asan.ll
testcase. The testcase checks that the address of variable "y" is stored
at [RSP+16], which also lines up with the comment.
It also check(ed) that the *value* of "y" is stored in RDI before that,
but that is actually incorrect, since RDI is the very value that is
stored in [RSP+16]. Here's the assembler output:
movb 2147450880(%rcx), %r8b
#DEBUG_VALUE: bar:y <- RDI
cmpb $0, %r8b
movq %rax, 32(%rsp) # 8-byte Spill
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
.Ltmp3:
#DEBUG_VALUE: bar:y <- [RSP+16]
Fixed the comment to spell out the correct register and the check to
expect an address rather than a value.
Note that the range that is emitted for the RDI location was and is still
wrong, it claims to begin at the function prologue, but really it should
start where RDI is first assigned.
llvm-svn: 225851
2015-01-14 07:39:11 +08:00
|
|
|
AddOpPiece(SizeInBits, getOffsetOrZero(OffsetInBits, PieceOffsetInBits));
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
case dwarf::DW_OP_plus:
|
|
|
|
EmitOp(dwarf::DW_OP_plus_uconst);
|
2015-04-07 11:45:57 +08:00
|
|
|
EmitUnsigned(I->getArg(0));
|
Debug Info: Move the complex expression handling (=the remainder) of
emitDebugLocValue() into DwarfExpression.
Ought to be NFC, but it actually uncovered a bug in the debug-loc-asan.ll
testcase. The testcase checks that the address of variable "y" is stored
at [RSP+16], which also lines up with the comment.
It also check(ed) that the *value* of "y" is stored in RDI before that,
but that is actually incorrect, since RDI is the very value that is
stored in [RSP+16]. Here's the assembler output:
movb 2147450880(%rcx), %r8b
#DEBUG_VALUE: bar:y <- RDI
cmpb $0, %r8b
movq %rax, 32(%rsp) # 8-byte Spill
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
.Ltmp3:
#DEBUG_VALUE: bar:y <- [RSP+16]
Fixed the comment to spell out the correct register and the check to
expect an address rather than a value.
Note that the range that is emitted for the RDI location was and is still
wrong, it claims to begin at the function prologue, but really it should
start where RDI is first assigned.
llvm-svn: 225851
2015-01-14 07:39:11 +08:00
|
|
|
break;
|
2015-10-01 03:55:43 +08:00
|
|
|
case dwarf::DW_OP_minus:
|
|
|
|
// There is no OP_minus_uconst.
|
|
|
|
EmitOp(dwarf::DW_OP_constu);
|
|
|
|
EmitUnsigned(I->getArg(0));
|
|
|
|
EmitOp(dwarf::DW_OP_minus);
|
|
|
|
break;
|
Debug Info: Move the complex expression handling (=the remainder) of
emitDebugLocValue() into DwarfExpression.
Ought to be NFC, but it actually uncovered a bug in the debug-loc-asan.ll
testcase. The testcase checks that the address of variable "y" is stored
at [RSP+16], which also lines up with the comment.
It also check(ed) that the *value* of "y" is stored in RDI before that,
but that is actually incorrect, since RDI is the very value that is
stored in [RSP+16]. Here's the assembler output:
movb 2147450880(%rcx), %r8b
#DEBUG_VALUE: bar:y <- RDI
cmpb $0, %r8b
movq %rax, 32(%rsp) # 8-byte Spill
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
.Ltmp3:
#DEBUG_VALUE: bar:y <- [RSP+16]
Fixed the comment to spell out the correct register and the check to
expect an address rather than a value.
Note that the range that is emitted for the RDI location was and is still
wrong, it claims to begin at the function prologue, but really it should
start where RDI is first assigned.
llvm-svn: 225851
2015-01-14 07:39:11 +08:00
|
|
|
case dwarf::DW_OP_deref:
|
|
|
|
EmitOp(dwarf::DW_OP_deref);
|
|
|
|
break;
|
|
|
|
default:
|
2015-04-22 02:44:06 +08:00
|
|
|
llvm_unreachable("unhandled opcode found in expression");
|
Debug Info: Move the complex expression handling (=the remainder) of
emitDebugLocValue() into DwarfExpression.
Ought to be NFC, but it actually uncovered a bug in the debug-loc-asan.ll
testcase. The testcase checks that the address of variable "y" is stored
at [RSP+16], which also lines up with the comment.
It also check(ed) that the *value* of "y" is stored in RDI before that,
but that is actually incorrect, since RDI is the very value that is
stored in [RSP+16]. Here's the assembler output:
movb 2147450880(%rcx), %r8b
#DEBUG_VALUE: bar:y <- RDI
cmpb $0, %r8b
movq %rax, 32(%rsp) # 8-byte Spill
movq %rsi, 24(%rsp) # 8-byte Spill
movq %rdi, 16(%rsp) # 8-byte Spill
.Ltmp3:
#DEBUG_VALUE: bar:y <- [RSP+16]
Fixed the comment to spell out the correct register and the check to
expect an address rather than a value.
Note that the range that is emitted for the RDI location was and is still
wrong, it claims to begin at the function prologue, but really it should
start where RDI is first assigned.
llvm-svn: 225851
2015-01-14 07:39:11 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|