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llvm-project/llvm/test/MC/AArch64/neon-saturating-shift.s

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AArch64/ARM64: run AArch64 NEON MC tests through ARM64 too. This skips a couple of compare ones due to the different syntaxt for floating-point 0.0. AArch64 does it more canonically, and we'll need to fiddle ARM64 to make it work. llvm-svn: 207119
2014-04-24 23:04:20 +08:00
// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
AArch64: add initial NEON support Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187567
2013-08-01 17:20:35 +08:00
// Check that the assembler can handle the documented syntax for AArch64
//------------------------------------------------------------------------------
// Vector Integer Saturating Shift Lef (Signed)
//------------------------------------------------------------------------------
sqshl v0.8b, v1.8b, v2.8b
sqshl v0.16b, v1.16b, v2.16b
sqshl v0.4h, v1.4h, v2.4h
sqshl v0.8h, v1.8h, v2.8h
sqshl v0.2s, v1.2s, v2.2s
sqshl v0.4s, v1.4s, v2.4s
sqshl v0.2d, v1.2d, v2.2d
// CHECK: sqshl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x4c,0x22,0x0e]
// CHECK: sqshl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x4c,0x22,0x4e]
// CHECK: sqshl v0.4h, v1.4h, v2.4h // encoding: [0x20,0x4c,0x62,0x0e]
// CHECK: sqshl v0.8h, v1.8h, v2.8h // encoding: [0x20,0x4c,0x62,0x4e]
// CHECK: sqshl v0.2s, v1.2s, v2.2s // encoding: [0x20,0x4c,0xa2,0x0e]
// CHECK: sqshl v0.4s, v1.4s, v2.4s // encoding: [0x20,0x4c,0xa2,0x4e]
// CHECK: sqshl v0.2d, v1.2d, v2.2d // encoding: [0x20,0x4c,0xe2,0x4e]
//------------------------------------------------------------------------------
// Vector Integer Saturating Shift Lef (Unsigned)
//------------------------------------------------------------------------------
uqshl v0.8b, v1.8b, v2.8b
uqshl v0.16b, v1.16b, v2.16b
uqshl v0.4h, v1.4h, v2.4h
uqshl v0.8h, v1.8h, v2.8h
uqshl v0.2s, v1.2s, v2.2s
uqshl v0.4s, v1.4s, v2.4s
uqshl v0.2d, v1.2d, v2.2d
// CHECK: uqshl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x4c,0x22,0x2e]
// CHECK: uqshl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x4c,0x22,0x6e]
// CHECK: uqshl v0.4h, v1.4h, v2.4h // encoding: [0x20,0x4c,0x62,0x2e]
// CHECK: uqshl v0.8h, v1.8h, v2.8h // encoding: [0x20,0x4c,0x62,0x6e]
// CHECK: uqshl v0.2s, v1.2s, v2.2s // encoding: [0x20,0x4c,0xa2,0x2e]
// CHECK: uqshl v0.4s, v1.4s, v2.4s // encoding: [0x20,0x4c,0xa2,0x6e]
// CHECK: uqshl v0.2d, v1.2d, v2.2d // encoding: [0x20,0x4c,0xe2,0x6e]