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llvm-project/llvm/test/MC/AArch64/neon-bitwise-instructions.s

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AArch64/ARM64: run AArch64 NEON MC tests through ARM64 too. This skips a couple of compare ones due to the different syntaxt for floating-point 0.0. AArch64 does it more canonically, and we'll need to fiddle ARM64 to make it work. llvm-svn: 207119
2014-04-24 23:04:20 +08:00
// RUN: llvm-mc -triple arm64-none-linux-gnu -mattr=+neon -show-encoding < %s | FileCheck %s
AArch64: add initial NEON support Patch by Ana Pazos. - Completed implementation of instruction formats: AdvSIMD three same AdvSIMD modified immediate AdvSIMD scalar pairwise - Completed implementation of instruction classes (some of the instructions in these classes belong to yet unfinished instruction formats): Vector Arithmetic Vector Immediate Vector Pairwise Arithmetic - Initial implementation of instruction formats: AdvSIMD scalar two-reg misc AdvSIMD scalar three same - Intial implementation of instruction class: Scalar Arithmetic - Initial clang changes to support arm v8 intrinsics. Note: no clang changes for scalar intrinsics function name mangling yet. - Comprehensive test cases for added instructions To verify auto codegen, encoding, decoding, diagnosis, intrinsics. llvm-svn: 187567
2013-08-01 17:20:35 +08:00
// Check that the assembler can handle the documented syntax for AArch64
//------------------------------------------------------------------------------
// Vector And
//------------------------------------------------------------------------------
and v0.8b, v1.8b, v2.8b
and v0.16b, v1.16b, v2.16b
// CHECK: and v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x22,0x0e]
// CHECK: and v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x22,0x4e]
//------------------------------------------------------------------------------
// Vector Orr
//------------------------------------------------------------------------------
orr v0.8b, v1.8b, v2.8b
orr v0.16b, v1.16b, v2.16b
// CHECK: orr v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xa2,0x0e]
// CHECK: orr v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xa2,0x4e]
//------------------------------------------------------------------------------
// Vector Eor
//------------------------------------------------------------------------------
eor v0.8b, v1.8b, v2.8b
eor v0.16b, v1.16b, v2.16b
// CHECK: eor v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x22,0x2e]
// CHECK: eor v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x22,0x6e]
//----------------------------------------------------------------------
// Vector Bitwise
//----------------------------------------------------------------------
bit v0.8b, v1.8b, v2.8b
bit v0.16b, v1.16b, v2.16b
bif v0.8b, v1.8b, v2.8b
bif v0.16b, v1.16b, v2.16b
bsl v0.8b, v1.8b, v2.8b
bsl v0.16b, v1.16b, v2.16b
orn v0.8b, v1.8b, v2.8b
orn v0.16b, v1.16b, v2.16b
bic v0.8b, v1.8b, v2.8b
bic v0.16b, v1.16b, v2.16b
// CHECK: bit v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xa2,0x2e]
// CHECK: bit v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xa2,0x6e]
// CHECK: bif v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xe2,0x2e]
// CHECK: bif v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xe2,0x6e]
// CHECK: bsl v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x62,0x2e]
// CHECK: bsl v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x62,0x6e]
// CHECK: orn v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0xe2,0x0e]
// CHECK: orn v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0xe2,0x4e]
// CHECK: bic v0.8b, v1.8b, v2.8b // encoding: [0x20,0x1c,0x62,0x0e]
// CHECK: bic v0.16b, v1.16b, v2.16b // encoding: [0x20,0x1c,0x62,0x4e]