2009-11-24 02:04:58 +08:00
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//===-- SelectionDAGBuilder.h - Selection-DAG building --------------------===//
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2008-09-04 00:12:24 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This implements routines for translating from LLVM IR into SelectionDAG IR.
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//
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//===----------------------------------------------------------------------===//
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2009-11-24 02:04:58 +08:00
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#ifndef SELECTIONDAGBUILDER_H
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#define SELECTIONDAGBUILDER_H
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2008-09-04 00:12:24 +08:00
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#include "llvm/Constants.h"
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2009-07-13 12:09:18 +08:00
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#include "llvm/CodeGen/SelectionDAG.h"
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2008-09-04 00:12:24 +08:00
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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2009-02-03 09:32:22 +08:00
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#include "llvm/CodeGen/ValueTypes.h"
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2008-09-04 00:12:24 +08:00
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#include "llvm/Support/CallSite.h"
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2009-07-12 04:10:48 +08:00
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#include "llvm/Support/ErrorHandling.h"
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2008-09-04 00:12:24 +08:00
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#include <vector>
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namespace llvm {
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class AliasAnalysis;
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class AllocaInst;
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class BasicBlock;
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class BitCastInst;
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class BranchInst;
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class CallInst;
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2010-08-27 07:35:15 +08:00
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class DbgValueInst;
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2008-09-04 00:12:24 +08:00
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class ExtractElementInst;
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class ExtractValueInst;
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class FCmpInst;
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class FPExtInst;
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class FPToSIInst;
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class FPToUIInst;
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class FPTruncInst;
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class Function;
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2009-11-24 01:16:22 +08:00
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class FunctionLoweringInfo;
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2008-09-04 00:12:24 +08:00
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class GetElementPtrInst;
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class GCFunctionInfo;
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class ICmpInst;
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class IntToPtrInst;
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2009-10-28 08:19:10 +08:00
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class IndirectBrInst;
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2008-09-04 00:12:24 +08:00
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class InvokeInst;
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class InsertElementInst;
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class InsertValueInst;
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class Instruction;
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class LoadInst;
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class MachineBasicBlock;
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class MachineInstr;
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class MachineRegisterInfo;
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2010-04-29 07:08:54 +08:00
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class MDNode;
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2008-09-04 00:12:24 +08:00
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class PHINode;
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class PtrToIntInst;
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class ReturnInst;
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class SDDbgValue;
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class SExtInst;
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class SelectInst;
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class ShuffleVectorInst;
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class SIToFPInst;
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class StoreInst;
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class SwitchInst;
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class TargetData;
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class TargetLibraryInfo;
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class TargetLowering;
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class TruncInst;
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class UIToFPInst;
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class UnreachableInst;
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class UnwindInst;
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class VAArgInst;
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class ZExtInst;
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//===----------------------------------------------------------------------===//
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2009-11-24 02:04:58 +08:00
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/// SelectionDAGBuilder - This is the common target-independent lowering
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2008-09-04 00:12:24 +08:00
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/// implementation that is parameterized by a TargetLowering object.
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///
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class SelectionDAGBuilder {
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2009-01-31 10:22:37 +08:00
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/// CurDebugLoc - current file + line number. Changes as we build the DAG.
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DebugLoc CurDebugLoc;
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2008-09-04 00:12:24 +08:00
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DenseMap<const Value*, SDValue> NodeMap;
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2010-06-02 03:59:01 +08:00
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/// UnusedArgNodeMap - Maps argument value for unused arguments. This is used
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/// to preserve debug information for incoming arguments.
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DenseMap<const Value*, SDValue> UnusedArgNodeMap;
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2008-09-04 00:12:24 +08:00
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2010-07-16 08:02:08 +08:00
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/// DanglingDebugInfo - Helper type for DanglingDebugInfoMap.
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class DanglingDebugInfo {
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const DbgValueInst* DI;
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DebugLoc dl;
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unsigned SDNodeOrder;
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public:
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DanglingDebugInfo() : DI(0), dl(DebugLoc()), SDNodeOrder(0) { }
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DanglingDebugInfo(const DbgValueInst *di, DebugLoc DL, unsigned SDNO) :
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DI(di), dl(DL), SDNodeOrder(SDNO) { }
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const DbgValueInst* getDI() { return DI; }
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2010-07-16 08:02:08 +08:00
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DebugLoc getdl() { return dl; }
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unsigned getSDNodeOrder() { return SDNodeOrder; }
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};
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/// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not
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/// yet seen the referent. We defer handling these until we do see it.
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DenseMap<const Value*, DanglingDebugInfo> DanglingDebugInfoMap;
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2009-12-24 08:37:38 +08:00
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public:
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2008-09-04 00:12:24 +08:00
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/// PendingLoads - Loads are not emitted to the program immediately. We bunch
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/// them up and then emit token factor nodes when possible. This allows us to
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/// get simple disambiguation between loads without worrying about alias
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/// analysis.
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SmallVector<SDValue, 8> PendingLoads;
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2009-12-24 08:37:38 +08:00
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private:
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2008-09-04 00:12:24 +08:00
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/// PendingExports - CopyToReg nodes that copy values to virtual registers
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/// for export to other blocks need to be emitted before any terminator
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/// instruction, but they have no other ordering requirements. We bunch them
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/// up and the emit a single tokenfactor for them just before terminator
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/// instructions.
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SmallVector<SDValue, 8> PendingExports;
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2009-12-19 07:32:53 +08:00
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/// SDNodeOrder - A unique monotonically increasing number used to order the
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/// SDNodes we create.
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unsigned SDNodeOrder;
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2008-09-04 00:12:24 +08:00
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/// Case - A struct to record the Value for a switch case, and the
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/// case's target basic block.
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struct Case {
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Constant* Low;
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Constant* High;
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MachineBasicBlock* BB;
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2011-07-30 06:25:21 +08:00
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uint32_t ExtraWeight;
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Case() : Low(0), High(0), BB(0), ExtraWeight(0) { }
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Case(Constant* low, Constant* high, MachineBasicBlock* bb,
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uint32_t extraweight) : Low(low), High(high), BB(bb),
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ExtraWeight(extraweight) { }
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2008-09-04 00:12:24 +08:00
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2009-11-07 15:50:34 +08:00
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APInt size() const {
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const APInt &rHigh = cast<ConstantInt>(High)->getValue();
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const APInt &rLow = cast<ConstantInt>(Low)->getValue();
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return (rHigh - rLow + 1ULL);
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}
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};
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struct CaseBits {
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uint64_t Mask;
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MachineBasicBlock* BB;
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unsigned Bits;
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CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits):
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Mask(mask), BB(bb), Bits(bits) { }
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};
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typedef std::vector<Case> CaseVector;
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typedef std::vector<CaseBits> CaseBitsVector;
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typedef CaseVector::iterator CaseItr;
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typedef std::pair<CaseItr, CaseItr> CaseRange;
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/// CaseRec - A struct with ctor used in lowering switches to a binary tree
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/// of conditional branches.
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struct CaseRec {
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CaseRec(MachineBasicBlock *bb, const Constant *lt, const Constant *ge,
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CaseRange r) :
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CaseBB(bb), LT(lt), GE(ge), Range(r) {}
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/// CaseBB - The MBB in which to emit the compare and branch
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MachineBasicBlock *CaseBB;
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/// LT, GE - If nonzero, we know the current case value must be less-than or
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/// greater-than-or-equal-to these Constants.
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const Constant *LT;
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const Constant *GE;
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/// Range - A pair of iterators representing the range of case values to be
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/// processed at this point in the binary search tree.
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CaseRange Range;
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};
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typedef std::vector<CaseRec> CaseRecVector;
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/// The comparison function for sorting the switch case values in the vector.
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/// WARNING: Case ranges should be disjoint!
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struct CaseCmp {
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bool operator()(const Case &C1, const Case &C2) {
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assert(isa<ConstantInt>(C1.Low) && isa<ConstantInt>(C2.High));
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const ConstantInt* CI1 = cast<const ConstantInt>(C1.Low);
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const ConstantInt* CI2 = cast<const ConstantInt>(C2.High);
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return CI1->getValue().slt(CI2->getValue());
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}
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};
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struct CaseBitsCmp {
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bool operator()(const CaseBits &C1, const CaseBits &C2) {
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return C1.Bits > C2.Bits;
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}
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};
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2010-01-02 07:37:34 +08:00
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size_t Clusterify(CaseVector &Cases, const SwitchInst &SI);
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2008-12-24 06:25:27 +08:00
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2009-11-24 02:04:58 +08:00
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/// CaseBlock - This structure is used to communicate between
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/// SelectionDAGBuilder and SDISel for the code generation of additional basic
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/// blocks needed by multi-case switch statements.
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struct CaseBlock {
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CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
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const Value *cmpmiddle,
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MachineBasicBlock *truebb, MachineBasicBlock *falsebb,
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MachineBasicBlock *me,
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uint32_t trueweight = 0, uint32_t falseweight = 0)
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: CC(cc), CmpLHS(cmplhs), CmpMHS(cmpmiddle), CmpRHS(cmprhs),
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TrueBB(truebb), FalseBB(falsebb), ThisBB(me),
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TrueWeight(trueweight), FalseWeight(falseweight) { }
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2008-09-04 00:12:24 +08:00
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// CC - the condition code to use for the case block's setcc node
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ISD::CondCode CC;
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2011-07-30 06:25:21 +08:00
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2008-09-04 00:12:24 +08:00
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// CmpLHS/CmpRHS/CmpMHS - The LHS/MHS/RHS of the comparison to emit.
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// Emit by default LHS op RHS. MHS is used for range comparisons:
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// If MHS is not null: (LHS <= MHS) and (MHS <= RHS).
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2010-04-15 09:51:59 +08:00
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const Value *CmpLHS, *CmpMHS, *CmpRHS;
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2008-09-04 00:12:24 +08:00
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// TrueBB/FalseBB - the block to branch to if the setcc is true/false.
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MachineBasicBlock *TrueBB, *FalseBB;
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2011-07-30 06:25:21 +08:00
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2008-09-04 00:12:24 +08:00
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// ThisBB - the block into which to emit the code for the setcc and branches
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MachineBasicBlock *ThisBB;
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2011-07-30 06:25:21 +08:00
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// TrueWeight/FalseWeight - branch weights.
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uint32_t TrueWeight, FalseWeight;
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2008-09-04 00:12:24 +08:00
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};
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2011-07-30 06:25:21 +08:00
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2008-09-04 00:12:24 +08:00
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struct JumpTable {
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JumpTable(unsigned R, unsigned J, MachineBasicBlock *M,
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MachineBasicBlock *D): Reg(R), JTI(J), MBB(M), Default(D) {}
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/// Reg - the virtual register containing the index of the jump table entry
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//. to jump to.
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unsigned Reg;
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/// JTI - the JumpTableIndex for this jump table in the function.
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unsigned JTI;
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/// MBB - the MBB into which to emit the code for the indirect jump.
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MachineBasicBlock *MBB;
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/// Default - the MBB of the default bb, which is a successor of the range
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/// check MBB. This is when updating PHI nodes in successors.
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MachineBasicBlock *Default;
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};
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struct JumpTableHeader {
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JumpTableHeader(APInt F, APInt L, const Value *SV, MachineBasicBlock *H,
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bool E = false):
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First(F), Last(L), SValue(SV), HeaderBB(H), Emitted(E) {}
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APInt First;
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APInt Last;
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2010-04-15 09:51:59 +08:00
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const Value *SValue;
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2008-09-04 00:12:24 +08:00
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MachineBasicBlock *HeaderBB;
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bool Emitted;
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};
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typedef std::pair<JumpTableHeader, JumpTable> JumpTableBlock;
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struct BitTestCase {
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BitTestCase(uint64_t M, MachineBasicBlock* T, MachineBasicBlock* Tr):
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Mask(M), ThisBB(T), TargetBB(Tr) { }
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uint64_t Mask;
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2010-01-02 07:37:34 +08:00
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MachineBasicBlock *ThisBB;
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MachineBasicBlock *TargetBB;
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2008-09-04 00:12:24 +08:00
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};
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typedef SmallVector<BitTestCase, 3> BitTestInfo;
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struct BitTestBlock {
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2010-04-15 09:51:59 +08:00
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BitTestBlock(APInt F, APInt R, const Value* SV,
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unsigned Rg, EVT RgVT, bool E,
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2008-09-04 00:12:24 +08:00
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MachineBasicBlock* P, MachineBasicBlock* D,
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const BitTestInfo& C):
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First(F), Range(R), SValue(SV), Reg(Rg), RegVT(RgVT), Emitted(E),
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2008-09-04 00:12:24 +08:00
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Parent(P), Default(D), Cases(C) { }
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2008-12-24 06:25:27 +08:00
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APInt First;
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APInt Range;
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2010-04-15 09:51:59 +08:00
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const Value *SValue;
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2008-09-04 00:12:24 +08:00
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unsigned Reg;
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2011-01-06 09:02:44 +08:00
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EVT RegVT;
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2008-09-04 00:12:24 +08:00
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bool Emitted;
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MachineBasicBlock *Parent;
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MachineBasicBlock *Default;
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BitTestInfo Cases;
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};
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public:
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// TLI - This is information that describes the available target features we
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// need for lowering. This indicates when operations are unavailable,
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// implemented with a libcall, etc.
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2010-04-20 03:05:59 +08:00
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const TargetMachine &TM;
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2010-04-17 23:26:15 +08:00
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const TargetLowering &TLI;
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2008-09-04 00:12:24 +08:00
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SelectionDAG &DAG;
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const TargetData *TD;
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AliasAnalysis *AA;
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2011-12-09 06:15:21 +08:00
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const TargetLibraryInfo *LibInfo;
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2008-09-04 00:12:24 +08:00
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/// SwitchCases - Vector of CaseBlock structures used to communicate
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/// SwitchInst code generation information.
|
|
|
|
std::vector<CaseBlock> SwitchCases;
|
|
|
|
/// JTCases - Vector of JumpTable structures used to communicate
|
|
|
|
/// SwitchInst code generation information.
|
|
|
|
std::vector<JumpTableBlock> JTCases;
|
|
|
|
/// BitTestCases - Vector of BitTestBlock structures used to communicate
|
|
|
|
/// SwitchInst code generation information.
|
|
|
|
std::vector<BitTestBlock> BitTestCases;
|
2009-09-19 05:02:19 +08:00
|
|
|
|
2008-09-04 00:12:24 +08:00
|
|
|
// Emit PHI-node-operand constants only once even if used by multiple
|
|
|
|
// PHI nodes.
|
2010-04-15 09:51:59 +08:00
|
|
|
DenseMap<const Constant *, unsigned> ConstantsOut;
|
2008-09-04 00:12:24 +08:00
|
|
|
|
|
|
|
/// FuncInfo - Information about the function as a whole.
|
|
|
|
///
|
|
|
|
FunctionLoweringInfo &FuncInfo;
|
2009-02-20 05:12:54 +08:00
|
|
|
|
2009-04-29 08:15:41 +08:00
|
|
|
/// OptLevel - What optimization level we're generating code for.
|
2009-02-20 05:12:54 +08:00
|
|
|
///
|
2009-04-30 07:29:43 +08:00
|
|
|
CodeGenOpt::Level OptLevel;
|
2008-09-04 00:12:24 +08:00
|
|
|
|
|
|
|
/// GFI - Garbage collection metadata for the function.
|
|
|
|
GCFunctionInfo *GFI;
|
|
|
|
|
2011-10-06 06:24:35 +08:00
|
|
|
/// LPadToCallSiteMap - Map a landing pad to the call site indexes.
|
|
|
|
DenseMap<MachineBasicBlock*, SmallVector<unsigned, 4> > LPadToCallSiteMap;
|
2011-10-05 06:00:35 +08:00
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
/// HasTailCall - This is set to true if a call in the current
|
|
|
|
/// block has been translated as a tail call. In this case,
|
|
|
|
/// no subsequent DAG nodes should be created.
|
|
|
|
///
|
|
|
|
bool HasTailCall;
|
|
|
|
|
2009-07-13 12:09:18 +08:00
|
|
|
LLVMContext *Context;
|
|
|
|
|
2010-04-20 03:05:59 +08:00
|
|
|
SelectionDAGBuilder(SelectionDAG &dag, FunctionLoweringInfo &funcinfo,
|
2009-11-24 02:04:58 +08:00
|
|
|
CodeGenOpt::Level ol)
|
2010-04-20 03:05:59 +08:00
|
|
|
: SDNodeOrder(0), TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()),
|
|
|
|
DAG(dag), FuncInfo(funcinfo), OptLevel(ol),
|
2010-04-03 04:17:23 +08:00
|
|
|
HasTailCall(false), Context(dag.getContext()) {
|
2008-09-04 00:12:24 +08:00
|
|
|
}
|
|
|
|
|
2011-12-09 06:15:21 +08:00
|
|
|
void init(GCFunctionInfo *gfi, AliasAnalysis &aa,
|
|
|
|
const TargetLibraryInfo *li);
|
2008-09-04 00:12:24 +08:00
|
|
|
|
2010-04-15 02:24:06 +08:00
|
|
|
/// clear - Clear out the current SelectionDAG and the associated
|
2009-11-24 02:04:58 +08:00
|
|
|
/// state and prepare this SelectionDAGBuilder object to be used
|
2008-09-04 00:12:24 +08:00
|
|
|
/// for a new block. This doesn't clear out information about
|
|
|
|
/// additional blocks that are needed to complete switch lowering
|
|
|
|
/// or PHI node updating; that information is cleared out as it is
|
|
|
|
/// consumed.
|
|
|
|
void clear();
|
|
|
|
|
2011-05-24 01:44:13 +08:00
|
|
|
/// clearDanglingDebugInfo - Clear the dangling debug information
|
|
|
|
/// map. This function is seperated from the clear so that debug
|
|
|
|
/// information that is dangling in a basic block can be properly
|
|
|
|
/// resolved in a different basic block. This allows the
|
|
|
|
/// SelectionDAG to resolve dangling debug information attached
|
|
|
|
/// to PHI nodes.
|
|
|
|
void clearDanglingDebugInfo();
|
|
|
|
|
2008-09-04 00:12:24 +08:00
|
|
|
/// getRoot - Return the current virtual root of the Selection DAG,
|
|
|
|
/// flushing any PendingLoad items. This must be done before emitting
|
|
|
|
/// a store or any other node that may need to be ordered after any
|
|
|
|
/// prior load instructions.
|
|
|
|
///
|
|
|
|
SDValue getRoot();
|
|
|
|
|
|
|
|
/// getControlRoot - Similar to getRoot, but instead of flushing all the
|
|
|
|
/// PendingLoad items, flush all the PendingExports items. It is necessary
|
|
|
|
/// to do this before emitting a terminator instruction.
|
|
|
|
///
|
|
|
|
SDValue getControlRoot();
|
|
|
|
|
2009-01-31 10:22:37 +08:00
|
|
|
DebugLoc getCurDebugLoc() const { return CurDebugLoc; }
|
2011-02-22 07:21:26 +08:00
|
|
|
|
2009-12-22 10:10:19 +08:00
|
|
|
unsigned getSDNodeOrder() const { return SDNodeOrder; }
|
|
|
|
|
2010-04-15 09:51:59 +08:00
|
|
|
void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
|
2008-09-04 00:12:24 +08:00
|
|
|
|
2010-01-29 05:51:40 +08:00
|
|
|
/// AssignOrderingToNode - Assign an ordering to the node. The order is gotten
|
|
|
|
/// from how the code appeared in the source. The ordering is used by the
|
|
|
|
/// scheduler to effectively turn off scheduling.
|
|
|
|
void AssignOrderingToNode(const SDNode *Node);
|
|
|
|
|
2010-04-15 09:51:59 +08:00
|
|
|
void visit(const Instruction &I);
|
2008-09-04 00:12:24 +08:00
|
|
|
|
2010-04-15 09:51:59 +08:00
|
|
|
void visit(unsigned Opcode, const User &I);
|
2008-09-04 00:12:24 +08:00
|
|
|
|
2010-07-16 08:02:08 +08:00
|
|
|
// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
|
|
|
|
// generate the debug data structures now that we've seen its definition.
|
|
|
|
void resolveDanglingDebugInfo(const Value *V, SDValue Val);
|
2008-09-04 00:12:24 +08:00
|
|
|
SDValue getValue(const Value *V);
|
2010-07-01 09:59:43 +08:00
|
|
|
SDValue getNonRegisterValue(const Value *V);
|
|
|
|
SDValue getValueImpl(const Value *V);
|
2008-09-04 00:12:24 +08:00
|
|
|
|
|
|
|
void setValue(const Value *V, SDValue NewN) {
|
|
|
|
SDValue &N = NodeMap[V];
|
|
|
|
assert(N.getNode() == 0 && "Already set a value for this node!");
|
|
|
|
N = NewN;
|
|
|
|
}
|
|
|
|
|
2010-06-02 03:59:01 +08:00
|
|
|
void setUnusedArgValue(const Value *V, SDValue NewN) {
|
|
|
|
SDValue &N = UnusedArgNodeMap[V];
|
|
|
|
assert(N.getNode() == 0 && "Already set a value for this node!");
|
|
|
|
N = NewN;
|
|
|
|
}
|
2008-09-04 00:12:24 +08:00
|
|
|
|
2010-04-15 09:51:59 +08:00
|
|
|
void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB,
|
2008-09-04 00:12:24 +08:00
|
|
|
MachineBasicBlock *FBB, MachineBasicBlock *CurBB,
|
2010-04-20 06:41:47 +08:00
|
|
|
MachineBasicBlock *SwitchBB, unsigned Opc);
|
2010-04-15 09:51:59 +08:00
|
|
|
void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB,
|
2008-10-18 05:16:08 +08:00
|
|
|
MachineBasicBlock *FBB,
|
2010-04-20 06:41:47 +08:00
|
|
|
MachineBasicBlock *CurBB,
|
|
|
|
MachineBasicBlock *SwitchBB);
|
2008-09-04 00:12:24 +08:00
|
|
|
bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases);
|
2010-04-15 09:51:59 +08:00
|
|
|
bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB);
|
|
|
|
void CopyToExportRegsIfNeeded(const Value *V);
|
|
|
|
void ExportFromCurrentBlock(const Value *V);
|
|
|
|
void LowerCallTo(ImmutableCallSite CS, SDValue Callee, bool IsTailCall,
|
2008-09-04 00:12:24 +08:00
|
|
|
MachineBasicBlock *LandingPad = NULL);
|
|
|
|
|
2010-10-01 03:44:31 +08:00
|
|
|
/// UpdateSplitBlock - When an MBB was split during scheduling, update the
|
|
|
|
/// references that ned to refer to the last resulting block.
|
|
|
|
void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last);
|
|
|
|
|
2008-09-04 00:12:24 +08:00
|
|
|
private:
|
|
|
|
// Terminator instructions.
|
2010-04-15 09:51:59 +08:00
|
|
|
void visitRet(const ReturnInst &I);
|
|
|
|
void visitBr(const BranchInst &I);
|
|
|
|
void visitSwitch(const SwitchInst &I);
|
|
|
|
void visitIndirectBr(const IndirectBrInst &I);
|
2010-07-16 07:42:21 +08:00
|
|
|
void visitUnreachable(const UnreachableInst &I) { /* noop */ }
|
2008-09-04 00:12:24 +08:00
|
|
|
|
|
|
|
// Helpers for visitSwitch
|
|
|
|
bool handleSmallSwitchRange(CaseRec& CR,
|
|
|
|
CaseRecVector& WorkList,
|
2010-04-15 09:51:59 +08:00
|
|
|
const Value* SV,
|
2010-04-20 06:41:47 +08:00
|
|
|
MachineBasicBlock* Default,
|
|
|
|
MachineBasicBlock *SwitchBB);
|
2008-09-04 00:12:24 +08:00
|
|
|
bool handleJTSwitchCase(CaseRec& CR,
|
|
|
|
CaseRecVector& WorkList,
|
2010-04-15 09:51:59 +08:00
|
|
|
const Value* SV,
|
2010-04-20 06:41:47 +08:00
|
|
|
MachineBasicBlock* Default,
|
|
|
|
MachineBasicBlock *SwitchBB);
|
2008-09-04 00:12:24 +08:00
|
|
|
bool handleBTSplitSwitchCase(CaseRec& CR,
|
|
|
|
CaseRecVector& WorkList,
|
2010-04-15 09:51:59 +08:00
|
|
|
const Value* SV,
|
2010-04-20 06:41:47 +08:00
|
|
|
MachineBasicBlock* Default,
|
|
|
|
MachineBasicBlock *SwitchBB);
|
2008-09-04 00:12:24 +08:00
|
|
|
bool handleBitTestsSwitchCase(CaseRec& CR,
|
|
|
|
CaseRecVector& WorkList,
|
2010-04-15 09:51:59 +08:00
|
|
|
const Value* SV,
|
2010-04-20 06:41:47 +08:00
|
|
|
MachineBasicBlock* Default,
|
|
|
|
MachineBasicBlock *SwitchBB);
|
2011-06-17 04:22:37 +08:00
|
|
|
|
2011-12-21 04:03:10 +08:00
|
|
|
uint32_t getEdgeWeight(const MachineBasicBlock *Src,
|
|
|
|
const MachineBasicBlock *Dst) const;
|
2011-07-30 06:25:21 +08:00
|
|
|
void addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst,
|
|
|
|
uint32_t Weight = 0);
|
2008-09-04 00:12:24 +08:00
|
|
|
public:
|
2010-04-20 06:41:47 +08:00
|
|
|
void visitSwitchCase(CaseBlock &CB,
|
|
|
|
MachineBasicBlock *SwitchBB);
|
|
|
|
void visitBitTestHeader(BitTestBlock &B, MachineBasicBlock *SwitchBB);
|
2011-01-06 09:02:44 +08:00
|
|
|
void visitBitTestCase(BitTestBlock &BB,
|
|
|
|
MachineBasicBlock* NextMBB,
|
2008-09-04 00:12:24 +08:00
|
|
|
unsigned Reg,
|
2010-04-20 06:41:47 +08:00
|
|
|
BitTestCase &B,
|
|
|
|
MachineBasicBlock *SwitchBB);
|
2008-09-04 00:12:24 +08:00
|
|
|
void visitJumpTable(JumpTable &JT);
|
2010-04-20 06:41:47 +08:00
|
|
|
void visitJumpTableHeader(JumpTable &JT, JumpTableHeader &JTH,
|
|
|
|
MachineBasicBlock *SwitchBB);
|
2008-09-04 00:12:24 +08:00
|
|
|
|
|
|
|
private:
|
|
|
|
// These all get lowered before this pass.
|
2010-04-15 09:51:59 +08:00
|
|
|
void visitInvoke(const InvokeInst &I);
|
2011-07-31 14:30:59 +08:00
|
|
|
void visitResume(const ResumeInst &I);
|
2010-04-15 09:51:59 +08:00
|
|
|
void visitUnwind(const UnwindInst &I);
|
|
|
|
|
|
|
|
void visitBinary(const User &I, unsigned OpCode);
|
|
|
|
void visitShift(const User &I, unsigned Opcode);
|
|
|
|
void visitAdd(const User &I) { visitBinary(I, ISD::ADD); }
|
|
|
|
void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); }
|
|
|
|
void visitSub(const User &I) { visitBinary(I, ISD::SUB); }
|
|
|
|
void visitFSub(const User &I);
|
|
|
|
void visitMul(const User &I) { visitBinary(I, ISD::MUL); }
|
|
|
|
void visitFMul(const User &I) { visitBinary(I, ISD::FMUL); }
|
|
|
|
void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
|
|
|
|
void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
|
|
|
|
void visitFRem(const User &I) { visitBinary(I, ISD::FREM); }
|
|
|
|
void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); }
|
Emit a more efficient magic number multiplication for exact sdivs.
We have to do this in DAGBuilder instead of DAGCombiner, because the exact bit is lost after building.
struct foo { char x[24]; };
long bar(struct foo *a, struct foo *b) { return a-b; }
is now compiled into
movl 4(%esp), %eax
subl 8(%esp), %eax
sarl $3, %eax
imull $-1431655765, %eax, %eax
instead of
movl 4(%esp), %eax
subl 8(%esp), %eax
movl $715827883, %ecx
imull %ecx
movl %edx, %eax
shrl $31, %eax
sarl $2, %edx
addl %eax, %edx
movl %edx, %eax
llvm-svn: 134695
2011-07-08 18:31:30 +08:00
|
|
|
void visitSDiv(const User &I);
|
2010-04-15 09:51:59 +08:00
|
|
|
void visitFDiv(const User &I) { visitBinary(I, ISD::FDIV); }
|
|
|
|
void visitAnd (const User &I) { visitBinary(I, ISD::AND); }
|
|
|
|
void visitOr (const User &I) { visitBinary(I, ISD::OR); }
|
|
|
|
void visitXor (const User &I) { visitBinary(I, ISD::XOR); }
|
|
|
|
void visitShl (const User &I) { visitShift(I, ISD::SHL); }
|
|
|
|
void visitLShr(const User &I) { visitShift(I, ISD::SRL); }
|
|
|
|
void visitAShr(const User &I) { visitShift(I, ISD::SRA); }
|
|
|
|
void visitICmp(const User &I);
|
|
|
|
void visitFCmp(const User &I);
|
2008-09-04 00:12:24 +08:00
|
|
|
// Visit the conversion instructions
|
2010-04-15 09:51:59 +08:00
|
|
|
void visitTrunc(const User &I);
|
|
|
|
void visitZExt(const User &I);
|
|
|
|
void visitSExt(const User &I);
|
|
|
|
void visitFPTrunc(const User &I);
|
|
|
|
void visitFPExt(const User &I);
|
|
|
|
void visitFPToUI(const User &I);
|
|
|
|
void visitFPToSI(const User &I);
|
|
|
|
void visitUIToFP(const User &I);
|
|
|
|
void visitSIToFP(const User &I);
|
|
|
|
void visitPtrToInt(const User &I);
|
|
|
|
void visitIntToPtr(const User &I);
|
|
|
|
void visitBitCast(const User &I);
|
|
|
|
|
|
|
|
void visitExtractElement(const User &I);
|
|
|
|
void visitInsertElement(const User &I);
|
|
|
|
void visitShuffleVector(const User &I);
|
|
|
|
|
|
|
|
void visitExtractValue(const ExtractValueInst &I);
|
|
|
|
void visitInsertValue(const InsertValueInst &I);
|
2011-08-13 04:24:12 +08:00
|
|
|
void visitLandingPad(const LandingPadInst &I);
|
2010-04-15 09:51:59 +08:00
|
|
|
|
|
|
|
void visitGetElementPtr(const User &I);
|
|
|
|
void visitSelect(const User &I);
|
|
|
|
|
|
|
|
void visitAlloca(const AllocaInst &I);
|
|
|
|
void visitLoad(const LoadInst &I);
|
|
|
|
void visitStore(const StoreInst &I);
|
2011-07-29 05:48:00 +08:00
|
|
|
void visitAtomicCmpXchg(const AtomicCmpXchgInst &I);
|
|
|
|
void visitAtomicRMW(const AtomicRMWInst &I);
|
2011-07-26 07:16:38 +08:00
|
|
|
void visitFence(const FenceInst &I);
|
2010-04-20 23:00:41 +08:00
|
|
|
void visitPHI(const PHINode &I);
|
2010-04-15 09:51:59 +08:00
|
|
|
void visitCall(const CallInst &I);
|
|
|
|
bool visitMemCmpCall(const CallInst &I);
|
2011-08-25 04:50:09 +08:00
|
|
|
void visitAtomicLoad(const LoadInst &I);
|
|
|
|
void visitAtomicStore(const StoreInst &I);
|
|
|
|
|
2010-04-15 09:51:59 +08:00
|
|
|
void visitInlineAsm(ImmutableCallSite CS);
|
|
|
|
const char *visitIntrinsicCall(const CallInst &I, unsigned Intrinsic);
|
|
|
|
void visitTargetIntrinsic(const CallInst &I, unsigned Intrinsic);
|
|
|
|
|
|
|
|
void visitPow(const CallInst &I);
|
|
|
|
void visitExp2(const CallInst &I);
|
|
|
|
void visitExp(const CallInst &I);
|
|
|
|
void visitLog(const CallInst &I);
|
|
|
|
void visitLog2(const CallInst &I);
|
|
|
|
void visitLog10(const CallInst &I);
|
|
|
|
|
|
|
|
void visitVAStart(const CallInst &I);
|
|
|
|
void visitVAArg(const VAArgInst &I);
|
|
|
|
void visitVAEnd(const CallInst &I);
|
|
|
|
void visitVACopy(const CallInst &I);
|
|
|
|
|
|
|
|
void visitUserOp1(const Instruction &I) {
|
2009-07-15 00:55:14 +08:00
|
|
|
llvm_unreachable("UserOp1 should not exist at instruction selection time!");
|
2008-09-04 00:12:24 +08:00
|
|
|
}
|
2010-04-15 09:51:59 +08:00
|
|
|
void visitUserOp2(const Instruction &I) {
|
2009-07-15 00:55:14 +08:00
|
|
|
llvm_unreachable("UserOp2 should not exist at instruction selection time!");
|
2008-09-04 00:12:24 +08:00
|
|
|
}
|
|
|
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2010-04-15 09:51:59 +08:00
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const char *implVisitAluOverflow(const CallInst &I, ISD::NodeType Op);
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2010-04-23 04:55:53 +08:00
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void HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB);
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2010-04-29 07:08:54 +08:00
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2010-08-26 04:41:24 +08:00
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/// EmitFuncArgumentDbgValue - If V is an function argument then create
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/// corresponding DBG_VALUE machine instruction for it now. At the end of
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/// instruction selection, they will be inserted to the entry BB.
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2010-08-26 04:39:26 +08:00
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bool EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable,
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2010-08-31 14:12:08 +08:00
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int64_t Offset, const SDValue &N);
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2008-09-04 00:12:24 +08:00
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};
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} // end namespace llvm
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#endif
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