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llvm-project/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.dcache.wb.ll

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AMDGPU: Add s_dcache_* instructions llvm-svn: 248533
2015-09-25 03:52:27 +08:00
; RUN: llc -march=amdgcn -mcpu=fiji -show-mc-encoding < %s | FileCheck -check-prefix=VI %s
declare void @llvm.amdgcn.s.dcache.wb() #0
AMDGPU: Implement AnalyzeBranch Original patch by Tom Stellard llvm-svn: 270295
2016-05-21 08:29:27 +08:00
declare void @llvm.amdgcn.s.waitcnt(i32) #0
AMDGPU: Add s_dcache_* instructions llvm-svn: 248533
2015-09-25 03:52:27 +08:00
; VI-LABEL: {{^}}test_s_dcache_wb:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; VI-NEXT: ; %bb.0:
AMDGPU: Add s_dcache_* instructions llvm-svn: 248533
2015-09-25 03:52:27 +08:00
; VI-NEXT: s_dcache_wb ; encoding: [0x00,0x00,0x84,0xc0,0x00,0x00,0x00,0x00]
; VI-NEXT: s_endpgm
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
2017-03-22 05:39:51 +08:00
define amdgpu_kernel void @test_s_dcache_wb() #0 {
AMDGPU: Add s_dcache_* instructions llvm-svn: 248533
2015-09-25 03:52:27 +08:00
call void @llvm.amdgcn.s.dcache.wb()
ret void
}
; VI-LABEL: {{^}}test_s_dcache_wb_insert_wait:
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; VI-NEXT: ; %bb.0:
AMDGPU: Add s_dcache_* instructions llvm-svn: 248533
2015-09-25 03:52:27 +08:00
; VI-NEXT: s_dcache_wb
AMDGPU: Implement AnalyzeBranch Original patch by Tom Stellard llvm-svn: 270295
2016-05-21 08:29:27 +08:00
; VI: s_waitcnt lgkmcnt(0) ; encoding
AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
2017-03-22 05:39:51 +08:00
define amdgpu_kernel void @test_s_dcache_wb_insert_wait() #0 {
AMDGPU: Add s_dcache_* instructions llvm-svn: 248533
2015-09-25 03:52:27 +08:00
call void @llvm.amdgcn.s.dcache.wb()
[AMDGPU] Turn on the new waitcnt insertion pass. Adjust tests. -enable-si-insert-waitcnts=1 becomes the default -enable-si-insert-waitcnts=0 to use old pass Differential Revision: https://reviews.llvm.org/D33730 llvm-svn: 304551
2017-06-02 22:19:25 +08:00
call void @llvm.amdgcn.s.waitcnt(i32 127)
AMDGPU: Add s_dcache_* instructions llvm-svn: 248533
2015-09-25 03:52:27 +08:00
br label %end
end:
store volatile i32 3, i32 addrspace(1)* undef
ret void
}
attributes #0 = { nounwind }