2016-05-02 23:18:13 +08:00
|
|
|
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
|
2002-05-06 13:35:20 +08:00
|
|
|
; This test makes sure that div instructions are properly eliminated.
|
|
|
|
|
|
2011-05-01 02:15:53 +08:00
|
|
|
; RUN: opt < %s -instcombine -S | FileCheck %s
|
2002-05-06 13:35:20 +08:00
|
|
|
|
2008-03-18 11:45:45 +08:00
|
|
|
define i32 @test1(i32 %A) {
|
2013-07-14 09:42:54 +08:00
|
|
|
; CHECK-LABEL: @test1(
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-NEXT: ret i32 %A
|
|
|
|
|
;
|
|
|
|
|
%B = sdiv i32 %A, 1 ; <i32> [#uses=1]
|
|
|
|
|
ret i32 %B
|
2003-02-19 03:16:45 +08:00
|
|
|
}
|
2003-02-19 03:28:47 +08:00
|
|
|
|
2008-03-18 11:45:45 +08:00
|
|
|
define i32 @test2(i32 %A) {
|
|
|
|
|
; => Shift
|
2013-07-14 09:42:54 +08:00
|
|
|
; CHECK-LABEL: @test2(
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-NEXT: [[B:%.*]] = lshr i32 %A, 3
|
|
|
|
|
; CHECK-NEXT: ret i32 [[B]]
|
|
|
|
|
;
|
|
|
|
|
%B = udiv i32 %A, 8 ; <i32> [#uses=1]
|
|
|
|
|
ret i32 %B
|
2003-02-19 03:28:47 +08:00
|
|
|
}
|
|
|
|
|
|
2008-03-18 11:45:45 +08:00
|
|
|
define i32 @test3(i32 %A) {
|
|
|
|
|
; => 0, don't need to keep traps
|
2013-07-14 09:42:54 +08:00
|
|
|
; CHECK-LABEL: @test3(
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-NEXT: ret i32 0
|
|
|
|
|
;
|
|
|
|
|
%B = sdiv i32 0, %A ; <i32> [#uses=1]
|
|
|
|
|
ret i32 %B
|
2003-02-19 03:28:47 +08:00
|
|
|
}
|
2004-04-26 22:01:47 +08:00
|
|
|
|
2008-03-18 11:45:45 +08:00
|
|
|
define i32 @test4(i32 %A) {
|
|
|
|
|
; 0-A
|
2013-07-14 09:42:54 +08:00
|
|
|
; CHECK-LABEL: @test4(
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-NEXT: [[B:%.*]] = sub i32 0, %A
|
|
|
|
|
; CHECK-NEXT: ret i32 [[B]]
|
|
|
|
|
;
|
|
|
|
|
%B = sdiv i32 %A, -1 ; <i32> [#uses=1]
|
|
|
|
|
ret i32 %B
|
2004-04-26 22:01:47 +08:00
|
|
|
}
|
2004-09-29 02:21:01 +08:00
|
|
|
|
2008-03-18 11:45:45 +08:00
|
|
|
define i32 @test5(i32 %A) {
|
2013-07-14 09:42:54 +08:00
|
|
|
; CHECK-LABEL: @test5(
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-NEXT: ret i32 0
|
|
|
|
|
;
|
|
|
|
|
%B = udiv i32 %A, -16 ; <i32> [#uses=1]
|
|
|
|
|
%C = udiv i32 %B, -4 ; <i32> [#uses=1]
|
|
|
|
|
ret i32 %C
|
2004-09-29 02:21:01 +08:00
|
|
|
}
|
2004-09-30 01:37:07 +08:00
|
|
|
|
2008-03-18 11:45:45 +08:00
|
|
|
define i1 @test6(i32 %A) {
|
2013-07-14 09:42:54 +08:00
|
|
|
; CHECK-LABEL: @test6(
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 %A, 123
|
|
|
|
|
; CHECK-NEXT: ret i1 [[TMP1]]
|
|
|
|
|
;
|
|
|
|
|
%B = udiv i32 %A, 123 ; <i32> [#uses=1]
|
|
|
|
|
; A < 123
|
|
|
|
|
%C = icmp eq i32 %B, 0 ; <i1> [#uses=1]
|
|
|
|
|
ret i1 %C
|
2008-03-18 11:45:45 +08:00
|
|
|
}
|
2004-09-30 01:37:07 +08:00
|
|
|
|
2008-03-18 11:45:45 +08:00
|
|
|
define i1 @test7(i32 %A) {
|
2013-07-14 09:42:54 +08:00
|
|
|
; CHECK-LABEL: @test7(
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-NEXT: [[A_OFF:%.*]] = add i32 %A, -20
|
|
|
|
|
; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[A_OFF]], 10
|
|
|
|
|
; CHECK-NEXT: ret i1 [[TMP1]]
|
|
|
|
|
;
|
|
|
|
|
%B = udiv i32 %A, 10 ; <i32> [#uses=1]
|
|
|
|
|
; A >= 20 && A < 30
|
|
|
|
|
%C = icmp eq i32 %B, 2 ; <i1> [#uses=1]
|
|
|
|
|
ret i1 %C
|
2004-09-30 01:37:07 +08:00
|
|
|
}
|
|
|
|
|
|
2008-03-18 11:45:45 +08:00
|
|
|
define i1 @test8(i8 %A) {
|
2013-07-14 09:42:54 +08:00
|
|
|
; CHECK-LABEL: @test8(
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-NEXT: [[C:%.*]] = icmp ugt i8 %A, -11
|
|
|
|
|
; CHECK-NEXT: ret i1 [[C]]
|
|
|
|
|
;
|
|
|
|
|
%B = udiv i8 %A, 123 ; <i8> [#uses=1]
|
|
|
|
|
; A >= 246
|
|
|
|
|
%C = icmp eq i8 %B, 2 ; <i1> [#uses=1]
|
|
|
|
|
ret i1 %C
|
2008-03-18 11:45:45 +08:00
|
|
|
}
|
2004-09-30 01:37:07 +08:00
|
|
|
|
2008-03-18 11:45:45 +08:00
|
|
|
define i1 @test9(i8 %A) {
|
2013-07-14 09:42:54 +08:00
|
|
|
; CHECK-LABEL: @test9(
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-NEXT: [[C:%.*]] = icmp ult i8 %A, -10
|
|
|
|
|
; CHECK-NEXT: ret i1 [[C]]
|
|
|
|
|
;
|
|
|
|
|
%B = udiv i8 %A, 123 ; <i8> [#uses=1]
|
|
|
|
|
; A < 246
|
|
|
|
|
%C = icmp ne i8 %B, 2 ; <i1> [#uses=1]
|
|
|
|
|
ret i1 %C
|
2008-03-18 11:45:45 +08:00
|
|
|
}
|
2004-09-30 01:37:07 +08:00
|
|
|
|
2008-03-18 11:45:45 +08:00
|
|
|
define i32 @test10(i32 %X, i1 %C) {
|
2013-07-14 09:42:54 +08:00
|
|
|
; CHECK-LABEL: @test10(
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-NEXT: [[R_V:%.*]] = select i1 %C, i32 6, i32 3
|
|
|
|
|
; CHECK-NEXT: [[R:%.*]] = lshr i32 %X, [[R:%.*]].v
|
|
|
|
|
; CHECK-NEXT: ret i32 [[R]]
|
|
|
|
|
;
|
|
|
|
|
%V = select i1 %C, i32 64, i32 8 ; <i32> [#uses=1]
|
|
|
|
|
%R = udiv i32 %X, %V ; <i32> [#uses=1]
|
|
|
|
|
ret i32 %R
|
2004-12-13 05:40:22 +08:00
|
|
|
}
|
|
|
|
|
|
2008-03-18 11:45:45 +08:00
|
|
|
define i32 @test11(i32 %X, i1 %C) {
|
2013-07-14 09:42:54 +08:00
|
|
|
; CHECK-LABEL: @test11(
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-NEXT: [[B_V:%.*]] = select i1 %C, i32 10, i32 5
|
|
|
|
|
; CHECK-NEXT: [[B:%.*]] = lshr i32 %X, [[B:%.*]].v
|
|
|
|
|
; CHECK-NEXT: ret i32 [[B]]
|
|
|
|
|
;
|
|
|
|
|
%A = select i1 %C, i32 1024, i32 32 ; <i32> [#uses=1]
|
|
|
|
|
%B = udiv i32 %X, %A ; <i32> [#uses=1]
|
|
|
|
|
ret i32 %B
|
2006-02-05 15:52:47 +08:00
|
|
|
}
|
2008-05-16 10:59:42 +08:00
|
|
|
|
|
|
|
|
; PR2328
|
|
|
|
|
define i32 @test12(i32 %x) nounwind {
|
2013-07-14 09:42:54 +08:00
|
|
|
; CHECK-LABEL: @test12(
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-NEXT: ret i32 1
|
|
|
|
|
;
|
|
|
|
|
%tmp3 = udiv i32 %x, %x ; 1
|
|
|
|
|
ret i32 %tmp3
|
2008-05-16 10:59:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @test13(i32 %x) nounwind {
|
2013-07-14 09:42:54 +08:00
|
|
|
; CHECK-LABEL: @test13(
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-NEXT: ret i32 1
|
|
|
|
|
;
|
|
|
|
|
%tmp3 = sdiv i32 %x, %x ; 1
|
|
|
|
|
ret i32 %tmp3
|
2008-05-16 10:59:42 +08:00
|
|
|
}
|
|
|
|
|
|
2011-05-01 02:16:00 +08:00
|
|
|
define i32 @test14(i8 %x) nounwind {
|
2013-07-14 09:42:54 +08:00
|
|
|
; CHECK-LABEL: @test14(
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-NEXT: ret i32 0
|
|
|
|
|
;
|
|
|
|
|
%zext = zext i8 %x to i32
|
|
|
|
|
%div = udiv i32 %zext, 257 ; 0
|
|
|
|
|
ret i32 %div
|
2011-05-01 02:16:00 +08:00
|
|
|
}
|
Carve out a place in instcombine to put transformations which work knowing that their
result is non-zero. Implement an example optimization (PR9814), which allows us to
transform:
A / ((1 << B) >>u 2)
into:
A >>u (B-2)
which we compile into:
_divu3: ## @divu3
leal -2(%rsi), %ecx
shrl %cl, %edi
movl %edi, %eax
ret
instead of:
_divu3: ## @divu3
movb %sil, %cl
movl $1, %esi
shll %cl, %esi
shrl $2, %esi
movl %edi, %eax
xorl %edx, %edx
divl %esi, %eax
ret
llvm-svn: 131860
2011-05-23 02:18:41 +08:00
|
|
|
|
|
|
|
|
; PR9814
|
|
|
|
|
define i32 @test15(i32 %a, i32 %b) nounwind {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test15(
|
|
|
|
|
; CHECK-NEXT: [[TMP1:%.*]] = add i32 %b, -2
|
|
|
|
|
; CHECK-NEXT: [[DIV2:%.*]] = lshr i32 %a, [[TMP1]]
|
|
|
|
|
; CHECK-NEXT: ret i32 [[DIV2]]
|
|
|
|
|
;
|
Carve out a place in instcombine to put transformations which work knowing that their
result is non-zero. Implement an example optimization (PR9814), which allows us to
transform:
A / ((1 << B) >>u 2)
into:
A >>u (B-2)
which we compile into:
_divu3: ## @divu3
leal -2(%rsi), %ecx
shrl %cl, %edi
movl %edi, %eax
ret
instead of:
_divu3: ## @divu3
movb %sil, %cl
movl $1, %esi
shll %cl, %esi
shrl $2, %esi
movl %edi, %eax
xorl %edx, %edx
divl %esi, %eax
ret
llvm-svn: 131860
2011-05-23 02:18:41 +08:00
|
|
|
%shl = shl i32 1, %b
|
|
|
|
|
%div = lshr i32 %shl, 2
|
|
|
|
|
%div2 = udiv i32 %a, %div
|
|
|
|
|
ret i32 %div2
|
|
|
|
|
}
|
|
|
|
|
|
2014-01-19 23:24:22 +08:00
|
|
|
define <2 x i64> @test16(<2 x i64> %x) nounwind {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test16(
|
|
|
|
|
; CHECK-NEXT: [[DIV:%.*]] = udiv <2 x i64> %x, <i64 192, i64 192>
|
|
|
|
|
; CHECK-NEXT: ret <2 x i64> [[DIV]]
|
|
|
|
|
;
|
2014-10-14 05:48:30 +08:00
|
|
|
%shr = lshr <2 x i64> %x, <i64 5, i64 5>
|
|
|
|
|
%div = udiv <2 x i64> %shr, <i64 6, i64 6>
|
2014-01-19 23:24:22 +08:00
|
|
|
ret <2 x i64> %div
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <2 x i64> @test17(<2 x i64> %x) nounwind {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test17(
|
|
|
|
|
; CHECK-NEXT: [[DIV:%.*]] = sdiv <2 x i64> %x, <i64 -3, i64 -4>
|
|
|
|
|
; CHECK-NEXT: ret <2 x i64> [[DIV]]
|
|
|
|
|
;
|
2014-01-19 23:24:22 +08:00
|
|
|
%neg = sub nsw <2 x i64> zeroinitializer, %x
|
|
|
|
|
%div = sdiv <2 x i64> %neg, <i64 3, i64 4>
|
|
|
|
|
ret <2 x i64> %div
|
|
|
|
|
}
|
Carve out a place in instcombine to put transformations which work knowing that their
result is non-zero. Implement an example optimization (PR9814), which allows us to
transform:
A / ((1 << B) >>u 2)
into:
A >>u (B-2)
which we compile into:
_divu3: ## @divu3
leal -2(%rsi), %ecx
shrl %cl, %edi
movl %edi, %eax
ret
instead of:
_divu3: ## @divu3
movb %sil, %cl
movl $1, %esi
shll %cl, %esi
shrl $2, %esi
movl %edi, %eax
xorl %edx, %edx
divl %esi, %eax
ret
llvm-svn: 131860
2011-05-23 02:18:41 +08:00
|
|
|
|
2014-01-19 23:24:22 +08:00
|
|
|
define <2 x i64> @test18(<2 x i64> %x) nounwind {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test18(
|
|
|
|
|
; CHECK-NEXT: [[DIV:%.*]] = sub <2 x i64> zeroinitializer, %x
|
|
|
|
|
; CHECK-NEXT: ret <2 x i64> [[DIV]]
|
|
|
|
|
;
|
2014-01-19 23:24:22 +08:00
|
|
|
%div = sdiv <2 x i64> %x, <i64 -1, i64 -1>
|
|
|
|
|
ret <2 x i64> %div
|
|
|
|
|
}
|
2014-05-14 11:03:05 +08:00
|
|
|
|
|
|
|
|
define i32 @test19(i32 %x) {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test19(
|
|
|
|
|
; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i32 %x, 1
|
|
|
|
|
; CHECK-NEXT: [[A:%.*]] = zext i1 [[TMP1]] to i32
|
|
|
|
|
; CHECK-NEXT: ret i32 [[A]]
|
|
|
|
|
;
|
2014-05-14 11:03:05 +08:00
|
|
|
%A = udiv i32 1, %x
|
|
|
|
|
ret i32 %A
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @test20(i32 %x) {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test20(
|
|
|
|
|
; CHECK-NEXT: [[TMP1:%.*]] = add i32 %x, 1
|
|
|
|
|
; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[TMP1]], 3
|
|
|
|
|
; CHECK-NEXT: [[A:%.*]] = select i1 [[TMP2]], i32 %x, i32 0
|
|
|
|
|
; CHECK-NEXT: ret i32 [[A]]
|
|
|
|
|
;
|
2014-05-14 11:03:05 +08:00
|
|
|
%A = sdiv i32 1, %x
|
|
|
|
|
ret i32 %A
|
|
|
|
|
}
|
InstCombine: Combine mul with div.
We can combne a mul with a div if one of the operands is a multiple of
the other:
%mul = mul nsw nuw %a, C1
%ret = udiv %mul, C2
=>
%ret = mul nsw %a, (C1 / C2)
This can expose further optimization opportunities if we end up
multiplying or dividing by a power of 2.
Consider this small example:
define i32 @f(i32 %a) {
%mul = mul nuw i32 %a, 14
%div = udiv exact i32 %mul, 7
ret i32 %div
}
which gets CodeGen'd to:
imull $14, %edi, %eax
imulq $613566757, %rax, %rcx
shrq $32, %rcx
subl %ecx, %eax
shrl %eax
addl %ecx, %eax
shrl $2, %eax
retq
We can now transform this into:
define i32 @f(i32 %a) {
%shl = shl nuw i32 %a, 1
ret i32 %shl
}
which gets CodeGen'd to:
leal (%rdi,%rdi), %eax
retq
This fixes PR20681.
llvm-svn: 215815
2014-08-16 16:55:06 +08:00
|
|
|
|
|
|
|
|
define i32 @test21(i32 %a) {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test21(
|
|
|
|
|
; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 %a, 3
|
|
|
|
|
; CHECK-NEXT: ret i32 [[DIV]]
|
|
|
|
|
;
|
InstCombine: Combine mul with div.
We can combne a mul with a div if one of the operands is a multiple of
the other:
%mul = mul nsw nuw %a, C1
%ret = udiv %mul, C2
=>
%ret = mul nsw %a, (C1 / C2)
This can expose further optimization opportunities if we end up
multiplying or dividing by a power of 2.
Consider this small example:
define i32 @f(i32 %a) {
%mul = mul nuw i32 %a, 14
%div = udiv exact i32 %mul, 7
ret i32 %div
}
which gets CodeGen'd to:
imull $14, %edi, %eax
imulq $613566757, %rax, %rcx
shrq $32, %rcx
subl %ecx, %eax
shrl %eax
addl %ecx, %eax
shrl $2, %eax
retq
We can now transform this into:
define i32 @f(i32 %a) {
%shl = shl nuw i32 %a, 1
ret i32 %shl
}
which gets CodeGen'd to:
leal (%rdi,%rdi), %eax
retq
This fixes PR20681.
llvm-svn: 215815
2014-08-16 16:55:06 +08:00
|
|
|
%shl = shl nsw i32 %a, 2
|
|
|
|
|
%div = sdiv i32 %shl, 12
|
|
|
|
|
ret i32 %div
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @test22(i32 %a) {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test22(
|
|
|
|
|
; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 %a, 4
|
|
|
|
|
; CHECK-NEXT: ret i32 [[DIV]]
|
|
|
|
|
;
|
InstCombine: Combine mul with div.
We can combne a mul with a div if one of the operands is a multiple of
the other:
%mul = mul nsw nuw %a, C1
%ret = udiv %mul, C2
=>
%ret = mul nsw %a, (C1 / C2)
This can expose further optimization opportunities if we end up
multiplying or dividing by a power of 2.
Consider this small example:
define i32 @f(i32 %a) {
%mul = mul nuw i32 %a, 14
%div = udiv exact i32 %mul, 7
ret i32 %div
}
which gets CodeGen'd to:
imull $14, %edi, %eax
imulq $613566757, %rax, %rcx
shrq $32, %rcx
subl %ecx, %eax
shrl %eax
addl %ecx, %eax
shrl $2, %eax
retq
We can now transform this into:
define i32 @f(i32 %a) {
%shl = shl nuw i32 %a, 1
ret i32 %shl
}
which gets CodeGen'd to:
leal (%rdi,%rdi), %eax
retq
This fixes PR20681.
llvm-svn: 215815
2014-08-16 16:55:06 +08:00
|
|
|
%mul = mul nsw i32 %a, 3
|
|
|
|
|
%div = sdiv i32 %mul, 12
|
|
|
|
|
ret i32 %div
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @test23(i32 %a) {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test23(
|
|
|
|
|
; CHECK-NEXT: [[DIV:%.*]] = udiv i32 %a, 3
|
|
|
|
|
; CHECK-NEXT: ret i32 [[DIV]]
|
|
|
|
|
;
|
InstCombine: Combine mul with div.
We can combne a mul with a div if one of the operands is a multiple of
the other:
%mul = mul nsw nuw %a, C1
%ret = udiv %mul, C2
=>
%ret = mul nsw %a, (C1 / C2)
This can expose further optimization opportunities if we end up
multiplying or dividing by a power of 2.
Consider this small example:
define i32 @f(i32 %a) {
%mul = mul nuw i32 %a, 14
%div = udiv exact i32 %mul, 7
ret i32 %div
}
which gets CodeGen'd to:
imull $14, %edi, %eax
imulq $613566757, %rax, %rcx
shrq $32, %rcx
subl %ecx, %eax
shrl %eax
addl %ecx, %eax
shrl $2, %eax
retq
We can now transform this into:
define i32 @f(i32 %a) {
%shl = shl nuw i32 %a, 1
ret i32 %shl
}
which gets CodeGen'd to:
leal (%rdi,%rdi), %eax
retq
This fixes PR20681.
llvm-svn: 215815
2014-08-16 16:55:06 +08:00
|
|
|
%shl = shl nuw i32 %a, 2
|
|
|
|
|
%div = udiv i32 %shl, 12
|
|
|
|
|
ret i32 %div
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @test24(i32 %a) {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test24(
|
|
|
|
|
; CHECK-NEXT: [[DIV:%.*]] = lshr i32 %a, 2
|
|
|
|
|
; CHECK-NEXT: ret i32 [[DIV]]
|
|
|
|
|
;
|
InstCombine: Combine mul with div.
We can combne a mul with a div if one of the operands is a multiple of
the other:
%mul = mul nsw nuw %a, C1
%ret = udiv %mul, C2
=>
%ret = mul nsw %a, (C1 / C2)
This can expose further optimization opportunities if we end up
multiplying or dividing by a power of 2.
Consider this small example:
define i32 @f(i32 %a) {
%mul = mul nuw i32 %a, 14
%div = udiv exact i32 %mul, 7
ret i32 %div
}
which gets CodeGen'd to:
imull $14, %edi, %eax
imulq $613566757, %rax, %rcx
shrq $32, %rcx
subl %ecx, %eax
shrl %eax
addl %ecx, %eax
shrl $2, %eax
retq
We can now transform this into:
define i32 @f(i32 %a) {
%shl = shl nuw i32 %a, 1
ret i32 %shl
}
which gets CodeGen'd to:
leal (%rdi,%rdi), %eax
retq
This fixes PR20681.
llvm-svn: 215815
2014-08-16 16:55:06 +08:00
|
|
|
%mul = mul nuw i32 %a, 3
|
|
|
|
|
%div = udiv i32 %mul, 12
|
|
|
|
|
ret i32 %div
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @test25(i32 %a) {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test25(
|
|
|
|
|
; CHECK-NEXT: [[DIV:%.*]] = shl nsw i32 %a, 1
|
|
|
|
|
; CHECK-NEXT: ret i32 [[DIV]]
|
|
|
|
|
;
|
InstCombine: Combine mul with div.
We can combne a mul with a div if one of the operands is a multiple of
the other:
%mul = mul nsw nuw %a, C1
%ret = udiv %mul, C2
=>
%ret = mul nsw %a, (C1 / C2)
This can expose further optimization opportunities if we end up
multiplying or dividing by a power of 2.
Consider this small example:
define i32 @f(i32 %a) {
%mul = mul nuw i32 %a, 14
%div = udiv exact i32 %mul, 7
ret i32 %div
}
which gets CodeGen'd to:
imull $14, %edi, %eax
imulq $613566757, %rax, %rcx
shrq $32, %rcx
subl %ecx, %eax
shrl %eax
addl %ecx, %eax
shrl $2, %eax
retq
We can now transform this into:
define i32 @f(i32 %a) {
%shl = shl nuw i32 %a, 1
ret i32 %shl
}
which gets CodeGen'd to:
leal (%rdi,%rdi), %eax
retq
This fixes PR20681.
llvm-svn: 215815
2014-08-16 16:55:06 +08:00
|
|
|
%shl = shl nsw i32 %a, 2
|
|
|
|
|
%div = sdiv i32 %shl, 2
|
|
|
|
|
ret i32 %div
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @test26(i32 %a) {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test26(
|
|
|
|
|
; CHECK-NEXT: [[DIV:%.*]] = shl nsw i32 %a, 2
|
|
|
|
|
; CHECK-NEXT: ret i32 [[DIV]]
|
|
|
|
|
;
|
InstCombine: Combine mul with div.
We can combne a mul with a div if one of the operands is a multiple of
the other:
%mul = mul nsw nuw %a, C1
%ret = udiv %mul, C2
=>
%ret = mul nsw %a, (C1 / C2)
This can expose further optimization opportunities if we end up
multiplying or dividing by a power of 2.
Consider this small example:
define i32 @f(i32 %a) {
%mul = mul nuw i32 %a, 14
%div = udiv exact i32 %mul, 7
ret i32 %div
}
which gets CodeGen'd to:
imull $14, %edi, %eax
imulq $613566757, %rax, %rcx
shrq $32, %rcx
subl %ecx, %eax
shrl %eax
addl %ecx, %eax
shrl $2, %eax
retq
We can now transform this into:
define i32 @f(i32 %a) {
%shl = shl nuw i32 %a, 1
ret i32 %shl
}
which gets CodeGen'd to:
leal (%rdi,%rdi), %eax
retq
This fixes PR20681.
llvm-svn: 215815
2014-08-16 16:55:06 +08:00
|
|
|
%mul = mul nsw i32 %a, 12
|
|
|
|
|
%div = sdiv i32 %mul, 3
|
|
|
|
|
ret i32 %div
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @test27(i32 %a) {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test27(
|
|
|
|
|
; CHECK-NEXT: [[DIV:%.*]] = shl nuw i32 %a, 1
|
|
|
|
|
; CHECK-NEXT: ret i32 [[DIV]]
|
|
|
|
|
;
|
InstCombine: Combine mul with div.
We can combne a mul with a div if one of the operands is a multiple of
the other:
%mul = mul nsw nuw %a, C1
%ret = udiv %mul, C2
=>
%ret = mul nsw %a, (C1 / C2)
This can expose further optimization opportunities if we end up
multiplying or dividing by a power of 2.
Consider this small example:
define i32 @f(i32 %a) {
%mul = mul nuw i32 %a, 14
%div = udiv exact i32 %mul, 7
ret i32 %div
}
which gets CodeGen'd to:
imull $14, %edi, %eax
imulq $613566757, %rax, %rcx
shrq $32, %rcx
subl %ecx, %eax
shrl %eax
addl %ecx, %eax
shrl $2, %eax
retq
We can now transform this into:
define i32 @f(i32 %a) {
%shl = shl nuw i32 %a, 1
ret i32 %shl
}
which gets CodeGen'd to:
leal (%rdi,%rdi), %eax
retq
This fixes PR20681.
llvm-svn: 215815
2014-08-16 16:55:06 +08:00
|
|
|
%shl = shl nuw i32 %a, 2
|
|
|
|
|
%div = udiv i32 %shl, 2
|
|
|
|
|
ret i32 %div
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @test28(i32 %a) {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test28(
|
|
|
|
|
; CHECK-NEXT: [[DIV:%.*]] = mul nuw i32 %a, 12
|
|
|
|
|
; CHECK-NEXT: ret i32 [[DIV]]
|
|
|
|
|
;
|
InstCombine: Combine mul with div.
We can combne a mul with a div if one of the operands is a multiple of
the other:
%mul = mul nsw nuw %a, C1
%ret = udiv %mul, C2
=>
%ret = mul nsw %a, (C1 / C2)
This can expose further optimization opportunities if we end up
multiplying or dividing by a power of 2.
Consider this small example:
define i32 @f(i32 %a) {
%mul = mul nuw i32 %a, 14
%div = udiv exact i32 %mul, 7
ret i32 %div
}
which gets CodeGen'd to:
imull $14, %edi, %eax
imulq $613566757, %rax, %rcx
shrq $32, %rcx
subl %ecx, %eax
shrl %eax
addl %ecx, %eax
shrl $2, %eax
retq
We can now transform this into:
define i32 @f(i32 %a) {
%shl = shl nuw i32 %a, 1
ret i32 %shl
}
which gets CodeGen'd to:
leal (%rdi,%rdi), %eax
retq
This fixes PR20681.
llvm-svn: 215815
2014-08-16 16:55:06 +08:00
|
|
|
%mul = mul nuw i32 %a, 36
|
|
|
|
|
%div = udiv i32 %mul, 3
|
|
|
|
|
ret i32 %div
|
|
|
|
|
}
|
2014-10-11 18:20:04 +08:00
|
|
|
|
|
|
|
|
define i32 @test29(i32 %a) {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test29(
|
|
|
|
|
; CHECK-NEXT: [[MUL_LOBIT:%.*]] = and i32 %a, 1
|
|
|
|
|
; CHECK-NEXT: ret i32 [[MUL_LOBIT]]
|
|
|
|
|
;
|
2014-10-11 18:20:04 +08:00
|
|
|
%mul = shl nsw i32 %a, 31
|
|
|
|
|
%div = sdiv i32 %mul, -2147483648
|
|
|
|
|
ret i32 %div
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @test30(i32 %a) {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test30(
|
|
|
|
|
; CHECK-NEXT: ret i32 %a
|
|
|
|
|
;
|
2014-10-11 18:20:04 +08:00
|
|
|
%mul = shl nuw i32 %a, 31
|
|
|
|
|
%div = udiv i32 %mul, -2147483648
|
|
|
|
|
ret i32 %div
|
|
|
|
|
}
|
2014-10-14 05:48:30 +08:00
|
|
|
|
2014-10-15 04:28:40 +08:00
|
|
|
define <2 x i32> @test31(<2 x i32> %x) {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test31(
|
|
|
|
|
; CHECK-NEXT: ret <2 x i32> zeroinitializer
|
|
|
|
|
;
|
2014-10-14 05:48:30 +08:00
|
|
|
%shr = lshr <2 x i32> %x, <i32 31, i32 31>
|
|
|
|
|
%div = udiv <2 x i32> %shr, <i32 2147483647, i32 2147483647>
|
|
|
|
|
ret <2 x i32> %div
|
|
|
|
|
}
|
2014-10-15 04:28:40 +08:00
|
|
|
|
|
|
|
|
define i32 @test32(i32 %a, i32 %b) {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test32(
|
|
|
|
|
; CHECK-NEXT: [[SHL:%.*]] = shl i32 2, %b
|
|
|
|
|
; CHECK-NEXT: [[DIV:%.*]] = lshr i32 [[SHL]], 2
|
|
|
|
|
; CHECK-NEXT: [[DIV2:%.*]] = udiv i32 %a, [[DIV]]
|
|
|
|
|
; CHECK-NEXT: ret i32 [[DIV2]]
|
|
|
|
|
;
|
2014-10-15 04:28:40 +08:00
|
|
|
%shl = shl i32 2, %b
|
|
|
|
|
%div = lshr i32 %shl, 2
|
|
|
|
|
%div2 = udiv i32 %a, %div
|
|
|
|
|
ret i32 %div2
|
|
|
|
|
}
|
2014-11-23 02:16:54 +08:00
|
|
|
|
|
|
|
|
define <2 x i64> @test33(<2 x i64> %x) nounwind {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test33(
|
|
|
|
|
; CHECK-NEXT: [[DIV:%.*]] = udiv exact <2 x i64> %x, <i64 192, i64 192>
|
|
|
|
|
; CHECK-NEXT: ret <2 x i64> [[DIV]]
|
|
|
|
|
;
|
2014-11-23 02:16:54 +08:00
|
|
|
%shr = lshr exact <2 x i64> %x, <i64 5, i64 5>
|
|
|
|
|
%div = udiv exact <2 x i64> %shr, <i64 6, i64 6>
|
|
|
|
|
ret <2 x i64> %div
|
|
|
|
|
}
|
2014-11-23 04:00:34 +08:00
|
|
|
|
|
|
|
|
define <2 x i64> @test34(<2 x i64> %x) nounwind {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test34(
|
|
|
|
|
; CHECK-NEXT: [[DIV:%.*]] = sdiv exact <2 x i64> %x, <i64 -3, i64 -4>
|
|
|
|
|
; CHECK-NEXT: ret <2 x i64> [[DIV]]
|
|
|
|
|
;
|
2014-11-23 04:00:34 +08:00
|
|
|
%neg = sub nsw <2 x i64> zeroinitializer, %x
|
|
|
|
|
%div = sdiv exact <2 x i64> %neg, <i64 3, i64 4>
|
|
|
|
|
ret <2 x i64> %div
|
|
|
|
|
}
|
2014-11-23 04:00:38 +08:00
|
|
|
|
|
|
|
|
define i32 @test35(i32 %A) {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test35(
|
|
|
|
|
; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 2147483647
|
|
|
|
|
; CHECK-NEXT: [[MUL:%.*]] = udiv exact i32 [[AND]], 2147483647
|
|
|
|
|
; CHECK-NEXT: ret i32 [[MUL]]
|
|
|
|
|
;
|
2014-11-23 04:00:38 +08:00
|
|
|
%and = and i32 %A, 2147483647
|
|
|
|
|
%mul = sdiv exact i32 %and, 2147483647
|
|
|
|
|
ret i32 %mul
|
|
|
|
|
}
|
2014-11-23 04:00:41 +08:00
|
|
|
|
|
|
|
|
define i32 @test36(i32 %A) {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test36(
|
|
|
|
|
; CHECK-NEXT: [[AND:%.*]] = and i32 %A, 2147483647
|
|
|
|
|
; CHECK-NEXT: [[MUL:%.*]] = lshr exact i32 [[AND]], %A
|
|
|
|
|
; CHECK-NEXT: ret i32 [[MUL]]
|
|
|
|
|
;
|
2014-11-23 04:00:41 +08:00
|
|
|
%and = and i32 %A, 2147483647
|
|
|
|
|
%shl = shl nsw i32 1, %A
|
|
|
|
|
%mul = sdiv exact i32 %and, %shl
|
|
|
|
|
ret i32 %mul
|
|
|
|
|
}
|
2015-09-06 14:49:59 +08:00
|
|
|
|
2016-05-21 06:08:40 +08:00
|
|
|
; FIXME: Vector should get same transform as scalar.
|
|
|
|
|
|
|
|
|
|
define <2 x i32> @test36vec(<2 x i32> %A) {
|
|
|
|
|
; CHECK-LABEL: @test36vec(
|
|
|
|
|
; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> %A, <i32 2147483647, i32 2147483647>
|
2016-05-22 23:41:53 +08:00
|
|
|
; CHECK-NEXT: [[SHL:%.*]] = shl nuw nsw <2 x i32> <i32 1, i32 1>, %A
|
2016-05-21 06:08:40 +08:00
|
|
|
; CHECK-NEXT: [[MUL:%.*]] = sdiv exact <2 x i32> [[AND]], [[SHL]]
|
|
|
|
|
; CHECK-NEXT: ret <2 x i32> [[MUL]]
|
|
|
|
|
;
|
|
|
|
|
%and = and <2 x i32> %A, <i32 2147483647, i32 2147483647>
|
|
|
|
|
%shl = shl nsw <2 x i32> <i32 1, i32 1>, %A
|
|
|
|
|
%mul = sdiv exact <2 x i32> %and, %shl
|
|
|
|
|
ret <2 x i32> %mul
|
|
|
|
|
}
|
|
|
|
|
|
2015-09-06 14:49:59 +08:00
|
|
|
define i32 @test37(i32* %b) {
|
2016-05-02 23:18:13 +08:00
|
|
|
; CHECK-LABEL: @test37(
|
|
|
|
|
; CHECK-NEXT: entry:
|
|
|
|
|
; CHECK-NEXT: store i32 0, i32* %b, align 4
|
|
|
|
|
; CHECK-NEXT: br i1 undef, label %lor.rhs, label %lor.end
|
|
|
|
|
; CHECK: lor.rhs:
|
|
|
|
|
; CHECK-NEXT: br label %lor.end
|
|
|
|
|
; CHECK: lor.end:
|
|
|
|
|
; CHECK-NEXT: ret i32 0
|
|
|
|
|
;
|
2015-09-06 14:49:59 +08:00
|
|
|
entry:
|
|
|
|
|
store i32 0, i32* %b, align 4
|
|
|
|
|
%0 = load i32, i32* %b, align 4
|
|
|
|
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br i1 undef, label %lor.rhs, label %lor.end
|
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|
|
|
|
|
lor.rhs: ; preds = %entry
|
|
|
|
|
%mul = mul nsw i32 undef, %0
|
|
|
|
|
br label %lor.end
|
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|
|
|
|
|
|
lor.end: ; preds = %lor.rhs, %entry
|
|
|
|
|
%t.0 = phi i32 [ %0, %entry ], [ %mul, %lor.rhs ]
|
|
|
|
|
%div = sdiv i32 %t.0, 2
|
|
|
|
|
ret i32 %div
|
|
|
|
|
}
|
