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llvm-project/llvm/test/CodeGen/RISCV/select-or.ll

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[RISCV][NFC] Add Test for (select (or B1, B2), X, Y) Summary: As shown, LLVM is keen to avoid logic and introduce selects (in DAGCombiner, and other places). This leads to control flow on RISC-V which we should attempt to avoid. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79267
2020-07-01 18:54:56 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
;; There are a few different ways to lower (select (or A, B), X, Y). This test
;; ensures that we do so with as few branches as possible.
define signext i32 @select_of_or(i1 zeroext %a, i1 zeroext %b, i32 signext %c, i32 signext %d) nounwind {
; RV32I-LABEL: select_of_or:
; RV32I: # %bb.0:
[RISCV] Implement Hooks to avoid chaining SELECT Summary: This implements two hooks that attempt to avoid control flow for RISC-V. RISC-V will lower SELECTs into control flow, which is not a great idea. The hook `hasMultipleConditionRegisters()` turns off the following DAGCombiner folds: select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y)) select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y) The second hook `setJumpIsExpensive` controls a flag that has a similar purpose and is used in CodeGenPrepare and the SelectionDAGBuilder. Both of these have the effect of ensuring more logic is done before fewer jumps. Note: with the `B` extension, we may be able to lower select into a conditional move instruction, so at some point these hooks will need to be guarded based on enabled extensions. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79268
2020-07-01 18:55:07 +08:00
; RV32I-NEXT: or a1, a0, a1
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: bnez a1, .LBB0_2
[RISCV][NFC] Add Test for (select (or B1, B2), X, Y) Summary: As shown, LLVM is keen to avoid logic and introduce selects (in DAGCombiner, and other places). This leads to control flow on RISC-V which we should attempt to avoid. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79267
2020-07-01 18:54:56 +08:00
; RV32I-NEXT: # %bb.1:
[RISCV] Implement Hooks to avoid chaining SELECT Summary: This implements two hooks that attempt to avoid control flow for RISC-V. RISC-V will lower SELECTs into control flow, which is not a great idea. The hook `hasMultipleConditionRegisters()` turns off the following DAGCombiner folds: select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y)) select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y) The second hook `setJumpIsExpensive` controls a flag that has a similar purpose and is used in CodeGenPrepare and the SelectionDAGBuilder. Both of these have the effect of ensuring more logic is done before fewer jumps. Note: with the `B` extension, we may be able to lower select into a conditional move instruction, so at some point these hooks will need to be guarded based on enabled extensions. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79268
2020-07-01 18:55:07 +08:00
; RV32I-NEXT: mv a0, a3
[RISCV][NFC] Add Test for (select (or B1, B2), X, Y) Summary: As shown, LLVM is keen to avoid logic and introduce selects (in DAGCombiner, and other places). This leads to control flow on RISC-V which we should attempt to avoid. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79267
2020-07-01 18:54:56 +08:00
; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: ret
;
; RV64I-LABEL: select_of_or:
; RV64I: # %bb.0:
[RISCV] Implement Hooks to avoid chaining SELECT Summary: This implements two hooks that attempt to avoid control flow for RISC-V. RISC-V will lower SELECTs into control flow, which is not a great idea. The hook `hasMultipleConditionRegisters()` turns off the following DAGCombiner folds: select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y)) select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y) The second hook `setJumpIsExpensive` controls a flag that has a similar purpose and is used in CodeGenPrepare and the SelectionDAGBuilder. Both of these have the effect of ensuring more logic is done before fewer jumps. Note: with the `B` extension, we may be able to lower select into a conditional move instruction, so at some point these hooks will need to be guarded based on enabled extensions. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79268
2020-07-01 18:55:07 +08:00
; RV64I-NEXT: or a1, a0, a1
; RV64I-NEXT: mv a0, a2
; RV64I-NEXT: bnez a1, .LBB0_2
[RISCV][NFC] Add Test for (select (or B1, B2), X, Y) Summary: As shown, LLVM is keen to avoid logic and introduce selects (in DAGCombiner, and other places). This leads to control flow on RISC-V which we should attempt to avoid. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79267
2020-07-01 18:54:56 +08:00
; RV64I-NEXT: # %bb.1:
[RISCV] Implement Hooks to avoid chaining SELECT Summary: This implements two hooks that attempt to avoid control flow for RISC-V. RISC-V will lower SELECTs into control flow, which is not a great idea. The hook `hasMultipleConditionRegisters()` turns off the following DAGCombiner folds: select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y)) select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y) The second hook `setJumpIsExpensive` controls a flag that has a similar purpose and is used in CodeGenPrepare and the SelectionDAGBuilder. Both of these have the effect of ensuring more logic is done before fewer jumps. Note: with the `B` extension, we may be able to lower select into a conditional move instruction, so at some point these hooks will need to be guarded based on enabled extensions. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79268
2020-07-01 18:55:07 +08:00
; RV64I-NEXT: mv a0, a3
[RISCV][NFC] Add Test for (select (or B1, B2), X, Y) Summary: As shown, LLVM is keen to avoid logic and introduce selects (in DAGCombiner, and other places). This leads to control flow on RISC-V which we should attempt to avoid. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79267
2020-07-01 18:54:56 +08:00
; RV64I-NEXT: .LBB0_2:
; RV64I-NEXT: ret
%1 = or i1 %a, %b
%2 = select i1 %1, i32 %c, i32 %d
ret i32 %2
}
declare signext i32 @either() nounwind
declare signext i32 @neither() nounwind
define signext i32 @if_of_or(i1 zeroext %a, i1 zeroext %b) nounwind {
; RV32I-LABEL: if_of_or:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
[RISCV] Implement Hooks to avoid chaining SELECT Summary: This implements two hooks that attempt to avoid control flow for RISC-V. RISC-V will lower SELECTs into control flow, which is not a great idea. The hook `hasMultipleConditionRegisters()` turns off the following DAGCombiner folds: select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y)) select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y) The second hook `setJumpIsExpensive` controls a flag that has a similar purpose and is used in CodeGenPrepare and the SelectionDAGBuilder. Both of these have the effect of ensuring more logic is done before fewer jumps. Note: with the `B` extension, we may be able to lower select into a conditional move instruction, so at some point these hooks will need to be guarded based on enabled extensions. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79268
2020-07-01 18:55:07 +08:00
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: addi a1, zero, 1
; RV32I-NEXT: bne a0, a1, .LBB1_2
; RV32I-NEXT: # %bb.1: # %if.then
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: call either@plt
[RISCV] Implement Hooks to avoid chaining SELECT Summary: This implements two hooks that attempt to avoid control flow for RISC-V. RISC-V will lower SELECTs into control flow, which is not a great idea. The hook `hasMultipleConditionRegisters()` turns off the following DAGCombiner folds: select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y)) select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y) The second hook `setJumpIsExpensive` controls a flag that has a similar purpose and is used in CodeGenPrepare and the SelectionDAGBuilder. Both of these have the effect of ensuring more logic is done before fewer jumps. Note: with the `B` extension, we may be able to lower select into a conditional move instruction, so at some point these hooks will need to be guarded based on enabled extensions. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79268
2020-07-01 18:55:07 +08:00
; RV32I-NEXT: j .LBB1_3
; RV32I-NEXT: .LBB1_2: # %if.else
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: call neither@plt
[RISCV] Implement Hooks to avoid chaining SELECT Summary: This implements two hooks that attempt to avoid control flow for RISC-V. RISC-V will lower SELECTs into control flow, which is not a great idea. The hook `hasMultipleConditionRegisters()` turns off the following DAGCombiner folds: select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y)) select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y) The second hook `setJumpIsExpensive` controls a flag that has a similar purpose and is used in CodeGenPrepare and the SelectionDAGBuilder. Both of these have the effect of ensuring more logic is done before fewer jumps. Note: with the `B` extension, we may be able to lower select into a conditional move instruction, so at some point these hooks will need to be guarded based on enabled extensions. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79268
2020-07-01 18:55:07 +08:00
; RV32I-NEXT: .LBB1_3: # %if.end
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
[RISCV][NFC] Add Test for (select (or B1, B2), X, Y) Summary: As shown, LLVM is keen to avoid logic and introduce selects (in DAGCombiner, and other places). This leads to control flow on RISC-V which we should attempt to avoid. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79267
2020-07-01 18:54:56 +08:00
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: if_of_or:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
[RISCV] Implement Hooks to avoid chaining SELECT Summary: This implements two hooks that attempt to avoid control flow for RISC-V. RISC-V will lower SELECTs into control flow, which is not a great idea. The hook `hasMultipleConditionRegisters()` turns off the following DAGCombiner folds: select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y)) select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y) The second hook `setJumpIsExpensive` controls a flag that has a similar purpose and is used in CodeGenPrepare and the SelectionDAGBuilder. Both of these have the effect of ensuring more logic is done before fewer jumps. Note: with the `B` extension, we may be able to lower select into a conditional move instruction, so at some point these hooks will need to be guarded based on enabled extensions. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79268
2020-07-01 18:55:07 +08:00
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: bne a0, a1, .LBB1_2
; RV64I-NEXT: # %bb.1: # %if.then
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: call either@plt
[RISCV] Implement Hooks to avoid chaining SELECT Summary: This implements two hooks that attempt to avoid control flow for RISC-V. RISC-V will lower SELECTs into control flow, which is not a great idea. The hook `hasMultipleConditionRegisters()` turns off the following DAGCombiner folds: select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y)) select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y) The second hook `setJumpIsExpensive` controls a flag that has a similar purpose and is used in CodeGenPrepare and the SelectionDAGBuilder. Both of these have the effect of ensuring more logic is done before fewer jumps. Note: with the `B` extension, we may be able to lower select into a conditional move instruction, so at some point these hooks will need to be guarded based on enabled extensions. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79268
2020-07-01 18:55:07 +08:00
; RV64I-NEXT: j .LBB1_3
; RV64I-NEXT: .LBB1_2: # %if.else
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: call neither@plt
[RISCV] Implement Hooks to avoid chaining SELECT Summary: This implements two hooks that attempt to avoid control flow for RISC-V. RISC-V will lower SELECTs into control flow, which is not a great idea. The hook `hasMultipleConditionRegisters()` turns off the following DAGCombiner folds: select(C0|C1, x, y) <=> select(C0, x, select(C1, x, y)) select(C0&C1, x, y) <=> select(C0, select(C1, x, y), y) The second hook `setJumpIsExpensive` controls a flag that has a similar purpose and is used in CodeGenPrepare and the SelectionDAGBuilder. Both of these have the effect of ensuring more logic is done before fewer jumps. Note: with the `B` extension, we may be able to lower select into a conditional move instruction, so at some point these hooks will need to be guarded based on enabled extensions. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79268
2020-07-01 18:55:07 +08:00
; RV64I-NEXT: .LBB1_3: # %if.end
[RISCV][NFC] Regenerate RISCV CodeGen tests Regenerated using: ./llvm/utils/update_llc_test_checks.py -u llvm/test/CodeGen/RISCV/*.ll This has added comments to spill-related instructions and added @plt to some symbols. Differential Revision: https://reviews.llvm.org/D92841
2020-12-10 03:41:19 +08:00
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
[RISCV][NFC] Add Test for (select (or B1, B2), X, Y) Summary: As shown, LLVM is keen to avoid logic and introduce selects (in DAGCombiner, and other places). This leads to control flow on RISC-V which we should attempt to avoid. Reviewed By: luismarques Differential Revision: https://reviews.llvm.org/D79267
2020-07-01 18:54:56 +08:00
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = or i1 %a, %b
br i1 %1, label %if.then, label %if.else
if.then:
%2 = tail call i32 @either()
br label %if.end
if.else:
%3 = tail call i32 @neither()
br label %if.end
if.end:
%4 = phi i32 [%2, %if.then], [%3, %if.else]
ret i32 %4
}