[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
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2019-06-13 17:37:38 +08:00
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declare i1 @llvm.experimental.vector.reduce.and.v1i1(<1 x i1> %a)
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declare i8 @llvm.experimental.vector.reduce.and.v1i8(<1 x i8> %a)
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declare i16 @llvm.experimental.vector.reduce.and.v1i16(<1 x i16> %a)
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declare i24 @llvm.experimental.vector.reduce.and.v1i24(<1 x i24> %a)
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declare i32 @llvm.experimental.vector.reduce.and.v1i32(<1 x i32> %a)
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declare i64 @llvm.experimental.vector.reduce.and.v1i64(<1 x i64> %a)
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declare i128 @llvm.experimental.vector.reduce.and.v1i128(<1 x i128> %a)
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declare i8 @llvm.experimental.vector.reduce.and.v3i8(<3 x i8> %a)
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declare i8 @llvm.experimental.vector.reduce.and.v9i8(<9 x i8> %a)
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declare i32 @llvm.experimental.vector.reduce.and.v3i32(<3 x i32> %a)
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declare i1 @llvm.experimental.vector.reduce.and.v4i1(<4 x i1> %a)
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declare i24 @llvm.experimental.vector.reduce.and.v4i24(<4 x i24> %a)
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declare i128 @llvm.experimental.vector.reduce.and.v2i128(<2 x i128> %a)
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declare i32 @llvm.experimental.vector.reduce.and.v16i32(<16 x i32> %a)
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[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
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define i1 @test_v1i1(<1 x i1> %a) nounwind {
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; CHECK-LABEL: test_v1i1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w0, w0, #0x1
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; CHECK-NEXT: ret
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2019-06-13 17:37:38 +08:00
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%b = call i1 @llvm.experimental.vector.reduce.and.v1i1(<1 x i1> %a)
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
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ret i1 %b
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}
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define i8 @test_v1i8(<1 x i8> %a) nounwind {
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; CHECK-LABEL: test_v1i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: umov w0, v0.b[0]
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; CHECK-NEXT: ret
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2019-06-13 17:37:38 +08:00
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%b = call i8 @llvm.experimental.vector.reduce.and.v1i8(<1 x i8> %a)
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
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ret i8 %b
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}
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define i16 @test_v1i16(<1 x i16> %a) nounwind {
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; CHECK-LABEL: test_v1i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: umov w0, v0.h[0]
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; CHECK-NEXT: ret
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2019-06-13 17:37:38 +08:00
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%b = call i16 @llvm.experimental.vector.reduce.and.v1i16(<1 x i16> %a)
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
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ret i16 %b
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}
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define i24 @test_v1i24(<1 x i24> %a) nounwind {
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; CHECK-LABEL: test_v1i24:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ret
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2019-06-13 17:37:38 +08:00
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%b = call i24 @llvm.experimental.vector.reduce.and.v1i24(<1 x i24> %a)
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
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ret i24 %b
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}
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define i32 @test_v1i32(<1 x i32> %a) nounwind {
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; CHECK-LABEL: test_v1i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: fmov w0, s0
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; CHECK-NEXT: ret
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2019-06-13 17:37:38 +08:00
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%b = call i32 @llvm.experimental.vector.reduce.and.v1i32(<1 x i32> %a)
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
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|
ret i32 %b
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|
}
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define i64 @test_v1i64(<1 x i64> %a) nounwind {
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|
; CHECK-LABEL: test_v1i64:
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|
; CHECK: // %bb.0:
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|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
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; CHECK-NEXT: fmov x0, d0
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|
; CHECK-NEXT: ret
|
2019-06-13 17:37:38 +08:00
|
|
|
%b = call i64 @llvm.experimental.vector.reduce.and.v1i64(<1 x i64> %a)
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
|
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|
ret i64 %b
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|
}
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define i128 @test_v1i128(<1 x i128> %a) nounwind {
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|
|
; CHECK-LABEL: test_v1i128:
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|
; CHECK: // %bb.0:
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|
; CHECK-NEXT: ret
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2019-06-13 17:37:38 +08:00
|
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|
%b = call i128 @llvm.experimental.vector.reduce.and.v1i128(<1 x i128> %a)
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
|
|
|
ret i128 %b
|
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|
|
|
}
|
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|
|
define i8 @test_v3i8(<3 x i8> %a) nounwind {
|
|
|
|
|
; CHECK-LABEL: test_v3i8:
|
|
|
|
|
; CHECK: // %bb.0:
|
|
|
|
|
; CHECK-NEXT: and w8, w0, w1
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|
; CHECK-NEXT: and w8, w8, w2
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|
|
; CHECK-NEXT: and w0, w8, #0xff
|
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|
|
|
; CHECK-NEXT: ret
|
2019-06-13 17:37:38 +08:00
|
|
|
%b = call i8 @llvm.experimental.vector.reduce.and.v3i8(<3 x i8> %a)
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
|
|
|
ret i8 %b
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i8 @test_v9i8(<9 x i8> %a) nounwind {
|
|
|
|
|
; CHECK-LABEL: test_v9i8:
|
|
|
|
|
; CHECK: // %bb.0:
|
|
|
|
|
; CHECK-NEXT: mov w8, #-1
|
|
|
|
|
; CHECK-NEXT: mov v0.b[9], w8
|
|
|
|
|
; CHECK-NEXT: mov v0.b[10], w8
|
|
|
|
|
; CHECK-NEXT: mov v0.b[11], w8
|
|
|
|
|
; CHECK-NEXT: mov v0.b[12], w8
|
|
|
|
|
; CHECK-NEXT: mov v0.b[13], w8
|
|
|
|
|
; CHECK-NEXT: mov v0.b[14], w8
|
|
|
|
|
; CHECK-NEXT: mov v0.b[15], w8
|
|
|
|
|
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
|
2019-08-13 17:33:25 +08:00
|
|
|
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
|
|
|
|
|
; CHECK-NEXT: umov w8, v0.b[1]
|
|
|
|
|
; CHECK-NEXT: umov w9, v0.b[0]
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
|
|
|
; CHECK-NEXT: and w8, w9, w8
|
2019-08-13 17:33:25 +08:00
|
|
|
; CHECK-NEXT: umov w9, v0.b[2]
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
|
|
|
; CHECK-NEXT: and w8, w8, w9
|
2019-08-13 17:33:25 +08:00
|
|
|
; CHECK-NEXT: umov w9, v0.b[3]
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
|
|
|
; CHECK-NEXT: and w8, w8, w9
|
2019-08-13 17:33:25 +08:00
|
|
|
; CHECK-NEXT: umov w9, v0.b[4]
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
|
|
|
; CHECK-NEXT: and w8, w8, w9
|
2019-08-13 17:33:25 +08:00
|
|
|
; CHECK-NEXT: umov w9, v0.b[5]
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
|
|
|
; CHECK-NEXT: and w8, w8, w9
|
|
|
|
|
; CHECK-NEXT: umov w9, v0.b[6]
|
|
|
|
|
; CHECK-NEXT: and w8, w8, w9
|
|
|
|
|
; CHECK-NEXT: umov w9, v0.b[7]
|
|
|
|
|
; CHECK-NEXT: and w0, w8, w9
|
|
|
|
|
; CHECK-NEXT: ret
|
2019-06-13 17:37:38 +08:00
|
|
|
%b = call i8 @llvm.experimental.vector.reduce.and.v9i8(<9 x i8> %a)
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
|
|
|
ret i8 %b
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @test_v3i32(<3 x i32> %a) nounwind {
|
|
|
|
|
; CHECK-LABEL: test_v3i32:
|
|
|
|
|
; CHECK: // %bb.0:
|
|
|
|
|
; CHECK-NEXT: mov w8, #-1
|
|
|
|
|
; CHECK-NEXT: mov v0.s[3], w8
|
|
|
|
|
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
|
2019-08-13 17:33:25 +08:00
|
|
|
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
|
|
|
; CHECK-NEXT: mov w8, v0.s[1]
|
2019-08-13 17:33:25 +08:00
|
|
|
; CHECK-NEXT: fmov w9, s0
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
|
|
|
; CHECK-NEXT: and w0, w9, w8
|
|
|
|
|
; CHECK-NEXT: ret
|
2019-06-13 17:37:38 +08:00
|
|
|
%b = call i32 @llvm.experimental.vector.reduce.and.v3i32(<3 x i32> %a)
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
|
|
|
ret i32 %b
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i1 @test_v4i1(<4 x i1> %a) nounwind {
|
|
|
|
|
; CHECK-LABEL: test_v4i1:
|
|
|
|
|
; CHECK: // %bb.0:
|
|
|
|
|
; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
|
|
|
|
|
; CHECK-NEXT: umov w10, v0.h[1]
|
|
|
|
|
; CHECK-NEXT: umov w11, v0.h[0]
|
|
|
|
|
; CHECK-NEXT: umov w9, v0.h[2]
|
|
|
|
|
; CHECK-NEXT: and w10, w11, w10
|
|
|
|
|
; CHECK-NEXT: umov w8, v0.h[3]
|
|
|
|
|
; CHECK-NEXT: and w9, w10, w9
|
|
|
|
|
; CHECK-NEXT: and w8, w9, w8
|
|
|
|
|
; CHECK-NEXT: and w0, w8, #0x1
|
|
|
|
|
; CHECK-NEXT: ret
|
2019-06-13 17:37:38 +08:00
|
|
|
%b = call i1 @llvm.experimental.vector.reduce.and.v4i1(<4 x i1> %a)
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
|
|
|
ret i1 %b
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i24 @test_v4i24(<4 x i24> %a) nounwind {
|
|
|
|
|
; CHECK-LABEL: test_v4i24:
|
|
|
|
|
; CHECK: // %bb.0:
|
|
|
|
|
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
|
|
|
|
|
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
|
|
|
|
|
; CHECK-NEXT: mov w8, v0.s[1]
|
|
|
|
|
; CHECK-NEXT: fmov w9, s0
|
|
|
|
|
; CHECK-NEXT: and w0, w9, w8
|
|
|
|
|
; CHECK-NEXT: ret
|
2019-06-13 17:37:38 +08:00
|
|
|
%b = call i24 @llvm.experimental.vector.reduce.and.v4i24(<4 x i24> %a)
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
|
|
|
ret i24 %b
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i128 @test_v2i128(<2 x i128> %a) nounwind {
|
|
|
|
|
; CHECK-LABEL: test_v2i128:
|
|
|
|
|
; CHECK: // %bb.0:
|
|
|
|
|
; CHECK-NEXT: and x0, x0, x2
|
|
|
|
|
; CHECK-NEXT: and x1, x1, x3
|
|
|
|
|
; CHECK-NEXT: ret
|
2019-06-13 17:37:38 +08:00
|
|
|
%b = call i128 @llvm.experimental.vector.reduce.and.v2i128(<2 x i128> %a)
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
|
|
|
ret i128 %b
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define i32 @test_v16i32(<16 x i32> %a) nounwind {
|
|
|
|
|
; CHECK-LABEL: test_v16i32:
|
|
|
|
|
; CHECK: // %bb.0:
|
|
|
|
|
; CHECK-NEXT: and v1.16b, v1.16b, v3.16b
|
|
|
|
|
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
|
|
|
|
|
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
|
|
|
|
|
; CHECK-NEXT: ext v1.16b, v0.16b, v0.16b, #8
|
|
|
|
|
; CHECK-NEXT: and v0.8b, v0.8b, v1.8b
|
|
|
|
|
; CHECK-NEXT: mov w8, v0.s[1]
|
|
|
|
|
; CHECK-NEXT: fmov w9, s0
|
|
|
|
|
; CHECK-NEXT: and w0, w9, w8
|
|
|
|
|
; CHECK-NEXT: ret
|
2019-06-13 17:37:38 +08:00
|
|
|
%b = call i32 @llvm.experimental.vector.reduce.and.v16i32(<16 x i32> %a)
|
[SDAG][AArch64] Legalize VECREDUCE
Fixes https://bugs.llvm.org/show_bug.cgi?id=36796.
Implement basic legalizations (PromoteIntRes, PromoteIntOp,
ExpandIntRes, ScalarizeVecOp, WidenVecOp) for VECREDUCE opcodes.
There are more legalizations missing (esp float legalizations),
but there's no way to test them right now, so I'm not adding them.
This also includes a few more changes to make this work somewhat
reasonably:
* Add support for expanding VECREDUCE in SDAG. Usually
experimental.vector.reduce is expanded prior to codegen, but if the
target does have native vector reduce, it may of course still be
necessary to expand due to legalization issues. This uses a shuffle
reduction if possible, followed by a naive scalar reduction.
* Allow the result type of integer VECREDUCE to be larger than the
vector element type. For example we need to be able to reduce a v8i8
into an (nominally) i32 result type on AArch64.
* Use the vector operand type rather than the scalar result type to
determine the action, so we can control exactly which vector types are
supported. Also change the legalize vector op code to handle
operations that only have vector operands, but no vector results, as
is the case for VECREDUCE.
* Default VECREDUCE to Expand. On AArch64 (only target using VECREDUCE),
explicitly specify for which vector types the reductions are supported.
This does not handle anything related to VECREDUCE_STRICT_*.
Differential Revision: https://reviews.llvm.org/D58015
llvm-svn: 355860
2019-03-12 04:22:13 +08:00
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ret i32 %b
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}
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