2015-11-24 05:33:58 +08:00
|
|
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
2017-06-27 02:20:46 +08:00
|
|
|
; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefix=X86
|
|
|
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse3 | FileCheck %s --check-prefix=X64
|
2009-08-16 01:05:03 +08:00
|
|
|
|
2017-06-27 02:20:46 +08:00
|
|
|
; These are tests for SSE3 codegen.
|
2009-01-29 07:11:14 +08:00
|
|
|
|
|
|
|
|
; Test for v8xi16 lowering where we extract the first element of the vector and
|
|
|
|
|
; placed it in the second element of the result.
|
|
|
|
|
|
2009-08-16 01:21:44 +08:00
|
|
|
define void @t0(<8 x i16>* %dest, <8 x i16>* %old) nounwind {
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-LABEL: t0:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X86: # %bb.0: # %entry
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
|
|
|
; X86-NEXT: movl $1, %edx
|
|
|
|
|
; X86-NEXT: movd %edx, %xmm0
|
|
|
|
|
; X86-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
|
|
|
|
|
; X86-NEXT: movdqa %xmm0, (%eax)
|
|
|
|
|
; X86-NEXT: retl
|
|
|
|
|
;
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-LABEL: t0:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64: # %bb.0: # %entry
|
2014-11-19 18:06:49 +08:00
|
|
|
; X64-NEXT: movl $1, %eax
|
|
|
|
|
; X64-NEXT: movd %eax, %xmm0
|
[x86] Enable the new vector shuffle lowering by default.
Update the entire regression test suite for the new shuffles. Remove
most of the old testing which was devoted to the old shuffle lowering
path and is no longer relevant really. Also remove a few other random
tests that only really exercised shuffles and only incidently or without
any interesting aspects to them.
Benchmarking that I have done shows a few small regressions with this on
LNT, zero measurable regressions on real, large applications, and for
several benchmarks where the loop vectorizer fires in the hot path it
shows 5% to 40% improvements for SSE2 and SSE3 code running on Sandy
Bridge machines. Running on AMD machines shows even more dramatic
improvements.
When using newer ISA vector extensions the gains are much more modest,
but the code is still better on the whole. There are a few regressions
being tracked (PR21137, PR21138, PR21139) but by and large this is
expected to be a win for x86 generated code performance.
It is also more correct than the code it replaces. I have fuzz tested
this extensively with ISA extensions up through AVX2 and found no
crashes or miscompiles (yet...). The old lowering had a few miscompiles
and crashers after a somewhat smaller amount of fuzz testing.
There is one significant area where the new code path lags behind and
that is in AVX-512 support. However, there was *extremely little*
support for that already and so this isn't a significant step backwards
and the new framework will probably make it easier to implement lowering
that uses the full power of AVX-512's table-based shuffle+blend (IMO).
Many thanks to Quentin, Andrea, Robert, and others for benchmarking
assistance. Thanks to Adam and others for help with AVX-512. Thanks to
Hal, Eric, and *many* others for answering my incessant questions about
how the backend actually works. =]
I will leave the old code path in the tree until the 3 PRs above are at
least resolved to folks' satisfaction. Then I will rip it (and 1000s of
lines of code) out. =] I don't expect this flag to stay around for very
long. It may not survive next week.
llvm-svn: 219046
2014-10-04 11:52:55 +08:00
|
|
|
; X64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[1],mem[1],xmm0[2],mem[2],xmm0[3],mem[3]
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-NEXT: movdqa %xmm0, (%rdi)
|
|
|
|
|
; X64-NEXT: retq
|
2009-01-29 07:11:14 +08:00
|
|
|
entry:
|
2015-02-28 05:17:42 +08:00
|
|
|
%tmp3 = load <8 x i16>, <8 x i16>* %old
|
2009-08-16 01:05:03 +08:00
|
|
|
%tmp6 = shufflevector <8 x i16> %tmp3,
|
2014-11-19 18:06:49 +08:00
|
|
|
<8 x i16> < i16 1, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef, i16 undef >,
|
2009-08-16 01:05:03 +08:00
|
|
|
<8 x i32> < i32 8, i32 0, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef >
|
|
|
|
|
store <8 x i16> %tmp6, <8 x i16>* %dest
|
2009-01-29 07:11:14 +08:00
|
|
|
ret void
|
2009-08-16 01:21:44 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <8 x i16> @t1(<8 x i16>* %A, <8 x i16>* %B) nounwind {
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-LABEL: t1:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X86: # %bb.0:
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
|
|
|
; X86-NEXT: movaps {{.*#+}} xmm0 = [0,65535,65535,65535,65535,65535,65535,65535]
|
|
|
|
|
; X86-NEXT: movaps %xmm0, %xmm1
|
|
|
|
|
; X86-NEXT: andnps (%ecx), %xmm1
|
|
|
|
|
; X86-NEXT: andps (%eax), %xmm0
|
|
|
|
|
; X86-NEXT: orps %xmm1, %xmm0
|
|
|
|
|
; X86-NEXT: retl
|
|
|
|
|
;
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-LABEL: t1:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64: # %bb.0:
|
2015-02-19 18:46:52 +08:00
|
|
|
; X64-NEXT: movaps {{.*#+}} xmm0 = [0,65535,65535,65535,65535,65535,65535,65535]
|
|
|
|
|
; X64-NEXT: movaps %xmm0, %xmm1
|
|
|
|
|
; X64-NEXT: andnps (%rsi), %xmm1
|
|
|
|
|
; X64-NEXT: andps (%rdi), %xmm0
|
|
|
|
|
; X64-NEXT: orps %xmm1, %xmm0
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%tmp1 = load <8 x i16>, <8 x i16>* %A
|
|
|
|
|
%tmp2 = load <8 x i16>, <8 x i16>* %B
|
2009-08-16 01:21:44 +08:00
|
|
|
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> < i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 >
|
|
|
|
|
ret <8 x i16> %tmp3
|
2013-07-26 02:35:14 +08:00
|
|
|
|
2009-08-16 01:21:44 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <8 x i16> @t2(<8 x i16> %A, <8 x i16> %B) nounwind {
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-LABEL: t2:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X86: # %bb.0:
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-NEXT: movdqa {{.*#+}} xmm2 = [0,65535,65535,0,65535,65535,65535,65535]
|
|
|
|
|
; X86-NEXT: pand %xmm2, %xmm0
|
|
|
|
|
; X86-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[1,1,2,1,4,5,6,7]
|
|
|
|
|
; X86-NEXT: pandn %xmm1, %xmm2
|
|
|
|
|
; X86-NEXT: por %xmm2, %xmm0
|
|
|
|
|
; X86-NEXT: retl
|
|
|
|
|
;
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-LABEL: t2:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64: # %bb.0:
|
2015-02-19 21:56:49 +08:00
|
|
|
; X64-NEXT: movdqa {{.*#+}} xmm2 = [0,65535,65535,0,65535,65535,65535,65535]
|
|
|
|
|
; X64-NEXT: pand %xmm2, %xmm0
|
|
|
|
|
; X64-NEXT: pshuflw {{.*#+}} xmm1 = xmm1[1,1,2,1,4,5,6,7]
|
|
|
|
|
; X64-NEXT: pandn %xmm1, %xmm2
|
|
|
|
|
; X64-NEXT: por %xmm2, %xmm0
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-NEXT: retq
|
2009-08-16 01:21:44 +08:00
|
|
|
%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 9, i32 1, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7 >
|
|
|
|
|
ret <8 x i16> %tmp
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <8 x i16> @t3(<8 x i16> %A, <8 x i16> %B) nounwind {
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-LABEL: t3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X86: # %bb.0:
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,0]
|
|
|
|
|
; X86-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6,5]
|
|
|
|
|
; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,0]
|
|
|
|
|
; X86-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,3,2,1,4,5,6,7]
|
|
|
|
|
; X86-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
|
|
|
|
|
; X86-NEXT: retl
|
|
|
|
|
;
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-LABEL: t3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64: # %bb.0:
|
[x86] Enable the new vector shuffle lowering by default.
Update the entire regression test suite for the new shuffles. Remove
most of the old testing which was devoted to the old shuffle lowering
path and is no longer relevant really. Also remove a few other random
tests that only really exercised shuffles and only incidently or without
any interesting aspects to them.
Benchmarking that I have done shows a few small regressions with this on
LNT, zero measurable regressions on real, large applications, and for
several benchmarks where the loop vectorizer fires in the hot path it
shows 5% to 40% improvements for SSE2 and SSE3 code running on Sandy
Bridge machines. Running on AMD machines shows even more dramatic
improvements.
When using newer ISA vector extensions the gains are much more modest,
but the code is still better on the whole. There are a few regressions
being tracked (PR21137, PR21138, PR21139) but by and large this is
expected to be a win for x86 generated code performance.
It is also more correct than the code it replaces. I have fuzz tested
this extensively with ISA extensions up through AVX2 and found no
crashes or miscompiles (yet...). The old lowering had a few miscompiles
and crashers after a somewhat smaller amount of fuzz testing.
There is one significant area where the new code path lags behind and
that is in AVX-512 support. However, there was *extremely little*
support for that already and so this isn't a significant step backwards
and the new framework will probably make it easier to implement lowering
that uses the full power of AVX-512's table-based shuffle+blend (IMO).
Many thanks to Quentin, Andrea, Robert, and others for benchmarking
assistance. Thanks to Adam and others for help with AVX-512. Thanks to
Hal, Eric, and *many* others for answering my incessant questions about
how the backend actually works. =]
I will leave the old code path in the tree until the 3 PRs above are at
least resolved to folks' satisfaction. Then I will rip it (and 1000s of
lines of code) out. =] I don't expect this flag to stay around for very
long. It may not survive next week.
llvm-svn: 219046
2014-10-04 11:52:55 +08:00
|
|
|
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,0]
|
|
|
|
|
; X64-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5,6,5]
|
|
|
|
|
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,0]
|
|
|
|
|
; X64-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,3,2,1,4,5,6,7]
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4]
|
|
|
|
|
; X64-NEXT: retq
|
2009-08-16 01:21:44 +08:00
|
|
|
%tmp = shufflevector <8 x i16> %A, <8 x i16> %A, <8 x i32> < i32 8, i32 3, i32 2, i32 13, i32 7, i32 6, i32 5, i32 4 >
|
|
|
|
|
ret <8 x i16> %tmp
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind {
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-LABEL: t4:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X86: # %bb.0:
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
|
|
|
|
|
; X86-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,6,5,4,7]
|
|
|
|
|
; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,0]
|
|
|
|
|
; X86-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,7,4,7]
|
|
|
|
|
; X86-NEXT: retl
|
|
|
|
|
;
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-LABEL: t4:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64: # %bb.0:
|
[x86] Enable the new vector shuffle lowering by default.
Update the entire regression test suite for the new shuffles. Remove
most of the old testing which was devoted to the old shuffle lowering
path and is no longer relevant really. Also remove a few other random
tests that only really exercised shuffles and only incidently or without
any interesting aspects to them.
Benchmarking that I have done shows a few small regressions with this on
LNT, zero measurable regressions on real, large applications, and for
several benchmarks where the loop vectorizer fires in the hot path it
shows 5% to 40% improvements for SSE2 and SSE3 code running on Sandy
Bridge machines. Running on AMD machines shows even more dramatic
improvements.
When using newer ISA vector extensions the gains are much more modest,
but the code is still better on the whole. There are a few regressions
being tracked (PR21137, PR21138, PR21139) but by and large this is
expected to be a win for x86 generated code performance.
It is also more correct than the code it replaces. I have fuzz tested
this extensively with ISA extensions up through AVX2 and found no
crashes or miscompiles (yet...). The old lowering had a few miscompiles
and crashers after a somewhat smaller amount of fuzz testing.
There is one significant area where the new code path lags behind and
that is in AVX-512 support. However, there was *extremely little*
support for that already and so this isn't a significant step backwards
and the new framework will probably make it easier to implement lowering
that uses the full power of AVX-512's table-based shuffle+blend (IMO).
Many thanks to Quentin, Andrea, Robert, and others for benchmarking
assistance. Thanks to Adam and others for help with AVX-512. Thanks to
Hal, Eric, and *many* others for answering my incessant questions about
how the backend actually works. =]
I will leave the old code path in the tree until the 3 PRs above are at
least resolved to folks' satisfaction. Then I will rip it (and 1000s of
lines of code) out. =] I don't expect this flag to stay around for very
long. It may not survive next week.
llvm-svn: 219046
2014-10-04 11:52:55 +08:00
|
|
|
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,1,0,3]
|
|
|
|
|
; X64-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,6,5,4,7]
|
|
|
|
|
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,0]
|
|
|
|
|
; X64-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,5,7,4,7]
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-NEXT: retq
|
2009-08-16 01:21:44 +08:00
|
|
|
%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 7, i32 2, i32 3, i32 1, i32 5, i32 6, i32 5 >
|
|
|
|
|
ret <8 x i16> %tmp
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <8 x i16> @t5(<8 x i16> %A, <8 x i16> %B) nounwind {
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-LABEL: t5:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X86: # %bb.0:
|
2017-09-18 11:29:54 +08:00
|
|
|
; X86-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
|
|
|
|
|
; X86-NEXT: movaps %xmm1, %xmm0
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-NEXT: retl
|
|
|
|
|
;
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-LABEL: t5:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64: # %bb.0:
|
2017-09-18 11:29:54 +08:00
|
|
|
; X64-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1]
|
|
|
|
|
; X64-NEXT: movaps %xmm1, %xmm0
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-NEXT: retq
|
2009-08-16 01:21:44 +08:00
|
|
|
%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 8, i32 9, i32 0, i32 1, i32 10, i32 11, i32 2, i32 3 >
|
|
|
|
|
ret <8 x i16> %tmp
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <8 x i16> @t6(<8 x i16> %A, <8 x i16> %B) nounwind {
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-LABEL: t6:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X86: # %bb.0:
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
|
|
|
|
|
; X86-NEXT: retl
|
|
|
|
|
;
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-LABEL: t6:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64: # %bb.0:
|
2015-02-19 18:46:52 +08:00
|
|
|
; X64-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3]
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-NEXT: retq
|
2009-08-16 01:21:44 +08:00
|
|
|
%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 8, i32 9, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 >
|
|
|
|
|
ret <8 x i16> %tmp
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <8 x i16> @t7(<8 x i16> %A, <8 x i16> %B) nounwind {
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-LABEL: t7:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X86: # %bb.0:
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,3,2,4,5,6,7]
|
|
|
|
|
; X86-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,4,7]
|
|
|
|
|
; X86-NEXT: retl
|
|
|
|
|
;
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-LABEL: t7:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64: # %bb.0:
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,0,3,2,4,5,6,7]
|
|
|
|
|
; X64-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,4,7]
|
|
|
|
|
; X64-NEXT: retq
|
2009-08-16 01:21:44 +08:00
|
|
|
%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 0, i32 3, i32 2, i32 4, i32 6, i32 4, i32 7 >
|
|
|
|
|
ret <8 x i16> %tmp
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define void @t8(<2 x i64>* %res, <2 x i64>* %A) nounwind {
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-LABEL: t8:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X86: # %bb.0:
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
|
|
|
; X86-NEXT: pshuflw {{.*#+}} xmm0 = mem[2,1,0,3,4,5,6,7]
|
|
|
|
|
; X86-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,6,5,4,7]
|
|
|
|
|
; X86-NEXT: movdqa %xmm0, (%eax)
|
|
|
|
|
; X86-NEXT: retl
|
|
|
|
|
;
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-LABEL: t8:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64: # %bb.0:
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-NEXT: pshuflw {{.*#+}} xmm0 = mem[2,1,0,3,4,5,6,7]
|
|
|
|
|
; X64-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,6,5,4,7]
|
|
|
|
|
; X64-NEXT: movdqa %xmm0, (%rdi)
|
|
|
|
|
; X64-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%tmp = load <2 x i64>, <2 x i64>* %A
|
2009-08-16 01:21:44 +08:00
|
|
|
%tmp.upgrd.1 = bitcast <2 x i64> %tmp to <8 x i16>
|
|
|
|
|
%tmp0 = extractelement <8 x i16> %tmp.upgrd.1, i32 0
|
|
|
|
|
%tmp1 = extractelement <8 x i16> %tmp.upgrd.1, i32 1
|
|
|
|
|
%tmp2 = extractelement <8 x i16> %tmp.upgrd.1, i32 2
|
|
|
|
|
%tmp3 = extractelement <8 x i16> %tmp.upgrd.1, i32 3
|
|
|
|
|
%tmp4 = extractelement <8 x i16> %tmp.upgrd.1, i32 4
|
|
|
|
|
%tmp5 = extractelement <8 x i16> %tmp.upgrd.1, i32 5
|
|
|
|
|
%tmp6 = extractelement <8 x i16> %tmp.upgrd.1, i32 6
|
|
|
|
|
%tmp7 = extractelement <8 x i16> %tmp.upgrd.1, i32 7
|
|
|
|
|
%tmp8 = insertelement <8 x i16> undef, i16 %tmp2, i32 0
|
|
|
|
|
%tmp9 = insertelement <8 x i16> %tmp8, i16 %tmp1, i32 1
|
|
|
|
|
%tmp10 = insertelement <8 x i16> %tmp9, i16 %tmp0, i32 2
|
|
|
|
|
%tmp11 = insertelement <8 x i16> %tmp10, i16 %tmp3, i32 3
|
|
|
|
|
%tmp12 = insertelement <8 x i16> %tmp11, i16 %tmp6, i32 4
|
|
|
|
|
%tmp13 = insertelement <8 x i16> %tmp12, i16 %tmp5, i32 5
|
|
|
|
|
%tmp14 = insertelement <8 x i16> %tmp13, i16 %tmp4, i32 6
|
|
|
|
|
%tmp15 = insertelement <8 x i16> %tmp14, i16 %tmp7, i32 7
|
|
|
|
|
%tmp15.upgrd.2 = bitcast <8 x i16> %tmp15 to <2 x i64>
|
|
|
|
|
store <2 x i64> %tmp15.upgrd.2, <2 x i64>* %res
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define void @t9(<4 x float>* %r, <2 x i32>* %A) nounwind {
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-LABEL: t9:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X86: # %bb.0:
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
|
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
|
|
|
|
|
; X86-NEXT: movapd (%ecx), %xmm0
|
|
|
|
|
; X86-NEXT: movhpd {{.*#+}} xmm0 = xmm0[0],mem[0]
|
|
|
|
|
; X86-NEXT: movapd %xmm0, (%ecx)
|
|
|
|
|
; X86-NEXT: retl
|
|
|
|
|
;
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-LABEL: t9:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64: # %bb.0:
|
[x86] Enable the new vector shuffle lowering by default.
Update the entire regression test suite for the new shuffles. Remove
most of the old testing which was devoted to the old shuffle lowering
path and is no longer relevant really. Also remove a few other random
tests that only really exercised shuffles and only incidently or without
any interesting aspects to them.
Benchmarking that I have done shows a few small regressions with this on
LNT, zero measurable regressions on real, large applications, and for
several benchmarks where the loop vectorizer fires in the hot path it
shows 5% to 40% improvements for SSE2 and SSE3 code running on Sandy
Bridge machines. Running on AMD machines shows even more dramatic
improvements.
When using newer ISA vector extensions the gains are much more modest,
but the code is still better on the whole. There are a few regressions
being tracked (PR21137, PR21138, PR21139) but by and large this is
expected to be a win for x86 generated code performance.
It is also more correct than the code it replaces. I have fuzz tested
this extensively with ISA extensions up through AVX2 and found no
crashes or miscompiles (yet...). The old lowering had a few miscompiles
and crashers after a somewhat smaller amount of fuzz testing.
There is one significant area where the new code path lags behind and
that is in AVX-512 support. However, there was *extremely little*
support for that already and so this isn't a significant step backwards
and the new framework will probably make it easier to implement lowering
that uses the full power of AVX-512's table-based shuffle+blend (IMO).
Many thanks to Quentin, Andrea, Robert, and others for benchmarking
assistance. Thanks to Adam and others for help with AVX-512. Thanks to
Hal, Eric, and *many* others for answering my incessant questions about
how the backend actually works. =]
I will leave the old code path in the tree until the 3 PRs above are at
least resolved to folks' satisfaction. Then I will rip it (and 1000s of
lines of code) out. =] I don't expect this flag to stay around for very
long. It may not survive next week.
llvm-svn: 219046
2014-10-04 11:52:55 +08:00
|
|
|
; X64-NEXT: movapd (%rdi), %xmm0
|
2016-06-22 20:58:15 +08:00
|
|
|
; X64-NEXT: movhpd {{.*#+}} xmm0 = xmm0[0],mem[0]
|
[x86] Enable the new vector shuffle lowering by default.
Update the entire regression test suite for the new shuffles. Remove
most of the old testing which was devoted to the old shuffle lowering
path and is no longer relevant really. Also remove a few other random
tests that only really exercised shuffles and only incidently or without
any interesting aspects to them.
Benchmarking that I have done shows a few small regressions with this on
LNT, zero measurable regressions on real, large applications, and for
several benchmarks where the loop vectorizer fires in the hot path it
shows 5% to 40% improvements for SSE2 and SSE3 code running on Sandy
Bridge machines. Running on AMD machines shows even more dramatic
improvements.
When using newer ISA vector extensions the gains are much more modest,
but the code is still better on the whole. There are a few regressions
being tracked (PR21137, PR21138, PR21139) but by and large this is
expected to be a win for x86 generated code performance.
It is also more correct than the code it replaces. I have fuzz tested
this extensively with ISA extensions up through AVX2 and found no
crashes or miscompiles (yet...). The old lowering had a few miscompiles
and crashers after a somewhat smaller amount of fuzz testing.
There is one significant area where the new code path lags behind and
that is in AVX-512 support. However, there was *extremely little*
support for that already and so this isn't a significant step backwards
and the new framework will probably make it easier to implement lowering
that uses the full power of AVX-512's table-based shuffle+blend (IMO).
Many thanks to Quentin, Andrea, Robert, and others for benchmarking
assistance. Thanks to Adam and others for help with AVX-512. Thanks to
Hal, Eric, and *many* others for answering my incessant questions about
how the backend actually works. =]
I will leave the old code path in the tree until the 3 PRs above are at
least resolved to folks' satisfaction. Then I will rip it (and 1000s of
lines of code) out. =] I don't expect this flag to stay around for very
long. It may not survive next week.
llvm-svn: 219046
2014-10-04 11:52:55 +08:00
|
|
|
; X64-NEXT: movapd %xmm0, (%rdi)
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
%tmp = load <4 x float>, <4 x float>* %r
|
2009-08-16 01:21:44 +08:00
|
|
|
%tmp.upgrd.3 = bitcast <2 x i32>* %A to double*
|
2015-02-28 05:17:42 +08:00
|
|
|
%tmp.upgrd.4 = load double, double* %tmp.upgrd.3
|
2009-08-16 01:21:44 +08:00
|
|
|
%tmp.upgrd.5 = insertelement <2 x double> undef, double %tmp.upgrd.4, i32 0
|
2013-07-26 02:35:14 +08:00
|
|
|
%tmp5 = insertelement <2 x double> %tmp.upgrd.5, double undef, i32 1
|
|
|
|
|
%tmp6 = bitcast <2 x double> %tmp5 to <4 x float>
|
|
|
|
|
%tmp.upgrd.6 = extractelement <4 x float> %tmp, i32 0
|
|
|
|
|
%tmp7 = extractelement <4 x float> %tmp, i32 1
|
|
|
|
|
%tmp8 = extractelement <4 x float> %tmp6, i32 0
|
|
|
|
|
%tmp9 = extractelement <4 x float> %tmp6, i32 1
|
|
|
|
|
%tmp10 = insertelement <4 x float> undef, float %tmp.upgrd.6, i32 0
|
2009-08-16 01:21:44 +08:00
|
|
|
%tmp11 = insertelement <4 x float> %tmp10, float %tmp7, i32 1
|
|
|
|
|
%tmp12 = insertelement <4 x float> %tmp11, float %tmp8, i32 2
|
|
|
|
|
%tmp13 = insertelement <4 x float> %tmp12, float %tmp9, i32 3
|
|
|
|
|
store <4 x float> %tmp13, <4 x float>* %r
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
; FIXME: This testcase produces icky code. It can be made much better!
|
|
|
|
|
; PR2585
|
|
|
|
|
|
|
|
|
|
@g1 = external constant <4 x i32>
|
|
|
|
|
@g2 = external constant <4 x i16>
|
|
|
|
|
|
2014-10-03 09:37:58 +08:00
|
|
|
define void @t10() nounwind {
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-LABEL: t10:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X86: # %bb.0:
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-NEXT: pshuflw {{.*#+}} xmm0 = mem[0,2,2,3,4,5,6,7]
|
|
|
|
|
; X86-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
|
|
|
|
|
; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
|
|
|
|
|
; X86-NEXT: movq %xmm0, g2
|
|
|
|
|
; X86-NEXT: retl
|
|
|
|
|
;
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-LABEL: t10:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64: # %bb.0:
|
[x86] Enable the new vector shuffle lowering by default.
Update the entire regression test suite for the new shuffles. Remove
most of the old testing which was devoted to the old shuffle lowering
path and is no longer relevant really. Also remove a few other random
tests that only really exercised shuffles and only incidently or without
any interesting aspects to them.
Benchmarking that I have done shows a few small regressions with this on
LNT, zero measurable regressions on real, large applications, and for
several benchmarks where the loop vectorizer fires in the hot path it
shows 5% to 40% improvements for SSE2 and SSE3 code running on Sandy
Bridge machines. Running on AMD machines shows even more dramatic
improvements.
When using newer ISA vector extensions the gains are much more modest,
but the code is still better on the whole. There are a few regressions
being tracked (PR21137, PR21138, PR21139) but by and large this is
expected to be a win for x86 generated code performance.
It is also more correct than the code it replaces. I have fuzz tested
this extensively with ISA extensions up through AVX2 and found no
crashes or miscompiles (yet...). The old lowering had a few miscompiles
and crashers after a somewhat smaller amount of fuzz testing.
There is one significant area where the new code path lags behind and
that is in AVX-512 support. However, there was *extremely little*
support for that already and so this isn't a significant step backwards
and the new framework will probably make it easier to implement lowering
that uses the full power of AVX-512's table-based shuffle+blend (IMO).
Many thanks to Quentin, Andrea, Robert, and others for benchmarking
assistance. Thanks to Adam and others for help with AVX-512. Thanks to
Hal, Eric, and *many* others for answering my incessant questions about
how the backend actually works. =]
I will leave the old code path in the tree until the 3 PRs above are at
least resolved to folks' satisfaction. Then I will rip it (and 1000s of
lines of code) out. =] I don't expect this flag to stay around for very
long. It may not survive next week.
llvm-svn: 219046
2014-10-04 11:52:55 +08:00
|
|
|
; X64-NEXT: pshuflw {{.*#+}} xmm0 = mem[0,2,2,3,4,5,6,7]
|
|
|
|
|
; X64-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,6,6,7]
|
|
|
|
|
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3]
|
2017-06-27 02:20:46 +08:00
|
|
|
; X64-NEXT: movq %xmm0, {{.*}}(%rip)
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-NEXT: retq
|
2015-02-28 05:17:42 +08:00
|
|
|
load <4 x i32>, <4 x i32>* @g1, align 16
|
2014-10-03 09:37:58 +08:00
|
|
|
bitcast <4 x i32> %1 to <8 x i16>
|
|
|
|
|
shufflevector <8 x i16> %2, <8 x i16> undef, <8 x i32> < i32 0, i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 undef, i32 undef >
|
|
|
|
|
bitcast <8 x i16> %3 to <2 x i64>
|
|
|
|
|
extractelement <2 x i64> %4, i32 0
|
|
|
|
|
bitcast i64 %5 to <4 x i16>
|
|
|
|
|
store <4 x i16> %6, <4 x i16>* @g2, align 8
|
|
|
|
|
ret void
|
2009-08-16 01:21:44 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; Pack various elements via shuffles.
|
|
|
|
|
define <8 x i16> @t11(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-LABEL: t11:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X86: # %bb.0: # %entry
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-NEXT: psrld $16, %xmm0
|
|
|
|
|
; X86-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
|
|
|
|
|
; X86-NEXT: retl
|
|
|
|
|
;
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-LABEL: t11:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64: # %bb.0: # %entry
|
2015-02-19 22:08:24 +08:00
|
|
|
; X64-NEXT: psrld $16, %xmm0
|
[x86] Enable the new vector shuffle lowering by default.
Update the entire regression test suite for the new shuffles. Remove
most of the old testing which was devoted to the old shuffle lowering
path and is no longer relevant really. Also remove a few other random
tests that only really exercised shuffles and only incidently or without
any interesting aspects to them.
Benchmarking that I have done shows a few small regressions with this on
LNT, zero measurable regressions on real, large applications, and for
several benchmarks where the loop vectorizer fires in the hot path it
shows 5% to 40% improvements for SSE2 and SSE3 code running on Sandy
Bridge machines. Running on AMD machines shows even more dramatic
improvements.
When using newer ISA vector extensions the gains are much more modest,
but the code is still better on the whole. There are a few regressions
being tracked (PR21137, PR21138, PR21139) but by and large this is
expected to be a win for x86 generated code performance.
It is also more correct than the code it replaces. I have fuzz tested
this extensively with ISA extensions up through AVX2 and found no
crashes or miscompiles (yet...). The old lowering had a few miscompiles
and crashers after a somewhat smaller amount of fuzz testing.
There is one significant area where the new code path lags behind and
that is in AVX-512 support. However, there was *extremely little*
support for that already and so this isn't a significant step backwards
and the new framework will probably make it easier to implement lowering
that uses the full power of AVX-512's table-based shuffle+blend (IMO).
Many thanks to Quentin, Andrea, Robert, and others for benchmarking
assistance. Thanks to Adam and others for help with AVX-512. Thanks to
Hal, Eric, and *many* others for answering my incessant questions about
how the backend actually works. =]
I will leave the old code path in the tree until the 3 PRs above are at
least resolved to folks' satisfaction. Then I will rip it (and 1000s of
lines of code) out. =] I don't expect this flag to stay around for very
long. It may not survive next week.
llvm-svn: 219046
2014-10-04 11:52:55 +08:00
|
|
|
; X64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-NEXT: retq
|
2009-08-16 01:21:44 +08:00
|
|
|
entry:
|
|
|
|
|
%tmp7 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 1, i32 8, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
|
|
|
|
|
ret <8 x i16> %tmp7
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <8 x i16> @t12(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-LABEL: t12:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X86: # %bb.0: # %entry
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
|
|
|
|
|
; X86-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
|
|
|
|
|
; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,3,3]
|
|
|
|
|
; X86-NEXT: retl
|
|
|
|
|
;
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-LABEL: t12:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64: # %bb.0: # %entry
|
2015-02-19 23:06:13 +08:00
|
|
|
; X64-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3]
|
|
|
|
|
; X64-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,2,2,3,4,5,6,7]
|
2016-06-28 16:08:15 +08:00
|
|
|
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,3,3]
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-NEXT: retq
|
2009-08-16 01:21:44 +08:00
|
|
|
entry:
|
|
|
|
|
%tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 0, i32 1, i32 undef, i32 undef, i32 3, i32 11, i32 undef , i32 undef >
|
|
|
|
|
ret <8 x i16> %tmp9
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <8 x i16> @t13(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-LABEL: t13:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X86: # %bb.0: # %entry
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
|
|
|
|
|
; X86-NEXT: pshuflw {{.*#+}} xmm0 = xmm1[0,2,2,3,4,5,6,7]
|
|
|
|
|
; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,3,3]
|
|
|
|
|
; X86-NEXT: retl
|
|
|
|
|
;
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-LABEL: t13:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64: # %bb.0: # %entry
|
2015-02-19 23:06:13 +08:00
|
|
|
; X64-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3]
|
|
|
|
|
; X64-NEXT: pshuflw {{.*#+}} xmm0 = xmm1[0,2,2,3,4,5,6,7]
|
2016-06-28 16:08:15 +08:00
|
|
|
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,3,3]
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-NEXT: retq
|
2009-08-16 01:21:44 +08:00
|
|
|
entry:
|
|
|
|
|
%tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 8, i32 9, i32 undef, i32 undef, i32 11, i32 3, i32 undef , i32 undef >
|
|
|
|
|
ret <8 x i16> %tmp9
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
define <8 x i16> @t14(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-LABEL: t14:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X86: # %bb.0: # %entry
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-NEXT: psrlq $16, %xmm0
|
|
|
|
|
; X86-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
|
|
|
|
|
; X86-NEXT: movdqa %xmm1, %xmm0
|
|
|
|
|
; X86-NEXT: retl
|
|
|
|
|
;
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-LABEL: t14:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64: # %bb.0: # %entry
|
2015-02-19 22:08:24 +08:00
|
|
|
; X64-NEXT: psrlq $16, %xmm0
|
|
|
|
|
; X64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0]
|
|
|
|
|
; X64-NEXT: movdqa %xmm1, %xmm0
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-NEXT: retq
|
2009-08-16 01:21:44 +08:00
|
|
|
entry:
|
|
|
|
|
%tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 8, i32 9, i32 undef, i32 undef, i32 undef, i32 2, i32 undef , i32 undef >
|
|
|
|
|
ret <8 x i16> %tmp9
|
|
|
|
|
}
|
|
|
|
|
|
2011-11-10 15:43:16 +08:00
|
|
|
; FIXME: t15 is worse off from disabling of scheduler 2-address hack.
|
2009-08-16 01:21:44 +08:00
|
|
|
define <8 x i16> @t15(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-LABEL: t15:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X86: # %bb.0: # %entry
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
|
|
|
|
|
; X86-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,1,2,4,5,6,7]
|
|
|
|
|
; X86-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
|
|
|
|
; X86-NEXT: retl
|
|
|
|
|
;
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-LABEL: t15:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64: # %bb.0: # %entry
|
[x86] Enable the new vector shuffle lowering by default.
Update the entire regression test suite for the new shuffles. Remove
most of the old testing which was devoted to the old shuffle lowering
path and is no longer relevant really. Also remove a few other random
tests that only really exercised shuffles and only incidently or without
any interesting aspects to them.
Benchmarking that I have done shows a few small regressions with this on
LNT, zero measurable regressions on real, large applications, and for
several benchmarks where the loop vectorizer fires in the hot path it
shows 5% to 40% improvements for SSE2 and SSE3 code running on Sandy
Bridge machines. Running on AMD machines shows even more dramatic
improvements.
When using newer ISA vector extensions the gains are much more modest,
but the code is still better on the whole. There are a few regressions
being tracked (PR21137, PR21138, PR21139) but by and large this is
expected to be a win for x86 generated code performance.
It is also more correct than the code it replaces. I have fuzz tested
this extensively with ISA extensions up through AVX2 and found no
crashes or miscompiles (yet...). The old lowering had a few miscompiles
and crashers after a somewhat smaller amount of fuzz testing.
There is one significant area where the new code path lags behind and
that is in AVX-512 support. However, there was *extremely little*
support for that already and so this isn't a significant step backwards
and the new framework will probably make it easier to implement lowering
that uses the full power of AVX-512's table-based shuffle+blend (IMO).
Many thanks to Quentin, Andrea, Robert, and others for benchmarking
assistance. Thanks to Adam and others for help with AVX-512. Thanks to
Hal, Eric, and *many* others for answering my incessant questions about
how the backend actually works. =]
I will leave the old code path in the tree until the 3 PRs above are at
least resolved to folks' satisfaction. Then I will rip it (and 1000s of
lines of code) out. =] I don't expect this flag to stay around for very
long. It may not survive next week.
llvm-svn: 219046
2014-10-04 11:52:55 +08:00
|
|
|
; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,1,2,3]
|
2015-02-19 22:08:24 +08:00
|
|
|
; X64-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[0,1,1,2,4,5,6,7]
|
|
|
|
|
; X64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-NEXT: retq
|
2009-08-16 01:21:44 +08:00
|
|
|
entry:
|
2014-10-03 09:37:58 +08:00
|
|
|
%tmp8 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef >
|
|
|
|
|
ret <8 x i16> %tmp8
|
2009-08-16 01:21:44 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
; Test yonah where we convert a shuffle to pextrw and pinrsw
|
|
|
|
|
define <16 x i8> @t16(<16 x i8> %T0) nounwind readnone {
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-LABEL: t16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X86: # %bb.0: # %entry
|
2018-02-15 20:14:15 +08:00
|
|
|
; X86-NEXT: pslld $16, %xmm0
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-NEXT: retl
|
|
|
|
|
;
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-LABEL: t16:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64: # %bb.0: # %entry
|
2018-02-15 20:14:15 +08:00
|
|
|
; X64-NEXT: pslld $16, %xmm0
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-NEXT: retq
|
2009-08-16 01:21:44 +08:00
|
|
|
entry:
|
2014-10-03 09:37:58 +08:00
|
|
|
%tmp8 = shufflevector <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 1, i8 1, i8 1, i8 1, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 16, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
|
|
|
|
|
%tmp9 = shufflevector <16 x i8> %tmp8, <16 x i8> %T0, <16 x i32> < i32 0, i32 1, i32 2, i32 17, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
|
|
|
|
|
ret <16 x i8> %tmp9
|
2009-08-16 01:21:44 +08:00
|
|
|
}
|
2010-10-08 04:50:20 +08:00
|
|
|
|
|
|
|
|
; rdar://8520311
|
|
|
|
|
define <4 x i32> @t17() nounwind {
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-LABEL: t17:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X86: # %bb.0: # %entry
|
2018-02-17 00:22:14 +08:00
|
|
|
; X86-NEXT: movddup {{.*#+}} xmm0 = mem[0,0]
|
|
|
|
|
; X86-NEXT: andpd {{\.LCPI.*}}, %xmm0
|
2017-06-27 02:20:46 +08:00
|
|
|
; X86-NEXT: retl
|
|
|
|
|
;
|
2013-07-14 14:24:09 +08:00
|
|
|
; X64-LABEL: t17:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64: # %bb.0: # %entry
|
2018-02-17 00:22:14 +08:00
|
|
|
; X64-NEXT: movddup {{.*#+}} xmm0 = mem[0,0]
|
|
|
|
|
; X64-NEXT: andpd {{.*}}(%rip), %xmm0
|
2014-10-03 09:37:58 +08:00
|
|
|
; X64-NEXT: retq
|
|
|
|
|
entry:
|
2015-02-28 05:17:42 +08:00
|
|
|
%tmp1 = load <4 x float>, <4 x float>* undef, align 16
|
2010-10-08 04:50:20 +08:00
|
|
|
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
|
2015-02-28 05:17:42 +08:00
|
|
|
%tmp3 = load <4 x float>, <4 x float>* undef, align 16
|
2010-10-08 04:50:20 +08:00
|
|
|
%tmp4 = shufflevector <4 x float> %tmp2, <4 x float> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
|
|
|
|
|
%tmp5 = bitcast <4 x float> %tmp3 to <4 x i32>
|
|
|
|
|
%tmp6 = shufflevector <4 x i32> %tmp5, <4 x i32> undef, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
|
|
|
|
|
%tmp7 = and <4 x i32> %tmp6, <i32 undef, i32 undef, i32 -1, i32 0>
|
|
|
|
|
ret <4 x i32> %tmp7
|
|
|
|
|
}
|