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llvm-project/llvm/test/MC/AVR/inst-fmulsu.s

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[AVR] Add all of the machine code test suite Summary: This adds all of the AVR machine code tests. Reviewers: arsenm, kparzysz Subscribers: wdng, japaric Differential Revision: https://reviews.llvm.org/D26387 llvm-svn: 286417
2016-11-10 07:46:25 +08:00
; RUN: llvm-mc -triple avr -mattr=mul -show-encoding < %s | FileCheck %s
[AVR] Disassemble multiplication instructions These can often only use a limited range of registers, and apparently need special decoding support. Differential Revision: https://reviews.llvm.org/D81971
2020-06-17 05:42:43 +08:00
; RUN: llvm-mc -filetype=obj -triple avr -mattr=mul < %s | llvm-objdump -d --mattr=mul - | FileCheck -check-prefix=CHECK-INST %s
[AVR] Add all of the machine code test suite Summary: This adds all of the AVR machine code tests. Reviewers: arsenm, kparzysz Subscribers: wdng, japaric Differential Revision: https://reviews.llvm.org/D26387 llvm-svn: 286417
2016-11-10 07:46:25 +08:00
foo:
fmulsu r22, r16
fmulsu r19, r17
fmulsu r21, r23
fmulsu r23, r23
; CHECK: fmulsu r22, r16 ; encoding: [0xe8,0x03]
; CHECK: fmulsu r19, r17 ; encoding: [0xb9,0x03]
; CHECK: fmulsu r21, r23 ; encoding: [0xdf,0x03]
; CHECK: fmulsu r23, r23 ; encoding: [0xff,0x03]
[AVR] Disassemble multiplication instructions These can often only use a limited range of registers, and apparently need special decoding support. Differential Revision: https://reviews.llvm.org/D81971
2020-06-17 05:42:43 +08:00
; CHECK-INST: fmulsu r22, r16
; CHECK-INST: fmulsu r19, r17
; CHECK-INST: fmulsu r21, r23
; CHECK-INST: fmulsu r23, r23