llvm-project/llvm/test/CodeGen/X86/v-binop-widen.ll

; RUN: llc -mcpu=generic -march=x86 -mattr=+sse < %s | FileCheck %s
; CHECK: divps
; CHECK: divps
; CHECK: divss

%vec = type <9 x float>
define %vec @vecdiv( %vec %p1, %vec %p2)
{
  %result = fdiv %vec %p1, %p2
  ret %vec %result
}
Instruction scheduling itinerary for Intel Atom. Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558 2012-02-02 07:20:51 +08:00			`; RUN: llc -mcpu=generic -march=x86 -mattr=+sse < %s \| FileCheck %s`
Move v-binop-widen tests to X86 since they don't work on all platforms llvm-svn: 106562 2010-06-23 03:40:50 +08:00			`; CHECK: divps`
Change the x86 32-bit scheduler to register pressure and fix up the corresponding testcases back to the previous versions. Fixes some performance regressions only seen on 32-bit. llvm-svn: 127441 2011-03-11 09:05:58 +08:00			`; CHECK: divps`
Enable MI Sched for x86. This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750 2013-10-16 07:33:07 +08:00			`; CHECK: divss`
Fixed vector widening of binary instructions that can trap. Patch by Visa Putkinen! llvm-svn: 106038 2010-06-16 04:29:05 +08:00
			`%vec = type <9 x float>`
			`define %vec @vecdiv( %vec %p1, %vec %p2)`
			`{`
			`%result = fdiv %vec %p1, %p2`
			`ret %vec %result`
			`}`