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llvm-project/llvm/test/CodeGen/Hexagon/tstbit.ll

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UpdateTestChecks: hexagon support Summary: These tests are being affected by an upcoming patch, so having an understandable (autogenerated) diff is helpful. This target, again, prefers `-march`: ``` llvm/test/CodeGen/Hexagon$ grep -r triple | wc -l 467 llvm/test/CodeGen/Hexagon$ grep -r march | wc -l 1167 ``` Reviewers: RKSimon, kparzysz Reviewed By: kparzysz Subscribers: xbolva00, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62867 llvm-svn: 362605
2019-06-05 22:08:01 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
[Hexagon] Add more lit tests llvm-svn: 327271
2018-03-12 22:01:28 +08:00
; RUN: llc -march=hexagon < %s | FileCheck %s
; Function Attrs: nounwind readnone
define i32 @f0(i32 %a0, i32 %a1) #0 {
UpdateTestChecks: hexagon support Summary: These tests are being affected by an upcoming patch, so having an understandable (autogenerated) diff is helpful. This target, again, prefers `-march`: ``` llvm/test/CodeGen/Hexagon$ grep -r triple | wc -l 467 llvm/test/CodeGen/Hexagon$ grep -r march | wc -l 1167 ``` Reviewers: RKSimon, kparzysz Reviewed By: kparzysz Subscribers: xbolva00, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62867 llvm-svn: 362605
2019-06-05 22:08:01 +08:00
; CHECK-LABEL: f0:
; CHECK: // %bb.0: // %b0
; CHECK-NEXT: {
; CHECK-NEXT: p0 = tstbit(r0,r1)
; CHECK-NEXT: }
; CHECK-NEXT: {
; CHECK-NEXT: r0 = mux(p0,#1,#0)
; CHECK-NEXT: jumpr r31
; CHECK-NEXT: }
[Hexagon] Add more lit tests llvm-svn: 327271
2018-03-12 22:01:28 +08:00
b0:
%v0 = shl i32 1, %a1
%v1 = and i32 %v0, %a0
%v2 = icmp ne i32 %v1, 0
%v3 = zext i1 %v2 to i32
ret i32 %v3
}
attributes #0 = { nounwind readnone }