forked from OSchip/llvm-project
251 lines
8.6 KiB
LLVM
251 lines
8.6 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
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; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names \
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; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
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; assemble_acc
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declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
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define void @ass_acc(<512 x i1>* %ptr, <16 x i8> %vc) {
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; CHECK-LABEL: ass_acc:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmr v3, v2
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; CHECK-NEXT: xxlor vs0, v2, v2
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; CHECK-NEXT: xxlor vs1, v3, v3
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; CHECK-NEXT: xxlor vs2, v2, v2
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; CHECK-NEXT: xxlor vs3, v3, v3
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; CHECK-NEXT: xxmtacc acc0
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; CHECK-NEXT: xxmfacc acc0
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; CHECK-NEXT: stxv vs0, 48(r3)
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; CHECK-NEXT: stxv vs1, 32(r3)
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; CHECK-NEXT: stxv vs2, 16(r3)
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; CHECK-NEXT: stxv vs3, 0(r3)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: ass_acc:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: vmr v3, v2
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; CHECK-BE-NEXT: xxlor vs0, v2, v2
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; CHECK-BE-NEXT: xxlor vs1, v3, v3
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; CHECK-BE-NEXT: xxlor vs2, v2, v2
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; CHECK-BE-NEXT: xxlor vs3, v3, v3
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; CHECK-BE-NEXT: xxmtacc acc0
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; CHECK-BE-NEXT: xxmfacc acc0
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; CHECK-BE-NEXT: stxv vs1, 16(r3)
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; CHECK-BE-NEXT: stxv vs0, 0(r3)
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; CHECK-BE-NEXT: stxv vs3, 48(r3)
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; CHECK-BE-NEXT: stxv vs2, 32(r3)
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; CHECK-BE-NEXT: blr
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; CHECK-O0-LABEL: ass_acc:
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; CHECK-O0: # %bb.0: # %entry
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; CHECK-BE-O0-LABEL: ass_acc:
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; CHECK-BE-O0: # %bb.0: # %entry
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entry:
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%0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
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store <512 x i1> %0, <512 x i1>* %ptr, align 64
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ret void
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}
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; assemble_pair
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declare <256 x i1> @llvm.ppc.mma.assemble.pair(<16 x i8>, <16 x i8>)
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define void @ass_pair(<256 x i1>* %ptr, <16 x i8> %vc) {
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; CHECK-LABEL: ass_pair:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmr v3, v2
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; CHECK-NEXT: stxv v2, 16(r3)
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; CHECK-NEXT: stxv v3, 0(r3)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: ass_pair:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: vmr v3, v2
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; CHECK-BE-NEXT: stxv v2, 16(r3)
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; CHECK-BE-NEXT: stxv v2, 0(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = tail call <256 x i1> @llvm.ppc.mma.assemble.pair(<16 x i8> %vc, <16 x i8> %vc)
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store <256 x i1> %0, <256 x i1>* %ptr, align 32
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ret void
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}
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; xxmtacc
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declare <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1>)
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define void @int_xxmtacc(<512 x i1>* %ptr, <16 x i8> %vc) {
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; CHECK-LABEL: int_xxmtacc:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmr v3, v2
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; CHECK-NEXT: xxlor vs0, v2, v2
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; CHECK-NEXT: xxlor vs1, v3, v3
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; CHECK-NEXT: xxlor vs2, v2, v2
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; CHECK-NEXT: xxlor vs3, v3, v3
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; CHECK-NEXT: xxmtacc acc0
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; CHECK-NEXT: xxmtacc acc0
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; CHECK-NEXT: xxmfacc acc0
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; CHECK-NEXT: stxv vs0, 48(r3)
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; CHECK-NEXT: stxv vs1, 32(r3)
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; CHECK-NEXT: stxv vs2, 16(r3)
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; CHECK-NEXT: stxv vs3, 0(r3)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: int_xxmtacc:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: vmr v3, v2
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; CHECK-BE-NEXT: xxlor vs0, v2, v2
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; CHECK-BE-NEXT: xxlor vs1, v3, v3
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; CHECK-BE-NEXT: xxlor vs2, v2, v2
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; CHECK-BE-NEXT: xxlor vs3, v3, v3
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; CHECK-BE-NEXT: xxmtacc acc0
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; CHECK-BE-NEXT: xxmtacc acc0
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; CHECK-BE-NEXT: xxmfacc acc0
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; CHECK-BE-NEXT: stxv vs1, 16(r3)
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; CHECK-BE-NEXT: stxv vs0, 0(r3)
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; CHECK-BE-NEXT: stxv vs3, 48(r3)
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; CHECK-BE-NEXT: stxv vs2, 32(r3)
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; CHECK-BE-NEXT: blr
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entry:
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; One xxmtacc is generated from the call to assemble.acc then one xxmtacc is
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; generated from the call to xxmtacc then one xxmfacc is generated for the store
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%0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
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%1 = tail call <512 x i1> @llvm.ppc.mma.xxmtacc(<512 x i1> %0)
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store <512 x i1> %1, <512 x i1>* %ptr, align 64
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ret void
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}
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; xxmfacc
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declare <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1>)
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define void @int_xxmfacc(<512 x i1>* %ptr, <16 x i8> %vc) {
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; CHECK-LABEL: int_xxmfacc:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vmr v3, v2
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; CHECK-NEXT: xxlor vs0, v2, v2
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; CHECK-NEXT: xxlor vs1, v3, v3
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; CHECK-NEXT: xxlor vs2, v2, v2
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; CHECK-NEXT: xxlor vs3, v3, v3
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; CHECK-NEXT: xxmtacc acc0
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; CHECK-NEXT: xxmfacc acc0
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; CHECK-NEXT: xxmfacc acc0
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; CHECK-NEXT: stxv vs0, 48(r3)
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; CHECK-NEXT: stxv vs1, 32(r3)
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; CHECK-NEXT: stxv vs2, 16(r3)
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; CHECK-NEXT: stxv vs3, 0(r3)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: int_xxmfacc:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: vmr v3, v2
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; CHECK-BE-NEXT: xxlor vs0, v2, v2
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; CHECK-BE-NEXT: xxlor vs1, v3, v3
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; CHECK-BE-NEXT: xxlor vs2, v2, v2
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; CHECK-BE-NEXT: xxlor vs3, v3, v3
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; CHECK-BE-NEXT: xxmtacc acc0
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; CHECK-BE-NEXT: xxmfacc acc0
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; CHECK-BE-NEXT: xxmfacc acc0
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; CHECK-BE-NEXT: stxv vs1, 16(r3)
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; CHECK-BE-NEXT: stxv vs0, 0(r3)
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; CHECK-BE-NEXT: stxv vs3, 48(r3)
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; CHECK-BE-NEXT: stxv vs2, 32(r3)
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; CHECK-BE-NEXT: blr
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entry:
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; One xxmtacc is generated from the call to assemble.acc then one xxmfacc is
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; generated from the call to xxmfacc then one xxmfacc is generated for the store
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%0 = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc, <16 x i8> %vc)
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%1 = tail call <512 x i1> @llvm.ppc.mma.xxmfacc(<512 x i1> %0)
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store <512 x i1> %1, <512 x i1>* %ptr, align 64
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ret void
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}
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; xxsetaccz
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declare <512 x i1> @llvm.ppc.mma.xxsetaccz()
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define void @int_xxsetaccz(<512 x i1>* %ptr) {
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; CHECK-LABEL: int_xxsetaccz:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxsetaccz acc0
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; CHECK-NEXT: xxmfacc acc0
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; CHECK-NEXT: stxv vs0, 48(r3)
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; CHECK-NEXT: stxv vs1, 32(r3)
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; CHECK-NEXT: stxv vs2, 16(r3)
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; CHECK-NEXT: stxv vs3, 0(r3)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: int_xxsetaccz:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: xxsetaccz acc0
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; CHECK-BE-NEXT: xxmfacc acc0
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; CHECK-BE-NEXT: stxv vs1, 16(r3)
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; CHECK-BE-NEXT: stxv vs0, 0(r3)
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; CHECK-BE-NEXT: stxv vs3, 48(r3)
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; CHECK-BE-NEXT: stxv vs2, 32(r3)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
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store <512 x i1> %0, <512 x i1>* %ptr, align 64
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ret void
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}
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; disassemble_acc
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declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1>)
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define void @disass_acc(<16 x i8>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3, <16 x i8>* %ptr4) {
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; CHECK-LABEL: disass_acc:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xxsetaccz acc0
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; CHECK-NEXT: xxmfacc acc0
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; CHECK-NEXT: stxv vs3, 0(r3)
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; CHECK-NEXT: stxv vs2, 0(r4)
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; CHECK-NEXT: stxv vs1, 0(r5)
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; CHECK-NEXT: stxv vs0, 0(r6)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: disass_acc:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: xxsetaccz acc0
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; CHECK-BE-NEXT: xxmfacc acc0
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; CHECK-BE-NEXT: stxv vs0, 0(r3)
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; CHECK-BE-NEXT: stxv vs1, 0(r4)
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; CHECK-BE-NEXT: stxv vs2, 0(r5)
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; CHECK-BE-NEXT: stxv vs3, 0(r6)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = tail call <512 x i1> @llvm.ppc.mma.xxsetaccz()
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%1 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.acc(<512 x i1> %0)
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%2 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 0
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%3 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 1
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%4 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 2
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%5 = extractvalue { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } %1, 3
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store <16 x i8> %2, <16 x i8>* %ptr1, align 16
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store <16 x i8> %3, <16 x i8>* %ptr2, align 16
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store <16 x i8> %4, <16 x i8>* %ptr3, align 16
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store <16 x i8> %5, <16 x i8>* %ptr4, align 16
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ret void
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}
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; disassemble_pair
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declare { <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.pair(<256 x i1>)
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define void @disass_pair(<256 x i1>* %ptr1, <16 x i8>* %ptr2, <16 x i8>* %ptr3) {
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; CHECK-LABEL: disass_pair:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lxv vs1, 0(r3)
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; CHECK-NEXT: lxv vs0, 16(r3)
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; CHECK-NEXT: stxv vs1, 0(r4)
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; CHECK-NEXT: stxv vs0, 0(r5)
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; CHECK-NEXT: blr
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;
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; CHECK-BE-LABEL: disass_pair:
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; CHECK-BE: # %bb.0: # %entry
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; CHECK-BE-NEXT: lxv vs1, 16(r3)
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; CHECK-BE-NEXT: lxv vs0, 0(r3)
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; CHECK-BE-NEXT: stxv vs0, 0(r4)
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; CHECK-BE-NEXT: stxv vs1, 0(r5)
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; CHECK-BE-NEXT: blr
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entry:
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%0 = load <256 x i1>, <256 x i1>* %ptr1, align 32
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%1 = tail call { <16 x i8>, <16 x i8> } @llvm.ppc.mma.disassemble.pair(<256 x i1> %0)
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%2 = extractvalue { <16 x i8>, <16 x i8> } %1, 0
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%3 = extractvalue { <16 x i8>, <16 x i8> } %1, 1
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store <16 x i8> %2, <16 x i8>* %ptr2, align 16
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store <16 x i8> %3, <16 x i8>* %ptr3, align 16
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ret void
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}
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