forked from OSchip/llvm-project
58 lines
2.3 KiB
LLVM
58 lines
2.3 KiB
LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=CHECK,X64
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+adx | FileCheck %s --check-prefixes=CHECK,ADX
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; PR34292
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@_ZL1c = external global i8
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define void @sum_unroll(i64* nocapture readonly, i64* nocapture) {
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; CHECK-LABEL: sum_unroll:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movb {{.*}}(%rip), %al
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; CHECK-NEXT: movq (%rdi), %rcx
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; CHECK-NEXT: addb $-1, %al
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; CHECK-NEXT: adcq %rcx, (%rsi)
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; CHECK-NEXT: movq 8(%rdi), %rax
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; CHECK-NEXT: adcq %rax, 8(%rsi)
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; CHECK-NEXT: movq 16(%rdi), %rax
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; CHECK-NEXT: adcq %rax, 16(%rsi)
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; CHECK-NEXT: movq 24(%rdi), %rax
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; CHECK-NEXT: adcq %rax, 24(%rsi)
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; CHECK-NEXT: setb {{.*}}(%rip)
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; CHECK-NEXT: retq
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%3 = load i8, i8* @_ZL1c, align 1
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%4 = load i64, i64* %0, align 8
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%5 = load i64, i64* %1, align 8
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%6 = tail call { i8, i64 } @llvm.x86.addcarry.64(i8 %3, i64 %4, i64 %5)
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%7 = extractvalue { i8, i64 } %6, 1
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store i64 %7, i64* %1, align 8
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%8 = extractvalue { i8, i64 } %6, 0
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%9 = getelementptr inbounds i64, i64* %0, i64 1
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%10 = load i64, i64* %9, align 8
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%11 = getelementptr inbounds i64, i64* %1, i64 1
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%12 = load i64, i64* %11, align 8
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%13 = tail call { i8, i64 } @llvm.x86.addcarry.64(i8 %8, i64 %10, i64 %12)
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%14 = extractvalue { i8, i64 } %13, 1
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store i64 %14, i64* %11, align 8
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%15 = extractvalue { i8, i64 } %13, 0
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%16 = getelementptr inbounds i64, i64* %0, i64 2
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%17 = load i64, i64* %16, align 8
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%18 = getelementptr inbounds i64, i64* %1, i64 2
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%19 = load i64, i64* %18, align 8
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%20 = tail call { i8, i64 } @llvm.x86.addcarry.64(i8 %15, i64 %17, i64 %19)
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%21 = extractvalue { i8, i64 } %20, 1
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store i64 %21, i64* %18, align 8
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%22 = extractvalue { i8, i64 } %20, 0
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%23 = getelementptr inbounds i64, i64* %0, i64 3
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%24 = load i64, i64* %23, align 8
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%25 = getelementptr inbounds i64, i64* %1, i64 3
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%26 = load i64, i64* %25, align 8
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%27 = tail call { i8, i64 } @llvm.x86.addcarry.64(i8 %22, i64 %24, i64 %26)
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%28 = extractvalue { i8, i64 } %27, 1
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store i64 %28, i64* %25, align 8
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%29 = extractvalue { i8, i64 } %27, 0
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store i8 %29, i8* @_ZL1c, align 1
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ret void
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}
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declare { i8, i64 } @llvm.x86.addcarry.64(i8, i64, i64)
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