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llvm-project/llvm/test/CodeGen/X86/2011-12-28-vselecti8.ll

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Regenerate test in prep for SimplifyDemandedBits improvements. llvm-svn: 349350
2018-12-17 20:48:34 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
PR11662. Promotion of the mask operand needs to be done using PromoteTargetBoolean, and not padded with garbage. llvm-svn: 147309
2011-12-28 21:08:20 +08:00
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 | FileCheck %s
; ModuleID = '<stdin>'
Regenerate test in prep for SimplifyDemandedBits improvements. llvm-svn: 349350
2018-12-17 20:48:34 +08:00
PR11662. Promotion of the mask operand needs to be done using PromoteTargetBoolean, and not padded with garbage. llvm-svn: 147309
2011-12-28 21:08:20 +08:00
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-apple-darwin11.2.0"
Regenerate test in prep for SimplifyDemandedBits improvements. llvm-svn: 349350
2018-12-17 20:48:34 +08:00
; During legalization, the vselect mask is 'type legalized' into a
Teach DAGCombiner how to fold a SIGN_EXTEND_INREG of a BUILD_VECTOR of ConstantSDNodes (or UNDEFs) into a simple BUILD_VECTOR. For example, given the following sequence of dag nodes: i32 C = Constant<1> v4i32 V = BUILD_VECTOR C, C, C, C v4i32 Result = SIGN_EXTEND_INREG V, ValueType:v4i1 The SIGN_EXTEND_INREG node can be folded into a build_vector since the vector in input is a BUILD_VECTOR of constants. The optimized sequence is: i32 C = Constant<-1> v4i32 Result = BUILD_VECTOR C, C, C, C llvm-svn: 198084
2013-12-28 04:20:28 +08:00
; wider BUILD_VECTOR. This causes the introduction of a new
; sign_extend_inreg in the DAG.
;
; A sign_extend_inreg of a vector of ConstantSDNode or undef can be
; always folded into a simple build_vector.
;
; Make sure that the sign_extend_inreg is simplified and that we
; don't generate psll, psraw and pblendvb from the vselect.
PR11662. Promotion of the mask operand needs to be done using PromoteTargetBoolean, and not padded with garbage. llvm-svn: 147309
2011-12-28 21:08:20 +08:00
define void @foo8(float* nocapture %RET) nounwind {
Regenerate test in prep for SimplifyDemandedBits improvements. llvm-svn: 349350
2018-12-17 20:48:34 +08:00
; CHECK-LABEL: foo8:
; CHECK: ## %bb.0: ## %allocas
Recommit r354647 and r354648 "[LegalizeTypes] When promoting the result of EXTRACT_SUBVECTOR, also check if the input needs to be promoted. Use that to determine the element type to extract" r354648 was a follow up to fix a regression "[X86] Add a DAG combine for (aext_vector_inreg (aext_vector_inreg X)) -> (aext_vector_inreg X) to fix a regression from my previous commit." These were reverted in r354713 as their context depended on other patches that were reverted for a bug. llvm-svn: 354734
2019-02-24 03:51:32 +08:00
; CHECK-NEXT: movaps {{.*#+}} xmm0 = [1.0E+2,2.0E+0,1.0E+2,4.0E+0]
; CHECK-NEXT: movaps {{.*#+}} xmm1 = [1.0E+2,6.0E+0,1.0E+2,8.0E+0]
Regenerate test in prep for SimplifyDemandedBits improvements. llvm-svn: 349350
2018-12-17 20:48:34 +08:00
; CHECK-NEXT: movups %xmm1, 16(%rdi)
; CHECK-NEXT: movups %xmm0, (%rdi)
; CHECK-NEXT: retq
PR11662. Promotion of the mask operand needs to be done using PromoteTargetBoolean, and not padded with garbage. llvm-svn: 147309
2011-12-28 21:08:20 +08:00
allocas:
%resultvec.i = select <8 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, <8 x i8> <i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100, i8 100>
%uint2float = uitofp <8 x i8> %resultvec.i to <8 x float>
%ptr = bitcast float * %RET to <8 x float> *
store <8 x float> %uint2float, <8 x float>* %ptr, align 4
ret void
}