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llvm-project/llvm/test/MC/X86/x86_errors.s

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MC/X86/AsmParser: Give an explicit error message when we reject an instruction because it could have an ambiguous suffix. llvm-svn: 110890
2010-08-12 08:55:42 +08:00
// RUN: not llvm-mc -triple x86_64-unknown-unknown %s 2> %t.err
Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil. This can happen in cases where TableGen generated asm matcher cannot check whether a register operand is in the right register class. e.g. mem operands. rdar://8204588 llvm-svn: 136292
2011-07-28 07:22:03 +08:00
// RUN: FileCheck --check-prefix=64 < %t.err %s
MC/X86/AsmParser: Give an explicit error message when we reject an instruction because it could have an ambiguous suffix. llvm-svn: 110890
2010-08-12 08:55:42 +08:00
Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil. This can happen in cases where TableGen generated asm matcher cannot check whether a register operand is in the right register class. e.g. mem operands. rdar://8204588 llvm-svn: 136292
2011-07-28 07:22:03 +08:00
// RUN: not llvm-mc -triple i386-unknown-unknown %s 2> %t.err
// RUN: FileCheck --check-prefix=32 < %t.err %s
// rdar://8204588
// 64: error: ambiguous instructions require an explicit suffix (could be 'cmpb', 'cmpw', 'cmpl', or 'cmpq')
MC/X86/AsmParser: Give an explicit error message when we reject an instruction because it could have an ambiguous suffix. llvm-svn: 110890
2010-08-12 08:55:42 +08:00
cmp $0, 0(%eax)
Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil. This can happen in cases where TableGen generated asm matcher cannot check whether a register operand is in the right register class. e.g. mem operands. rdar://8204588 llvm-svn: 136292
2011-07-28 07:22:03 +08:00
// 32: error: register %rax is only available in 64-bit mode
addl $0, 0(%rax)
Finish supporting cpp #file/line comments in assembler for error messages. So for cpp pre-processed assembly we give correct filename and line numbers when reporting errors in assembly files when using clang and -integrated-as on .s files. rdar://8998895 llvm-svn: 141814
2011-10-13 05:38:39 +08:00
// 32: test.s:8:2: error: invalid instruction mnemonic 'movi'
# 8 "test.s"
movi $8,%eax
Enhance llvm::SourceMgr to support diagnostic ranges, the same way clang does. Enhance the X86 asmparser to produce ranges in the one case that was annoying me, for example: test.s:10:15: error: invalid operand for instruction movl 0(%rax), 0(%edx) ^~~~~~~ It should be straight-forward to enhance filecheck, tblgen, and/or the .ll parser to use ranges where appropriate if someone is interested. llvm-svn: 142106
2011-10-16 12:47:35 +08:00
movl 0(%rax), 0(%edx) // error: invalid operand for instruction
X86: Better diagnostics for 32-bit vs. 64-bit mode mismatches. When an instruction as written requires 32-bit mode and we're assembling in 64-bit mode, or vice-versa, issue a more specific diagnostic about what's wrong. rdar://12700702 llvm-svn: 167937
2012-11-15 02:04:47 +08:00
// 32: error: instruction requires: 64-bit mode
Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix and not depend on In32BitMode. Use the sysexitq mnemonic for the version with the REX.W prefix and only allow it only In64BitMode. rdar://9738584 llvm-svn: 143112
2011-10-28 01:40:41 +08:00
sysexitq
Add the missing call to Error when a bad X86 scale expression is parsed. llvm-svn: 152443
2012-03-10 06:24:10 +08:00
// rdar://10710167
// 64: error: expected scale expression
lea (%rsp, %rbp, $4), %rax
Added a missing error check for X86 assembly with mismatched base and index registers not both being 64-bit or both being 32-bit registers. llvm-svn: 152580
2012-03-13 05:32:09 +08:00
// rdar://10423777
[x86] Make AsmParser validate registers for memory operands a bit better We can't do a perfect job here. We *have* to allow (%dx) even in 64-bit mode, for example, because it might be used for an unofficial form of the in/out instructions. We actually want to do a better job of validation *later*. Perhaps *instead* of doing it where we are at the moment. But for now, doing what validation we *can* do in the place that the code already has its validation, is an improvement. llvm-svn: 198760
2014-01-08 20:58:28 +08:00
// 64: error: base register is 64-bit, but index register is not
Added a missing error check for X86 assembly with mismatched base and index registers not both being 64-bit or both being 32-bit registers. llvm-svn: 152580
2012-03-13 05:32:09 +08:00
movq (%rsi,%ecx),%xmm0
[ms-inline asm] Fix a crasher when we fail on a direct match. The issue was that the MatchingInlineAsm and VariantID args to the MatchInstructionImpl function weren't being set properly. Specifically, when parsing intel syntax, the parser thought it was parsing inline assembly in the at&t dialect; that will never be the case. The crash was caused when the emitter tried to emit the instruction, but the operands weren't set. When parsing inline assembly we only set the opcode, not the operands, which is used to lookup the instruction descriptor. rdar://13854391 and PR15945 Also, this commit reverts r176036. Now that we're correctly parsing the intel syntax the pushad/popad don't match properly. I've reimplemented that fix using a MnemonicAlias. llvm-svn: 181620
2013-05-11 02:24:17 +08:00
[x86] Make AsmParser validate registers for memory operands a bit better We can't do a perfect job here. We *have* to allow (%dx) even in 64-bit mode, for example, because it might be used for an unofficial form of the in/out instructions. We actually want to do a better job of validation *later*. Perhaps *instead* of doing it where we are at the moment. But for now, doing what validation we *can* do in the place that the code already has its validation, is an improvement. llvm-svn: 198760
2014-01-08 20:58:28 +08:00
// 64: error: invalid 16-bit base register
movl %eax,(%bp,%si)
// 32: error: scale factor in 16-bit address must be 1
movl %eax,(%bp,%si,2)
// 32: error: invalid 16-bit base register
movl %eax,(%cx)
// 32: error: invalid 16-bit base/index register combination
movl %eax,(%bp,%bx)
// 32: error: 16-bit memory operand may not include only index register
movl %eax,(,%bx)
[ms-inline asm] Fix a crasher when we fail on a direct match. The issue was that the MatchingInlineAsm and VariantID args to the MatchInstructionImpl function weren't being set properly. Specifically, when parsing intel syntax, the parser thought it was parsing inline assembly in the at&t dialect; that will never be the case. The crash was caused when the emitter tried to emit the instruction, but the operands weren't set. When parsing inline assembly we only set the opcode, not the operands, which is used to lookup the instruction descriptor. rdar://13854391 and PR15945 Also, this commit reverts r176036. Now that we're correctly parsing the intel syntax the pushad/popad don't match properly. I've reimplemented that fix using a MnemonicAlias. llvm-svn: 181620
2013-05-11 02:24:17 +08:00
// 32: error: invalid operand for instruction
outb al, 4
X86 MC: Reject invalid segment registers before a memory operand colon Previously we would execute unreachable during object emission. llvm-svn: 214456
2014-08-01 07:03:22 +08:00
// 32: error: invalid segment register
// 64: error: invalid segment register
movl %eax:0x00, %ebx
[x86] Add assembly parser bounds checking to the immediate value for cmpss/cmpsd/cmpps/cmppd. llvm-svn: 226642
2015-01-21 14:07:53 +08:00
// 32: error: invalid operand for instruction
// 64: error: invalid operand for instruction
cmpps $-129, %xmm0, %xmm0
// 32: error: invalid operand for instruction
// 64: error: invalid operand for instruction
cmppd $256, %xmm0, %xmm0
[X86] Add proper 64-bit mode checks to jrcxz and jcxz. llvm-svn: 241381
2015-07-04 08:01:07 +08:00
// 32: error: instruction requires: 64-bit mode
jrcxz 1
// 64: error: instruction requires: Not 64-bit mode
jcxz 1
[X86] Don't allow DR8-DR15 to be assembled in 32-bit mode. Add missing test for CR8-CR15. llvm-svn: 279921
2016-08-28 01:13:34 +08:00
// 32: error: register %cr8 is only available in 64-bit mode
movl %edx, %cr8
// 32: error: register %dr8 is only available in 64-bit mode
movl %edx, %dr8
[X86] Don't randomly encode %rip where illegal Differential Revision: https://reviews.llvm.org/D25112 llvm-svn: 283326
2016-10-05 23:23:35 +08:00
// 32: error: register %rip is only available in 64-bit mode
// 64: error: %rip can only be used as a base register
mov %rip, %rax
// 32: error: register %rax is only available in 64-bit mode
// 64: error: %rip is not allowed as an index register
mov (%rax,%rip), %rbx
[X86] Add a Requires<[In64BitMode]> to FARJMP64 Otherwise we can try to assemble it in 32-bit mode and throw an assert in the encoder. llvm-svn: 331161
2018-04-30 14:21:24 +08:00
// 32: error: instruction requires: 64-bit mode
ljmpq *(%eax)
[X86] Don't allow ESP/RSP to be used as an index register in assembly. Fixes PR37892 llvm-svn: 335370
2018-06-23 01:15:58 +08:00
// 32: error: register %rax is only available in 64-bit mode
// 64: error: invalid base+index expression
leaq (%rax,%rsp), %rax
// 32: error: invalid base+index expression
// 64: error: invalid base+index expression
leaq (%eax,%esp), %eax