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llvm-project/llvm/utils/TableGen/TableGen.cpp

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Move TableGen's parser and entry point into a library This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
2011-10-02 00:41:13 +08:00
//===- TableGen.cpp - Top-Level TableGen implementation for LLVM ----------===//
Remove trailing whitespace llvm-svn: 21428
2005-04-22 08:00:37 +08:00
//
Update the file headers across all of the LLVM projects in the monorepo to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
2019-01-19 16:50:56 +08:00
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Remove trailing whitespace llvm-svn: 21428
2005-04-22 08:00:37 +08:00
//
Added LLVM copyright header. llvm-svn: 9305
2003-10-21 04:20:30 +08:00
//===----------------------------------------------------------------------===//
Move support/tools/* back into utils llvm-svn: 8875
2003-10-06 03:27:59 +08:00
//
Move TableGen's parser and entry point into a library This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
2011-10-02 00:41:13 +08:00
// This file contains the main function for LLVM's TableGen.
Move support/tools/* back into utils llvm-svn: 8875
2003-10-06 03:27:59 +08:00
//
//===----------------------------------------------------------------------===//
Write llvm-tblgen backends as functions instead of sub-classes. The TableGenBackend base class doesn't do much, and will be removed completely soon. Patch by Sean Silva! llvm-svn: 158311
2012-06-11 23:37:55 +08:00
#include "TableGenBackends.h" // Declares all backends.
Add a new little "FileCheck" utility for regression testing. llvm-svn: 75022
2009-07-09 02:44:05 +08:00
#include "llvm/Support/CommandLine.h"
[TableGen] Call llvm_shutdown on exit so that all the ManagedStatic objects in the support library will be deleted. llvm-svn: 256732
2016-01-04 12:51:51 +08:00
#include "llvm/Support/ManagedStatic.h"
Add a new little "FileCheck" utility for regression testing. llvm-svn: 75022
2009-07-09 02:44:05 +08:00
#include "llvm/Support/PrettyStackTrace.h"
Merge System into Support. llvm-svn: 120298
2010-11-30 02:16:10 +08:00
#include "llvm/Support/Signals.h"
Move TableGen's parser and entry point into a library This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
2011-10-02 00:41:13 +08:00
#include "llvm/TableGen/Main.h"
#include "llvm/TableGen/Record.h"
Move SetTheory from utils/TableGen into lib/TableGen so Clang can use it. llvm-svn: 211100
2014-06-17 21:10:38 +08:00
#include "llvm/TableGen/SetTheory.h"
Move TableGen's parser and entry point into a library This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
2011-10-02 00:41:13 +08:00
Finegrainify namespacification llvm-svn: 15381
2004-08-01 11:55:39 +08:00
using namespace llvm;
Put all LLVM code into the llvm namespace, as per bug 109. llvm-svn: 9903
2003-11-12 06:41:34 +08:00
Move support/tools/* back into utils llvm-svn: 8875
2003-10-06 03:27:59 +08:00
enum ActionType {
PrintRecords,
[TableGen] Add a general-purpose JSON backend. The aim of this backend is to output everything TableGen knows about the record set, similarly to the default -print-records backend. But where -print-records produces output in TableGen's input syntax (convenient for humans to read), this backend produces it as structured JSON data, which is convenient for loading into standard scripting languages such as Python, in order to extract information from the data set in an automated way. The output data contains a JSON representation of the variable definitions in output 'def' records, and a few pieces of metadata such as which of those definitions are tagged with the 'field' prefix and which defs are derived from which classes. It doesn't dump out absolutely every piece of knowledge it _could_ produce, such as type information and complicated arithmetic operator nodes in abstract superclasses; the main aim is to allow consumers of this JSON dump to essentially act as new backends, and backends don't generally need to depend on that kind of data. The new backend is implemented as an EmitJSON() function similar to all of llvm-tblgen's other EmitFoo functions, except that it lives in lib/TableGen instead of utils/TableGen on the basis that I'm expecting to add it to clang-tblgen too in a future patch. To test it, I've written a Python script that loads the JSON output and tests properties of it based on comments in the .td source - more or less like FileCheck, except that the CHECK: lines have Python expressions after them instead of textual pattern matches. Reviewers: nhaehnle Reviewed By: nhaehnle Subscribers: arichardson, labath, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D46054 llvm-svn: 336771
2018-07-11 16:40:19 +08:00
DumpJSON,
Move support/tools/* back into utils llvm-svn: 8875
2003-10-06 03:27:59 +08:00
GenEmitter,
Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc into XXXGenRegisterInfo.inc. llvm-svn: 133922
2011-06-28 02:32:37 +08:00
GenRegisterInfo,
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc llvm-svn: 134024
2011-06-29 04:07:07 +08:00
GenInstrInfo,
[Docs] Add tablegen backend for target opcode documentation This is a tablegen backend to generate documentation for the opcodes that exist for each target. For each opcode, it lists the assembly string, the names and types of all operands, and the flags and predicates that apply to the opcode. Differential revision: https://reviews.llvm.org/D31025 llvm-svn: 318155
2017-11-14 23:35:15 +08:00
GenInstrDocs,
Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc llvm-svn: 134024
2011-06-29 04:07:07 +08:00
GenAsmWriter,
GenAsmMatcher,
Sketch TableGen disassembler emitter, based on patch by Sean Callanan. llvm-svn: 89833
2009-11-25 10:13:23 +08:00
GenDisassembler,
TableGen'erated MC lowering for simple pseudo-instructions. This allows the (many) pseudo-instructions we have that map onto a single real instruction to have their expansion during MC lowering handled automatically instead of the current cumbersome manual expansion required. These sorts of pseudos are common when an instruction is used in situations that require different MachineInstr flags (isTerminator, isBranch, et. al.) than the generic instruction description has. For example, using a move to the PC to implement a branch. llvm-svn: 134704
2011-07-09 01:36:35 +08:00
GenPseudoLowering,
[RISCV] Tablegen-driven Instruction Compression. Summary: This patch implements a tablegen-driven Instruction Compression mechanism for generating RISCV compressed instructions (C Extension) from the expanded instruction form. This tablegen backend processes CompressPat declarations in a td file and generates all the compile-time and runtime checks required to validate the declarations, validate the input operands and generate correct instructions. The checks include validating register operands, immediate operands, fixed register operands and fixed immediate operands. Example: class CompressPat<dag input, dag output> { dag Input = input; dag Output = output; list<Predicate> Predicates = []; } let Predicates = [HasStdExtC] in { def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2), (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>; } The result is an auto-generated header file 'RISCVGenCompressEmitter.inc' which exports two functions for compressing/uncompressing MCInst instructions, plus some helper functions: bool compressInst(MCInst& OutInst, const MCInst &MI, const MCSubtargetInfo &STI, MCContext &Context); bool uncompressInst(MCInst& OutInst, const MCInst &MI, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI); The clients that include this auto-generated header file and invoke these functions can compress an instruction before emitting it, in the target-specific ASM or ELF streamer, or can uncompress an instruction before printing it, when the expanded instruction format aliases is favored. The following clients were added to implement compression\uncompression for RISCV: 1) RISCVAsmParser::MatchAndEmitInstruction: Inserted a call to compressInst() to compresses instructions parsed by llvm-mc coming from an ASM input. 2) RISCVAsmPrinter::EmitInstruction: Inserted a call to compressInst() to compress instructions that were lowered from Machine Instructions (MachineInstr). 3) RVInstPrinter::printInst: Inserted a call to uncompressInst() to print the expanded version of the instruction instead of the compressed one (e.g, add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases is not passed. This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by asb, efriedma, apazos and mgrang. Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal Reviewed By: sabuasal Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng Differential Revision: https://reviews.llvm.org/D45385 llvm-svn: 329455
2018-04-07 05:07:05 +08:00
GenCompressInst,
reapply llvm-svn: 34697
2007-02-28 06:08:27 +08:00
GenCallingConv,
Add an option and stuff implementation of a dag isel emitter llvm-svn: 23236
2005-09-03 09:14:03 +08:00
GenDAGISel,
Add a deterministic finite automaton based packetizer for VLIW architectures llvm-svn: 145629
2011-12-02 05:10:21 +08:00
GenDFAPacketizer,
Initial checkin of the new "fast" instruction selection support. See the comments in FastISelEmitter.cpp for details on what this is. This is currently experimental and unusable. llvm-svn: 54751
2008-08-14 04:19:35 +08:00
GenFastISel,
Plugin new subtarget backend into the build. llvm-svn: 23870
2005-10-22 03:05:19 +08:00
GenSubtarget,
[IR] Split Intrinsics.inc into enums and implementations Implements PR34259 Intrinsics.h is a very popular header. Most LLVM TUs care about things like dbg_value, but they don't care how they are implemented. After I split these out, IntrinsicImpl.inc is 1.7 MB, so this saves each LLVM TU from scanning 1.7 MB of source that gets pre-processed away. It also means we can modify intrinsic properties without triggering a full rebuild, but that's probably less of a win. I think the next best thing to do would be to split out the target intrinsics into their own header. Very, very few TUs care about target-specific intrinsics. It's very hard to split up the target independent intrinsics like llvm.expect, assume, and dbg.value, though. llvm-svn: 335407
2018-06-23 10:02:38 +08:00
GenIntrinsicEnums,
GenIntrinsicImpl,
GenTgtIntrinsicEnums,
GenTgtIntrinsicImpl,
Teach TableGen to evaluate DAG expressions as set operations. A TableGen backend can define how certain classes can be expanded into ordered sets of defs, typically by evaluating a specific field in the record. The SetTheory class can then evaluate DAG expressions that refer to these named sets. A number of standard set and list operations are predefined, and the backend can add more specialized operators if needed. The -print-sets backend is used by SetTheory.td to provide examples. This is intended to simplify how register classes are defined: def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>; llvm-svn: 132621
2011-06-04 12:11:37 +08:00
PrintEnums,
Copy clang/Driver/<Option parsing stuff> to llvm. llvm-svn: 169344
2012-12-05 08:29:32 +08:00
PrintSets,
Add TableGen ctags(1) emitter and helper script. To use this in conjunction with exuberant ctags to generate a single combined tags file, run tblgen first and then $ ctags --append [...] Since some identifiers have corresponding definitions in C++ code, it can be useful (if using vim) to also use cscope, and :set cscopetagorder=1 so that :tag X will preferentially select the tablegen symbol, while :cscope find g X will always find the C++ symbol. Patch by Kevin Schoedel! (a couple small formatting changes courtesy of clang-format) llvm-svn: 177682
2013-03-22 07:40:38 +08:00
GenOptParserDefs,
Move the enum attributes defined in Attributes.h to a table-gen file. This is a step towards consolidating some of the information regarding attributes in a single place. This patch moves the enum attributes in Attributes.h to the table-gen file. Additionally, it adds definitions of target independent string attributes that will be used in follow-up commits by the inliner to check attribute compatibility. rdar://problem/19836465 llvm-svn: 252796
2015-11-12 04:35:42 +08:00
GenCTags,
AArch64: TableGenerate system instruction operands. The way the named arguments for various system instructions are handled at the moment has a few problems: - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp - That weird Mapping class that I have no idea what I was on when I thought it was a good idea. - Searches are performed linearly through the entire list. - We print absolutely all registers in upper-case, even though some are canonically mixed case (SPSel for example). - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated to comments in our implementation, with a slightly opaque hex value indicating the canonical encoding LLVM will use. This adds a new TableGen backend to produce efficiently searchable tables, and switches AArch64 over to using that infrastructure. llvm-svn: 274576
2016-07-06 05:23:04 +08:00
GenAttributes,
GenSearchableTables,
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-22 07:26:20 +08:00
GenGlobalISel,
[gicombiner] Add the boring boilerplate for the declarative combiner Summary: This is the first of a series of patches extracted from a much bigger WIP patch. It merely establishes the tblgen pass and the way empty combiner helpers are declared and integrated into a combiner info. The tablegen pass takes a -combiners option to select the combiner helper that will be generated. This can be given multiple values to generate multiple combiner helpers at once. Doing so helps to minimize parsing overhead. The reason for creating a GlobalISel subdirectory in utils/TableGen is that there will be quite a lot of non-pass files (~15) by the time the patch series is done. Reviewers: volkan Subscribers: mgorny, hiraditya, simoncook, Petar.Avramovic, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68286 llvm-svn: 373527
2019-10-03 05:13:07 +08:00
GenGICombiner,
[X86][AVX512] Adding new LLVM TableGen backend which generates the EVEX2VEX compressing tables. X86EvexToVex machine instruction pass compresses EVEX encoded instructions by replacing them with their identical VEX encoded instructions when possible. It uses manually supported 2 large tables that map the EVEX instructions to their VEX ideticals. This TableGen backend replaces the tables by automatically generating them. Differential Revision: https://reviews.llvm.org/D30451 llvm-svn: 297127
2017-03-07 16:11:19 +08:00
GenX86EVEX2VEXTables,
[X86][TableGen] Recommitting the X86 memory folding tables TableGen backend while disabling it by default. After the original commit ([[ https://reviews.llvm.org/rL304088 | rL304088 ]]) was reverted, a discussion in llvm-dev was opened on 'how to accomplish this task'. In the discussion we concluded that the best way to achieve our goal (which is to automate the folding tables and remove the manually maintained tables) is: # Commit the tablegen backend disabled by default. # Proceed with an incremental updating of the manual tables - while checking the validity of each added entry. # Repeat previous step until we reach a state where the generated and the manual tables are identical. Then we can safely remove the manual tables and include the generated tables instead. # Schedule periodical (1 week/2 weeks/1 month) runs of the pass: - if changes appear (new entries): - make sure the entries are legal - If they are not, mark them as illegal to folding - Commit the changes (if there are any). CMake flag added for this purpose is "X86_GEN_FOLD_TABLES". Building with this flags will run the pass and emit the X86GenFoldTables.inc file under build/lib/Target/X86/ directory which is a good reference for any developer who wants to take part in the effort of completing the current folding tables. Differential Revision: https://reviews.llvm.org/D38028 llvm-svn: 315173
2017-10-08 17:20:32 +08:00
GenX86FoldTables,
Re-commit: [globalisel] Tablegen-erate current Register Bank Information Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Changes since first commit attempt: * Added missing guards * Added more missing guards * Found and fixed a use-after-free bug involving Twine locals Reviewers: t.p.northover, ab, rovka, qcolombet Reviewed By: qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 llvm-svn: 292478
2017-01-19 19:15:55 +08:00
GenRegisterBank,
[MCSched] Bind PFM Counters to the CPUs instead of the SchedModel. Summary: The pfm counters are now in the ExegesisTarget rather than the MCSchedModel (PR39165). This also compresses the pfm counter tables (PR37068). Reviewers: RKSimon, gchatelet Subscribers: mgrang, llvm-commits Differential Revision: https://reviews.llvm.org/D52932 llvm-svn: 345243
2018-10-25 15:44:01 +08:00
GenExegesis,
[TableGen] Introduce a generic automaton (DFA) backend Summary: This patch introduces -gen-automata, a backend for generating deterministic finite-state automata. DFAs are already generated by the -gen-dfa-packetizer backend. This backend is more generic and will hopefully be used to implement the DFA generation (and determinization) for the packetizer in the future. This backend allows not only generation of a DFA from an NFA (nondeterministic finite-state automaton), it also emits sidetables that allow a path through the DFA under a sequence of inputs to be analyzed, and the equivalent set of all possible NFA transitions extracted. This allows a user to not just answer "can my problem be solved?" but also "what is the solution?". Clearly this analysis is more expensive than just playing a DFA forwards so is opt-in. The DFAPacketizer has this behaviour already but this is a more compact and generic representation. Examples are bundled in unittests/TableGen/Automata.td. Some are trivial, but the BinPacking example is a stripped-down version of the original target problem I set out to solve, where we pack values (actually immediates) into bins (an immediate pool in a VLIW bundle) subject to a set of esoteric constraints. Reviewers: t.p.northover Subscribers: mgorny, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67968 llvm-svn: 373718
2019-10-04 17:03:36 +08:00
GenAutomata,
Move support/tools/* back into utils llvm-svn: 8875
2003-10-06 03:27:59 +08:00
};
[tblgen] Add a timer covering the time spent reading the Instruction defs This patch adds a -time-regions option to tablegen that can enable timers (currently only one) that assess the performance of tablegen itself. This can be useful for identifying scaling problems with tablegen backends. This particular timer has allowed me to ignore time that is not attributed the GISel combiner pass. It's useful by itself but it is particularly useful in combination with https://reviews.llvm.org/D52954 which causes this period of time to be annotated within Xcode Instruments which in turn allows profile samples and recorded allocations attributed to reading instructions to be filtered out. llvm-svn: 353763
2019-02-12 07:02:02 +08:00
namespace llvm {
/// Storage for TimeRegionsOpt as a global so that backends aren't required to
/// include CommandLine.h
bool TimeRegions = false;
} // end namespace llvm
Move support/tools/* back into utils llvm-svn: 8875
2003-10-06 03:27:59 +08:00
namespace {
Fix inconsistent indentation in TableGen.cpp The anonymous namespace starts out (incorrectly) indented but isn't indented from the TimeRegionsOpt declaration onwards. llvm-svn: 373516
2019-10-03 03:56:04 +08:00
cl::opt<ActionType> Action(
cl::desc("Action to perform:"),
cl::values(
clEnumValN(PrintRecords, "print-records",
"Print all records to stdout (default)"),
clEnumValN(DumpJSON, "dump-json",
"Dump all records as machine-readable JSON"),
clEnumValN(GenEmitter, "gen-emitter", "Generate machine code emitter"),
clEnumValN(GenRegisterInfo, "gen-register-info",
"Generate registers and register classes info"),
clEnumValN(GenInstrInfo, "gen-instr-info",
"Generate instruction descriptions"),
clEnumValN(GenInstrDocs, "gen-instr-docs",
"Generate instruction documentation"),
clEnumValN(GenCallingConv, "gen-callingconv",
"Generate calling convention descriptions"),
clEnumValN(GenAsmWriter, "gen-asm-writer", "Generate assembly writer"),
clEnumValN(GenDisassembler, "gen-disassembler",
"Generate disassembler"),
clEnumValN(GenPseudoLowering, "gen-pseudo-lowering",
"Generate pseudo instruction lowering"),
clEnumValN(GenCompressInst, "gen-compress-inst-emitter",
"Generate RISCV compressed instructions."),
clEnumValN(GenAsmMatcher, "gen-asm-matcher",
"Generate assembly instruction matcher"),
clEnumValN(GenDAGISel, "gen-dag-isel",
"Generate a DAG instruction selector"),
clEnumValN(GenDFAPacketizer, "gen-dfa-packetizer",
"Generate DFA Packetizer for VLIW targets"),
clEnumValN(GenFastISel, "gen-fast-isel",
"Generate a \"fast\" instruction selector"),
clEnumValN(GenSubtarget, "gen-subtarget",
"Generate subtarget enumerations"),
clEnumValN(GenIntrinsicEnums, "gen-intrinsic-enums",
"Generate intrinsic enums"),
clEnumValN(GenIntrinsicImpl, "gen-intrinsic-impl",
"Generate intrinsic information"),
clEnumValN(GenTgtIntrinsicEnums, "gen-tgt-intrinsic-enums",
"Generate target intrinsic enums"),
clEnumValN(GenTgtIntrinsicImpl, "gen-tgt-intrinsic-impl",
"Generate target intrinsic information"),
clEnumValN(PrintEnums, "print-enums", "Print enum values for a class"),
clEnumValN(PrintSets, "print-sets",
"Print expanded sets for testing DAG exprs"),
clEnumValN(GenOptParserDefs, "gen-opt-parser-defs",
"Generate option definitions"),
clEnumValN(GenCTags, "gen-ctags", "Generate ctags-compatible index"),
clEnumValN(GenAttributes, "gen-attrs", "Generate attributes"),
clEnumValN(GenSearchableTables, "gen-searchable-tables",
"Generate generic binary-searchable table"),
clEnumValN(GenGlobalISel, "gen-global-isel",
"Generate GlobalISel selector"),
[gicombiner] Add the boring boilerplate for the declarative combiner Summary: This is the first of a series of patches extracted from a much bigger WIP patch. It merely establishes the tblgen pass and the way empty combiner helpers are declared and integrated into a combiner info. The tablegen pass takes a -combiners option to select the combiner helper that will be generated. This can be given multiple values to generate multiple combiner helpers at once. Doing so helps to minimize parsing overhead. The reason for creating a GlobalISel subdirectory in utils/TableGen is that there will be quite a lot of non-pass files (~15) by the time the patch series is done. Reviewers: volkan Subscribers: mgorny, hiraditya, simoncook, Petar.Avramovic, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68286 llvm-svn: 373527
2019-10-03 05:13:07 +08:00
clEnumValN(GenGICombiner, "gen-global-isel-combiner",
"Generate GlobalISel combiner"),
Fix inconsistent indentation in TableGen.cpp The anonymous namespace starts out (incorrectly) indented but isn't indented from the TimeRegionsOpt declaration onwards. llvm-svn: 373516
2019-10-03 03:56:04 +08:00
clEnumValN(GenX86EVEX2VEXTables, "gen-x86-EVEX2VEX-tables",
"Generate X86 EVEX to VEX compress tables"),
clEnumValN(GenX86FoldTables, "gen-x86-fold-tables",
"Generate X86 fold tables"),
clEnumValN(GenRegisterBank, "gen-register-bank",
"Generate registers bank descriptions"),
clEnumValN(GenExegesis, "gen-exegesis",
[TableGen] Introduce a generic automaton (DFA) backend Summary: This patch introduces -gen-automata, a backend for generating deterministic finite-state automata. DFAs are already generated by the -gen-dfa-packetizer backend. This backend is more generic and will hopefully be used to implement the DFA generation (and determinization) for the packetizer in the future. This backend allows not only generation of a DFA from an NFA (nondeterministic finite-state automaton), it also emits sidetables that allow a path through the DFA under a sequence of inputs to be analyzed, and the equivalent set of all possible NFA transitions extracted. This allows a user to not just answer "can my problem be solved?" but also "what is the solution?". Clearly this analysis is more expensive than just playing a DFA forwards so is opt-in. The DFAPacketizer has this behaviour already but this is a more compact and generic representation. Examples are bundled in unittests/TableGen/Automata.td. Some are trivial, but the BinPacking example is a stripped-down version of the original target problem I set out to solve, where we pack values (actually immediates) into bins (an immediate pool in a VLIW bundle) subject to a set of esoteric constraints. Reviewers: t.p.northover Subscribers: mgorny, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67968 llvm-svn: 373718
2019-10-04 17:03:36 +08:00
"Generate llvm-exegesis tables"),
clEnumValN(GenAutomata, "gen-automata",
"Generate generic automata")));
Move support/tools/* back into utils llvm-svn: 8875
2003-10-06 03:27:59 +08:00
Fix inconsistent indentation in TableGen.cpp The anonymous namespace starts out (incorrectly) indented but isn't indented from the TimeRegionsOpt declaration onwards. llvm-svn: 373516
2019-10-03 03:56:04 +08:00
cl::OptionCategory PrintEnumsCat("Options for -print-enums");
cl::opt<std::string> Class("class", cl::desc("Print Enum list for this class"),
cl::value_desc("class name"),
cl::cat(PrintEnumsCat));
Write llvm-tblgen backends as functions instead of sub-classes. The TableGenBackend base class doesn't do much, and will be removed completely soon. Patch by Sean Silva! llvm-svn: 158311
2012-06-11 23:37:55 +08:00
[tblgen] Add a timer covering the time spent reading the Instruction defs This patch adds a -time-regions option to tablegen that can enable timers (currently only one) that assess the performance of tablegen itself. This can be useful for identifying scaling problems with tablegen backends. This particular timer has allowed me to ignore time that is not attributed the GISel combiner pass. It's useful by itself but it is particularly useful in combination with https://reviews.llvm.org/D52954 which causes this period of time to be annotated within Xcode Instruments which in turn allows profile samples and recorded allocations attributed to reading instructions to be filtered out. llvm-svn: 353763
2019-02-12 07:02:02 +08:00
cl::opt<bool, true>
TimeRegionsOpt("time-regions",
cl::desc("Time regions of tablegens execution"),
cl::location(TimeRegions));
tblgen: Migrate llvm-tblgen to new TableGenMain API. llvm-svn: 165166
2012-10-04 05:29:19 +08:00
bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) {
switch (Action) {
case PrintRecords:
OS << Records; // No argument, dump all contents
break;
[TableGen] Add a general-purpose JSON backend. The aim of this backend is to output everything TableGen knows about the record set, similarly to the default -print-records backend. But where -print-records produces output in TableGen's input syntax (convenient for humans to read), this backend produces it as structured JSON data, which is convenient for loading into standard scripting languages such as Python, in order to extract information from the data set in an automated way. The output data contains a JSON representation of the variable definitions in output 'def' records, and a few pieces of metadata such as which of those definitions are tagged with the 'field' prefix and which defs are derived from which classes. It doesn't dump out absolutely every piece of knowledge it _could_ produce, such as type information and complicated arithmetic operator nodes in abstract superclasses; the main aim is to allow consumers of this JSON dump to essentially act as new backends, and backends don't generally need to depend on that kind of data. The new backend is implemented as an EmitJSON() function similar to all of llvm-tblgen's other EmitFoo functions, except that it lives in lib/TableGen instead of utils/TableGen on the basis that I'm expecting to add it to clang-tblgen too in a future patch. To test it, I've written a Python script that loads the JSON output and tests properties of it based on comments in the .td source - more or less like FileCheck, except that the CHECK: lines have Python expressions after them instead of textual pattern matches. Reviewers: nhaehnle Reviewed By: nhaehnle Subscribers: arichardson, labath, mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D46054 llvm-svn: 336771
2018-07-11 16:40:19 +08:00
case DumpJSON:
EmitJSON(Records, OS);
break;
tblgen: Migrate llvm-tblgen to new TableGenMain API. llvm-svn: 165166
2012-10-04 05:29:19 +08:00
case GenEmitter:
EmitCodeEmitter(Records, OS);
break;
case GenRegisterInfo:
EmitRegisterInfo(Records, OS);
break;
case GenInstrInfo:
EmitInstrInfo(Records, OS);
break;
[Docs] Add tablegen backend for target opcode documentation This is a tablegen backend to generate documentation for the opcodes that exist for each target. For each opcode, it lists the assembly string, the names and types of all operands, and the flags and predicates that apply to the opcode. Differential revision: https://reviews.llvm.org/D31025 llvm-svn: 318155
2017-11-14 23:35:15 +08:00
case GenInstrDocs:
EmitInstrDocs(Records, OS);
break;
tblgen: Migrate llvm-tblgen to new TableGenMain API. llvm-svn: 165166
2012-10-04 05:29:19 +08:00
case GenCallingConv:
EmitCallingConv(Records, OS);
break;
case GenAsmWriter:
EmitAsmWriter(Records, OS);
break;
case GenAsmMatcher:
EmitAsmMatcher(Records, OS);
break;
case GenDisassembler:
EmitDisassembler(Records, OS);
break;
case GenPseudoLowering:
EmitPseudoLowering(Records, OS);
break;
[RISCV] Tablegen-driven Instruction Compression. Summary: This patch implements a tablegen-driven Instruction Compression mechanism for generating RISCV compressed instructions (C Extension) from the expanded instruction form. This tablegen backend processes CompressPat declarations in a td file and generates all the compile-time and runtime checks required to validate the declarations, validate the input operands and generate correct instructions. The checks include validating register operands, immediate operands, fixed register operands and fixed immediate operands. Example: class CompressPat<dag input, dag output> { dag Input = input; dag Output = output; list<Predicate> Predicates = []; } let Predicates = [HasStdExtC] in { def : CompressPat<(ADD GPRNoX0:$rs1, GPRNoX0:$rs1, GPRNoX0:$rs2), (C_ADD GPRNoX0:$rs1, GPRNoX0:$rs2)>; } The result is an auto-generated header file 'RISCVGenCompressEmitter.inc' which exports two functions for compressing/uncompressing MCInst instructions, plus some helper functions: bool compressInst(MCInst& OutInst, const MCInst &MI, const MCSubtargetInfo &STI, MCContext &Context); bool uncompressInst(MCInst& OutInst, const MCInst &MI, const MCRegisterInfo &MRI, const MCSubtargetInfo &STI); The clients that include this auto-generated header file and invoke these functions can compress an instruction before emitting it, in the target-specific ASM or ELF streamer, or can uncompress an instruction before printing it, when the expanded instruction format aliases is favored. The following clients were added to implement compression\uncompression for RISCV: 1) RISCVAsmParser::MatchAndEmitInstruction: Inserted a call to compressInst() to compresses instructions parsed by llvm-mc coming from an ASM input. 2) RISCVAsmPrinter::EmitInstruction: Inserted a call to compressInst() to compress instructions that were lowered from Machine Instructions (MachineInstr). 3) RVInstPrinter::printInst: Inserted a call to uncompressInst() to print the expanded version of the instruction instead of the compressed one (e.g, add s0, s0, a5 instead of c.add s0, a5) when -riscv-no-aliases is not passed. This patch squashes D45119, D42780 and D41932. It was reviewed in smaller patches by asb, efriedma, apazos and mgrang. Reviewers: asb, efriedma, apazos, llvm-commits, sabuasal Reviewed By: sabuasal Subscribers: mgorny, eraman, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, niosHD, kito-cheng, shiva0217, zzheng Differential Revision: https://reviews.llvm.org/D45385 llvm-svn: 329455
2018-04-07 05:07:05 +08:00
case GenCompressInst:
EmitCompressInst(Records, OS);
break;
tblgen: Migrate llvm-tblgen to new TableGenMain API. llvm-svn: 165166
2012-10-04 05:29:19 +08:00
case GenDAGISel:
EmitDAGISel(Records, OS);
break;
case GenDFAPacketizer:
EmitDFAPacketizer(Records, OS);
break;
case GenFastISel:
EmitFastISel(Records, OS);
break;
case GenSubtarget:
EmitSubtarget(Records, OS);
break;
[IR] Split Intrinsics.inc into enums and implementations Implements PR34259 Intrinsics.h is a very popular header. Most LLVM TUs care about things like dbg_value, but they don't care how they are implemented. After I split these out, IntrinsicImpl.inc is 1.7 MB, so this saves each LLVM TU from scanning 1.7 MB of source that gets pre-processed away. It also means we can modify intrinsic properties without triggering a full rebuild, but that's probably less of a win. I think the next best thing to do would be to split out the target intrinsics into their own header. Very, very few TUs care about target-specific intrinsics. It's very hard to split up the target independent intrinsics like llvm.expect, assume, and dbg.value, though. llvm-svn: 335407
2018-06-23 10:02:38 +08:00
case GenIntrinsicEnums:
EmitIntrinsicEnums(Records, OS);
tblgen: Migrate llvm-tblgen to new TableGenMain API. llvm-svn: 165166
2012-10-04 05:29:19 +08:00
break;
[IR] Split Intrinsics.inc into enums and implementations Implements PR34259 Intrinsics.h is a very popular header. Most LLVM TUs care about things like dbg_value, but they don't care how they are implemented. After I split these out, IntrinsicImpl.inc is 1.7 MB, so this saves each LLVM TU from scanning 1.7 MB of source that gets pre-processed away. It also means we can modify intrinsic properties without triggering a full rebuild, but that's probably less of a win. I think the next best thing to do would be to split out the target intrinsics into their own header. Very, very few TUs care about target-specific intrinsics. It's very hard to split up the target independent intrinsics like llvm.expect, assume, and dbg.value, though. llvm-svn: 335407
2018-06-23 10:02:38 +08:00
case GenIntrinsicImpl:
EmitIntrinsicImpl(Records, OS);
break;
case GenTgtIntrinsicEnums:
EmitIntrinsicEnums(Records, OS, true);
break;
case GenTgtIntrinsicImpl:
EmitIntrinsicImpl(Records, OS, true);
tblgen: Migrate llvm-tblgen to new TableGenMain API. llvm-svn: 165166
2012-10-04 05:29:19 +08:00
break;
Copy clang/Driver/<Option parsing stuff> to llvm. llvm-svn: 169344
2012-12-05 08:29:32 +08:00
case GenOptParserDefs:
EmitOptParser(Records, OS);
break;
tblgen: Migrate llvm-tblgen to new TableGenMain API. llvm-svn: 165166
2012-10-04 05:29:19 +08:00
case PrintEnums:
{
Use range-based for loops. NFC llvm-svn: 224005
2014-12-11 15:04:54 +08:00
for (Record *Rec : Records.getAllDerivedDefinitions(Class))
OS << Rec->getName() << ", ";
tblgen: Migrate llvm-tblgen to new TableGenMain API. llvm-svn: 165166
2012-10-04 05:29:19 +08:00
OS << "\n";
break;
}
case PrintSets:
{
SetTheory Sets;
Sets.addFieldExpander("Set", "Elements");
Use range-based for loops. NFC llvm-svn: 224005
2014-12-11 15:04:54 +08:00
for (Record *Rec : Records.getAllDerivedDefinitions("Set")) {
OS << Rec->getName() << " = [";
const std::vector<Record*> *Elts = Sets.expand(Rec);
tblgen: Migrate llvm-tblgen to new TableGenMain API. llvm-svn: 165166
2012-10-04 05:29:19 +08:00
assert(Elts && "Couldn't expand Set instance");
Use range-based for loops. NFC llvm-svn: 224005
2014-12-11 15:04:54 +08:00
for (Record *Elt : *Elts)
OS << ' ' << Elt->getName();
tblgen: Migrate llvm-tblgen to new TableGenMain API. llvm-svn: 165166
2012-10-04 05:29:19 +08:00
OS << " ]\n";
Put all LLVM code into the llvm namespace, as per bug 109. llvm-svn: 9903
2003-11-12 06:41:34 +08:00
}
tblgen: Migrate llvm-tblgen to new TableGenMain API. llvm-svn: 165166
2012-10-04 05:29:19 +08:00
break;
}
Add TableGen ctags(1) emitter and helper script. To use this in conjunction with exuberant ctags to generate a single combined tags file, run tblgen first and then $ ctags --append [...] Since some identifiers have corresponding definitions in C++ code, it can be useful (if using vim) to also use cscope, and :set cscopetagorder=1 so that :tag X will preferentially select the tablegen symbol, while :cscope find g X will always find the C++ symbol. Patch by Kevin Schoedel! (a couple small formatting changes courtesy of clang-format) llvm-svn: 177682
2013-03-22 07:40:38 +08:00
case GenCTags:
EmitCTags(Records, OS);
break;
Move the enum attributes defined in Attributes.h to a table-gen file. This is a step towards consolidating some of the information regarding attributes in a single place. This patch moves the enum attributes in Attributes.h to the table-gen file. Additionally, it adds definitions of target independent string attributes that will be used in follow-up commits by the inliner to check attribute compatibility. rdar://problem/19836465 llvm-svn: 252796
2015-11-12 04:35:42 +08:00
case GenAttributes:
EmitAttributes(Records, OS);
break;
AArch64: TableGenerate system instruction operands. The way the named arguments for various system instructions are handled at the moment has a few problems: - Large-scale duplication between AArch64BaseInfo.h and AArch64BaseInfo.cpp - That weird Mapping class that I have no idea what I was on when I thought it was a good idea. - Searches are performed linearly through the entire list. - We print absolutely all registers in upper-case, even though some are canonically mixed case (SPSel for example). - The ARM ARM specifies sysregs in terms of 5 fields, but those are relegated to comments in our implementation, with a slightly opaque hex value indicating the canonical encoding LLVM will use. This adds a new TableGen backend to produce efficiently searchable tables, and switches AArch64 over to using that infrastructure. llvm-svn: 274576
2016-07-06 05:23:04 +08:00
case GenSearchableTables:
EmitSearchableTables(Records, OS);
break;
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-22 07:26:20 +08:00
case GenGlobalISel:
EmitGlobalISel(Records, OS);
[globalisel] Fix missing break. The instruction selector has been emitting the register bank information too. llvm-svn: 294007
2017-02-03 22:18:35 +08:00
break;
[gicombiner] Add the boring boilerplate for the declarative combiner Summary: This is the first of a series of patches extracted from a much bigger WIP patch. It merely establishes the tblgen pass and the way empty combiner helpers are declared and integrated into a combiner info. The tablegen pass takes a -combiners option to select the combiner helper that will be generated. This can be given multiple values to generate multiple combiner helpers at once. Doing so helps to minimize parsing overhead. The reason for creating a GlobalISel subdirectory in utils/TableGen is that there will be quite a lot of non-pass files (~15) by the time the patch series is done. Reviewers: volkan Subscribers: mgorny, hiraditya, simoncook, Petar.Avramovic, s.egerton, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D68286 llvm-svn: 373527
2019-10-03 05:13:07 +08:00
case GenGICombiner:
EmitGICombiner(Records, OS);
break;
Re-commit: [globalisel] Tablegen-erate current Register Bank Information Summary: Adds a RegisterBank tablegen class that can be used to declare the register banks and an associated tablegen pass to generate the necessary code. Changes since first commit attempt: * Added missing guards * Added more missing guards * Found and fixed a use-after-free bug involving Twine locals Reviewers: t.p.northover, ab, rovka, qcolombet Reviewed By: qcolombet Subscribers: aditya_nandakumar, rengolin, kristof.beyls, vkalintiris, mgorny, dberris, llvm-commits, rovka Differential Revision: https://reviews.llvm.org/D27338 llvm-svn: 292478
2017-01-19 19:15:55 +08:00
case GenRegisterBank:
EmitRegisterBank(Records, OS);
[GlobalISel] Add basic Selector-emitter tblgen backend. This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
2016-12-22 07:26:20 +08:00
break;
[X86][AVX512] Adding new LLVM TableGen backend which generates the EVEX2VEX compressing tables. X86EvexToVex machine instruction pass compresses EVEX encoded instructions by replacing them with their identical VEX encoded instructions when possible. It uses manually supported 2 large tables that map the EVEX instructions to their VEX ideticals. This TableGen backend replaces the tables by automatically generating them. Differential Revision: https://reviews.llvm.org/D30451 llvm-svn: 297127
2017-03-07 16:11:19 +08:00
case GenX86EVEX2VEXTables:
EmitX86EVEX2VEXTables(Records, OS);
break;
[X86][TableGen] Recommitting the X86 memory folding tables TableGen backend while disabling it by default. After the original commit ([[ https://reviews.llvm.org/rL304088 | rL304088 ]]) was reverted, a discussion in llvm-dev was opened on 'how to accomplish this task'. In the discussion we concluded that the best way to achieve our goal (which is to automate the folding tables and remove the manually maintained tables) is: # Commit the tablegen backend disabled by default. # Proceed with an incremental updating of the manual tables - while checking the validity of each added entry. # Repeat previous step until we reach a state where the generated and the manual tables are identical. Then we can safely remove the manual tables and include the generated tables instead. # Schedule periodical (1 week/2 weeks/1 month) runs of the pass: - if changes appear (new entries): - make sure the entries are legal - If they are not, mark them as illegal to folding - Commit the changes (if there are any). CMake flag added for this purpose is "X86_GEN_FOLD_TABLES". Building with this flags will run the pass and emit the X86GenFoldTables.inc file under build/lib/Target/X86/ directory which is a good reference for any developer who wants to take part in the effort of completing the current folding tables. Differential Revision: https://reviews.llvm.org/D38028 llvm-svn: 315173
2017-10-08 17:20:32 +08:00
case GenX86FoldTables:
EmitX86FoldTables(Records, OS);
break;
[MCSched] Bind PFM Counters to the CPUs instead of the SchedModel. Summary: The pfm counters are now in the ExegesisTarget rather than the MCSchedModel (PR39165). This also compresses the pfm counter tables (PR37068). Reviewers: RKSimon, gchatelet Subscribers: mgrang, llvm-commits Differential Revision: https://reviews.llvm.org/D52932 llvm-svn: 345243
2018-10-25 15:44:01 +08:00
case GenExegesis:
EmitExegesis(Records, OS);
break;
[TableGen] Introduce a generic automaton (DFA) backend Summary: This patch introduces -gen-automata, a backend for generating deterministic finite-state automata. DFAs are already generated by the -gen-dfa-packetizer backend. This backend is more generic and will hopefully be used to implement the DFA generation (and determinization) for the packetizer in the future. This backend allows not only generation of a DFA from an NFA (nondeterministic finite-state automaton), it also emits sidetables that allow a path through the DFA under a sequence of inputs to be analyzed, and the equivalent set of all possible NFA transitions extracted. This allows a user to not just answer "can my problem be solved?" but also "what is the solution?". Clearly this analysis is more expensive than just playing a DFA forwards so is opt-in. The DFAPacketizer has this behaviour already but this is a more compact and generic representation. Examples are bundled in unittests/TableGen/Automata.td. Some are trivial, but the BinPacking example is a stripped-down version of the original target problem I set out to solve, where we pack values (actually immediates) into bins (an immediate pool in a VLIW bundle) subject to a set of esoteric constraints. Reviewers: t.p.northover Subscribers: mgorny, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67968 llvm-svn: 373718
2019-10-04 17:03:36 +08:00
case GenAutomata:
EmitAutomata(Records, OS);
break;
tblgen: Migrate llvm-tblgen to new TableGenMain API. llvm-svn: 165166
2012-10-04 05:29:19 +08:00
}
return false;
}
Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch llvm-svn: 146960
2011-12-20 10:50:00 +08:00
}
Move TableGen's parser and entry point into a library This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
2011-10-02 00:41:13 +08:00
int main(int argc, char **argv) {
Search for llvm-symbolizer binary in the same directory as argv[0], before looking for it along $PATH. This allows installs of LLVM tools outside of $PATH to find the symbolizer and produce pretty backtraces if they crash. llvm-svn: 272232
2016-06-09 08:53:21 +08:00
sys::PrintStackTraceOnErrorSignal(argv[0]);
Move TableGen's parser and entry point into a library This is the first step towards splitting LLVM and Clang's tblgen executables. llvm-svn: 140951
2011-10-02 00:41:13 +08:00
PrettyStackTraceProgram X(argc, argv);
cl::ParseCommandLineOptions(argc, argv);
Add an emitter to handle the list of clang statement nodes. llvm-svn: 103071
2010-05-05 12:13:08 +08:00
[TableGen] Call llvm_shutdown on exit so that all the ManagedStatic objects in the support library will be deleted. llvm-svn: 256732
2016-01-04 12:51:51 +08:00
llvm_shutdown_obj Y;
tblgen: Migrate llvm-tblgen to new TableGenMain API. llvm-svn: 165166
2012-10-04 05:29:19 +08:00
return TableGenMain(argv[0], &LLVMTableGenMain);
Move support/tools/* back into utils llvm-svn: 8875
2003-10-06 03:27:59 +08:00
}
reapply r198858: Disable LeakSanitizer in TableGen binaries, see PR18325; this time LeakSanitizerIsTurnedOffForTheCurrentProcess is used instead of __lsan_is_turned_off llvm-svn: 198922
2014-01-10 16:05:42 +08:00
[tblgen] Disable Leak detection for ASan/GCC and LSan/LLVM Summary: Add support for sanitizing TableGen.cpp with ASan/GCC and LSan/LLVM. Reviewers: fjricci, kcc, aaron.ballman, mgorny Reviewed By: fjricci Subscribers: jakubjelinek, llvm-commits, #llvm Tags: #llvm Differential Revision: https://reviews.llvm.org/D67908 llvm-svn: 372731
2019-09-24 19:22:34 +08:00
#ifndef __has_feature
#define __has_feature(x) 0
#endif
#if __has_feature(address_sanitizer) || defined(__SANITIZE_ADDRESS__) || \
__has_feature(leak_sanitizer)
replace LeakSanitizerIsTurnedOffForTheCurrentProcess with __lsan_is_turned_off, but this time hide it under __has_feature(address_sanitizer); also include <sanitizer/lsan_interface.h> llvm-svn: 199303
2014-01-15 15:59:37 +08:00
#include <sanitizer/lsan_interface.h>
reapply r198858: Disable LeakSanitizer in TableGen binaries, see PR18325; this time LeakSanitizerIsTurnedOffForTheCurrentProcess is used instead of __lsan_is_turned_off llvm-svn: 198922
2014-01-10 16:05:42 +08:00
// Disable LeakSanitizer for this binary as it has too many leaks that are not
replace LeakSanitizerIsTurnedOffForTheCurrentProcess with __lsan_is_turned_off, but this time hide it under __has_feature(address_sanitizer); also include <sanitizer/lsan_interface.h> llvm-svn: 199303
2014-01-15 15:59:37 +08:00
// very interesting to fix. See compiler-rt/include/sanitizer/lsan_interface.h .
[TableGen] Ensure that __lsan_is_turned_off isn't removed by DCE in llvm-tblgen Summary: Since asan is linked dynamically on Darwin, the weak interface symbol is removed by -Wl,-dead_strip. Reviewers: kcc, compnerd, aaron.ballman Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D37636 llvm-svn: 312914
2017-09-11 21:50:39 +08:00
LLVM_ATTRIBUTE_USED int __lsan_is_turned_off() { return 1; }
[tblgen] Disable Leak detection for ASan/GCC and LSan/LLVM Summary: Add support for sanitizing TableGen.cpp with ASan/GCC and LSan/LLVM. Reviewers: fjricci, kcc, aaron.ballman, mgorny Reviewed By: fjricci Subscribers: jakubjelinek, llvm-commits, #llvm Tags: #llvm Differential Revision: https://reviews.llvm.org/D67908 llvm-svn: 372731
2019-09-24 19:22:34 +08:00
#endif