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llvm-project/llvm/test/CodeGen/SystemZ/fp-copysign-02.ll

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[SystemZ] Add support for IBM z14 processor (3/3) This adds support for the new 128-bit vector float instructions of z14. Note that these instructions actually only operate on the f128 type, since only each 128-bit vector register can hold only one 128-bit float value. However, this is still preferable to the legacy 128-bit float instructions, since those operate on pairs of floating-point registers (so we can hold at most 8 values in registers), while the new instructions use single vector registers (so we hold up to 32 value in registers). Adding support includes: - Enabling the instructions for the assembler/disassembler. - CodeGen for the instructions. This includes allocating the f128 type now to the VR128BitRegClass instead of FP128BitRegClass. - Scheduler description support for the instructions. Note that for a small number of operations, we have no new vector instructions (like integer <-> 128-bit float conversions), and so we use the legacy instruction and then reformat the operand (i.e. copy between a pair of floating-point registers and a vector register). llvm-svn: 308196
2017-07-18 01:44:20 +08:00
; Test f128 copysign operations on z14.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
declare float @copysignf(float, float) readnone
declare double @copysign(double, double) readnone
; FIXME: not really the correct prototype for SystemZ.
declare fp128 @copysignl(fp128, fp128) readnone
; Test f32 copies in which the sign comes from an f128.
define float @f1(float %a, fp128 *%bptr) {
; CHECK-LABEL: f1:
; CHECK: vl %v[[REG:[0-9]+]], 0(%r2)
; CHECK: cpsdr %f0, %f[[REG]], %f0
; CHECK: br %r14
%bl = load volatile fp128, fp128 *%bptr
%b = fptrunc fp128 %bl to float
%res = call float @copysignf(float %a, float %b) readnone
ret float %res
}
; Test f64 copies in which the sign comes from an f128.
define double @f2(double %a, fp128 *%bptr) {
; CHECK-LABEL: f2:
; CHECK: vl %v[[REG:[0-9]+]], 0(%r2)
; CHECK: cpsdr %f0, %f[[REG]], %f0
; CHECK: br %r14
%bl = load volatile fp128, fp128 *%bptr
%b = fptrunc fp128 %bl to double
%res = call double @copysign(double %a, double %b) readnone
ret double %res
}
; Test f128 copies in which the sign comes from an f32.
define void @f7(fp128 *%cptr, fp128 *%aptr, float %bf) {
; CHECK-LABEL: f7:
; CHECK: vl [[REG1:%v[0-7]+]], 0(%r3)
; CHECK: tmlh
[SystemZ] Enable machine scheduler. The machine scheduler (before register allocation) is enabled by default for SystemZ. The SelectionDAG scheduling preference now becomes source order scheduling (was regpressure). Review: Ulrich Weigand https://reviews.llvm.org/D37977 llvm-svn: 315063
2017-10-06 21:59:28 +08:00
; CHECK: wflnxb [[REG2:%v[0-9]+]], [[REG1]]
; CHECK: wflpxb [[REG2]], [[REG1]]
; CHECK: vst [[REG2]], 0(%r2)
[SystemZ] Add support for IBM z14 processor (3/3) This adds support for the new 128-bit vector float instructions of z14. Note that these instructions actually only operate on the f128 type, since only each 128-bit vector register can hold only one 128-bit float value. However, this is still preferable to the legacy 128-bit float instructions, since those operate on pairs of floating-point registers (so we can hold at most 8 values in registers), while the new instructions use single vector registers (so we hold up to 32 value in registers). Adding support includes: - Enabling the instructions for the assembler/disassembler. - CodeGen for the instructions. This includes allocating the f128 type now to the VR128BitRegClass instead of FP128BitRegClass. - Scheduler description support for the instructions. Note that for a small number of operations, we have no new vector instructions (like integer <-> 128-bit float conversions), and so we use the legacy instruction and then reformat the operand (i.e. copy between a pair of floating-point registers and a vector register). llvm-svn: 308196
2017-07-18 01:44:20 +08:00
; CHECK: br %r14
%a = load volatile fp128, fp128 *%aptr
%b = fpext float %bf to fp128
%c = call fp128 @copysignl(fp128 %a, fp128 %b) readnone
store fp128 %c, fp128 *%cptr
ret void
}
; As above, but the sign comes from an f64.
define void @f8(fp128 *%cptr, fp128 *%aptr, double %bd) {
; CHECK-LABEL: f8:
; CHECK: vl [[REG1:%v[0-7]+]], 0(%r3)
; CHECK: tmhh
[SystemZ] Enable machine scheduler. The machine scheduler (before register allocation) is enabled by default for SystemZ. The SelectionDAG scheduling preference now becomes source order scheduling (was regpressure). Review: Ulrich Weigand https://reviews.llvm.org/D37977 llvm-svn: 315063
2017-10-06 21:59:28 +08:00
; CHECK: wflnxb [[REG2:%v[0-9]+]], [[REG1]]
; CHECK: wflpxb [[REG2]], [[REG1]]
; CHECK: vst [[REG2]], 0(%r2)
[SystemZ] Add support for IBM z14 processor (3/3) This adds support for the new 128-bit vector float instructions of z14. Note that these instructions actually only operate on the f128 type, since only each 128-bit vector register can hold only one 128-bit float value. However, this is still preferable to the legacy 128-bit float instructions, since those operate on pairs of floating-point registers (so we can hold at most 8 values in registers), while the new instructions use single vector registers (so we hold up to 32 value in registers). Adding support includes: - Enabling the instructions for the assembler/disassembler. - CodeGen for the instructions. This includes allocating the f128 type now to the VR128BitRegClass instead of FP128BitRegClass. - Scheduler description support for the instructions. Note that for a small number of operations, we have no new vector instructions (like integer <-> 128-bit float conversions), and so we use the legacy instruction and then reformat the operand (i.e. copy between a pair of floating-point registers and a vector register). llvm-svn: 308196
2017-07-18 01:44:20 +08:00
; CHECK: br %r14
%a = load volatile fp128, fp128 *%aptr
%b = fpext double %bd to fp128
%c = call fp128 @copysignl(fp128 %a, fp128 %b) readnone
store fp128 %c, fp128 *%cptr
ret void
}
; As above, but the sign comes from an f128.
define void @f9(fp128 *%cptr, fp128 *%aptr, fp128 *%bptr) {
; CHECK-LABEL: f9:
; CHECK: vl [[REG1:%v[0-7]+]], 0(%r3)
; CHECK: vl [[REG2:%v[0-7]+]], 0(%r4)
; CHECK: tm
; CHECK: wflnxb [[REG1]], [[REG1]]
; CHECK: wflpxb [[REG1]], [[REG1]]
; CHECK: vst [[REG1]], 0(%r2)
; CHECK: br %r14
%a = load volatile fp128, fp128 *%aptr
%b = load volatile fp128, fp128 *%bptr
%c = call fp128 @copysignl(fp128 %a, fp128 %b) readnone
store fp128 %c, fp128 *%cptr
ret void
}