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llvm-project/llvm/test/CodeGen/X86/GlobalISel/select-merge-vec256.mir

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GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 07:33:31 +08:00
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
[globalisel] Remove redundant -global-isel option from tests that use -run-pass. NFC As Roman Tereshin pointed out in https://reviews.llvm.org/D45541, the -global-isel option is redundant when -run-pass is given. -global-isel sets up the GlobalISel passes in the pass manager but -run-pass skips that entirely and configures it's own pipeline. llvm-svn: 331603
2018-05-06 05:19:59 +08:00
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512vl -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=AVX512VL
[GlobalISel][X86] Support vector type G_MERGE_VALUES selection. Summary: Support vector type G_MERGE_VALUES selection. For now G_MERGE_VALUES marked as legal for any type, so nothing to do in legalizer. Split from https://reviews.llvm.org/D33665 Reviewers: qcolombet, t.p.northover, zvi, guyblank Reviewed By: guyblank Subscribers: rovka, kristof.beyls, guyblank, llvm-commits Differential Revision: https://reviews.llvm.org/D33958 llvm-svn: 306665
2017-06-29 20:08:28 +08:00
--- |
define void @test_merge() {
ret void
}
...
---
name: test_merge
#
alignment: 4
legalized: true
regBankSelected: true
#
registers:
- { id: 0, class: vecr }
- { id: 1, class: vecr }
#
body: |
bb.1 (%ir-block.0):
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 07:33:31 +08:00
; AVX-LABEL: name: test_merge
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
; AVX: [[DEF:%[0-9]+]]:vr128 = IMPLICIT_DEF
; AVX: undef %2.sub_xmm:vr256 = COPY [[DEF]]
; AVX: [[VINSERTF128rr:%[0-9]+]]:vr256 = VINSERTF128rr %2, [[DEF]], 1
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
; AVX: $ymm0 = COPY [[VINSERTF128rr]]
; AVX: RET 0, implicit $ymm0
GISel: Canonicalize select tests using update_mir_test_checks This runs `udpate_mir_test_checks --add-vreg-checks` on the tests taht are already more or less in the format that generates, so that there will be less churn in some upcoming changes. llvm-svn: 316139
2017-10-19 07:33:31 +08:00
; AVX512VL-LABEL: name: test_merge
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
; AVX512VL: [[DEF:%[0-9]+]]:vr128x = IMPLICIT_DEF
; AVX512VL: undef %2.sub_xmm:vr256x = COPY [[DEF]]
; AVX512VL: [[VINSERTF32x4Z256rr:%[0-9]+]]:vr256x = VINSERTF32x4Z256rr %2, [[DEF]], 1
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
; AVX512VL: $ymm0 = COPY [[VINSERTF32x4Z256rr]]
; AVX512VL: RET 0, implicit $ymm0
[GlobalISel][X86] Support vector type G_MERGE_VALUES selection. Summary: Support vector type G_MERGE_VALUES selection. For now G_MERGE_VALUES marked as legal for any type, so nothing to do in legalizer. Split from https://reviews.llvm.org/D33665 Reviewers: qcolombet, t.p.northover, zvi, guyblank Reviewed By: guyblank Subscribers: rovka, kristof.beyls, guyblank, llvm-commits Differential Revision: https://reviews.llvm.org/D33958 llvm-svn: 306665
2017-06-29 20:08:28 +08:00
%0(<4 x s32>) = IMPLICIT_DEF
%1(<8 x s32>) = G_MERGE_VALUES %0(<4 x s32>), %0(<4 x s32>)
Followup on Proposal to move MIR physical register namespace to '$' sigil. Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
2018-02-01 06:04:26 +08:00
$ymm0 = COPY %1(<8 x s32>)
RET 0, implicit $ymm0
[GlobalISel][X86] Support vector type G_MERGE_VALUES selection. Summary: Support vector type G_MERGE_VALUES selection. For now G_MERGE_VALUES marked as legal for any type, so nothing to do in legalizer. Split from https://reviews.llvm.org/D33665 Reviewers: qcolombet, t.p.northover, zvi, guyblank Reviewed By: guyblank Subscribers: rovka, kristof.beyls, guyblank, llvm-commits Differential Revision: https://reviews.llvm.org/D33958 llvm-svn: 306665
2017-06-29 20:08:28 +08:00
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