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llvm-project/lld/test/mach-o/parse-arm-relocs.yaml

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[mach-o] add support for round tripping all arm/thumb relocations Update the parse-arm-relocs.yaml test case to run the linker back to back to ensure all relocations round trip in and out of mach-o. llvm-svn: 213700
2014-07-23 07:07:49 +08:00
# RUN: lld -flavor darwin -arch armv7 -r -print_atoms %s -o %t | FileCheck %s \
# RUN: && lld -flavor darwin -arch armv7 -r -print_atoms %t -o %t2 | FileCheck %s
[mach-o] Add parsing of arm/thumb relocations This converts the very complicated mach-o arm relocations into the simple Reference Kinds in lld. The next patch will use the internal Reference kinds to fix up arm/thumb code. llvm-svn: 212306
2014-07-04 08:11:09 +08:00
#
# Test parsing of armv7 relocations.
#
#
--- !mach-o
arch: armv7
file-type: MH_OBJECT
flags: [ MH_SUBSECTIONS_VIA_SYMBOLS ]
has-UUID: false
OS: unknown
sections:
- segment: __TEXT
section: __text
type: S_REGULAR
attributes: [ S_ATTR_PURE_INSTRUCTIONS, S_ATTR_SOME_INSTRUCTIONS ]
alignment: 2
address: 0x0000000000000000
content: [ 0x00, 0xF0, 0x4A, 0xF8, 0x00, 0xF0, 0x4A, 0xF8,
0xFF, 0xF7, 0xFA, 0xFF, 0xFF, 0xF7, 0xFA, 0xFF,
0x40, 0xF2, 0x6E, 0x01, 0xC0, 0xF2, 0x00, 0x01,
0x40, 0xF2, 0x76, 0x02, 0xC0, 0xF2, 0x00, 0x02,
0x40, 0xF2, 0x29, 0x01, 0xC0, 0xF2, 0x00, 0x01,
0x79, 0x44, 0x40, 0xF2, 0x98, 0x03, 0xC0, 0xF2,
0x00, 0x03, 0x40, 0xF2, 0xA0, 0x04, 0xC0, 0xF2,
0x00, 0x04, 0x40, 0xF2, 0x53, 0x03, 0xC0, 0xF2,
0x00, 0x03, 0x40, 0xF2, 0x00, 0x05, 0xC0, 0xF2,
0x00, 0x05, 0x40, 0xF2, 0x08, 0x06, 0xC0, 0xF2,
0x00, 0x06, 0xC0, 0x46, 0x0F, 0x00, 0x00, 0xEB,
0x0F, 0x00, 0x00, 0xEB, 0xE7, 0xFF, 0xFF, 0xEB,
0xE7, 0xFF, 0xFF, 0xEB, 0x20, 0x10, 0x00, 0xE3,
0x00, 0x10, 0x40, 0xE3, 0x28, 0x20, 0x00, 0xE3,
0x00, 0x20, 0x40, 0xE3, 0x0F, 0x10, 0x81, 0xE0,
0x98, 0x30, 0x00, 0xE3, 0x00, 0x30, 0x40, 0xE3,
0xA0, 0x40, 0x00, 0xE3, 0x00, 0x40, 0x40, 0xE3,
0x00, 0x50, 0x00, 0xE3, 0x00, 0x50, 0x40, 0xE3,
0x08, 0x60, 0x00, 0xE3, 0x00, 0x60, 0x40, 0xE3 ]
relocations:
- offset: 0x00000094
type: ARM_RELOC_HALF
length: 1
pc-rel: false
extern: true
symbol: 4
- offset: 0x00000008
type: ARM_RELOC_PAIR
length: 1
pc-rel: false
extern: false
symbol: 16777215
- offset: 0x00000090
type: ARM_RELOC_HALF
length: 0
pc-rel: false
extern: true
symbol: 4
- offset: 0x00000000
type: ARM_RELOC_PAIR
length: 0
pc-rel: false
extern: false
symbol: 16777215
- offset: 0x0000008C
type: ARM_RELOC_HALF
length: 1
pc-rel: false
extern: true
symbol: 4
- offset: 0x00000000
type: ARM_RELOC_PAIR
length: 1
pc-rel: false
extern: false
symbol: 16777215
- offset: 0x00000088
type: ARM_RELOC_HALF
length: 0
pc-rel: false
extern: true
symbol: 4
- offset: 0x00000000
type: ARM_RELOC_PAIR
length: 0
pc-rel: false
extern: false
symbol: 16777215
- offset: 0x00000084
scattered: true
type: ARM_RELOC_HALF
length: 1
pc-rel: false
value: 0x00000098
- offset: 0x000000A0
type: ARM_RELOC_PAIR
length: 1
pc-rel: false
extern: false
symbol: 16777215
- offset: 0x00000080
scattered: true
type: ARM_RELOC_HALF
length: 0
pc-rel: false
value: 0x00000098
- offset: 0x00000000
type: ARM_RELOC_PAIR
length: 0
pc-rel: false
extern: false
symbol: 16777215
- offset: 0x0000007C
type: ARM_RELOC_HALF
length: 1
pc-rel: false
extern: false
symbol: 2
- offset: 0x00000098
type: ARM_RELOC_PAIR
length: 1
pc-rel: false
extern: false
symbol: 16777215
- offset: 0x00000078
type: ARM_RELOC_HALF
length: 0
pc-rel: false
extern: false
symbol: 2
- offset: 0x00000000
type: ARM_RELOC_PAIR
length: 0
pc-rel: false
extern: false
symbol: 16777215
- offset: 0x00000070
scattered: true
type: ARM_RELOC_HALF_SECTDIFF
length: 1
pc-rel: false
value: 0x00000098
- offset: 0x00000028
scattered: true
type: ARM_RELOC_PAIR
length: 1
pc-rel: false
value: 0x00000078
- offset: 0x0000006C
scattered: true
type: ARM_RELOC_HALF_SECTDIFF
length: 0
pc-rel: false
value: 0x00000098
- offset: 0x00000000
scattered: true
type: ARM_RELOC_PAIR
length: 0
pc-rel: false
value: 0x00000078
- offset: 0x00000068
scattered: true
type: ARM_RELOC_HALF_SECTDIFF
length: 1
pc-rel: false
value: 0x00000098
- offset: 0x00000020
scattered: true
type: ARM_RELOC_PAIR
length: 1
pc-rel: false
value: 0x00000078
- offset: 0x00000064
scattered: true
type: ARM_RELOC_HALF_SECTDIFF
length: 0
pc-rel: false
value: 0x00000098
- offset: 0x00000000
scattered: true
type: ARM_RELOC_PAIR
length: 0
pc-rel: false
value: 0x00000078
- offset: 0x00000060
type: ARM_RELOC_BR24
length: 2
pc-rel: true
extern: true
symbol: 4
- offset: 0x0000005C
type: ARM_RELOC_BR24
length: 2
pc-rel: true
extern: true
symbol: 4
- offset: 0x00000058
scattered: true
type: ARM_RELOC_BR24
length: 2
pc-rel: true
value: 0x00000098
- offset: 0x00000054
type: ARM_RELOC_BR24
length: 2
pc-rel: true
extern: false
symbol: 2
- offset: 0x0000004E
type: ARM_RELOC_HALF
length: 3
pc-rel: false
extern: true
symbol: 4
- offset: 0x00000008
type: ARM_RELOC_PAIR
length: 3
pc-rel: false
extern: false
symbol: 16777215
- offset: 0x0000004A
type: ARM_RELOC_HALF
length: 2
pc-rel: false
extern: true
symbol: 4
- offset: 0x00000000
type: ARM_RELOC_PAIR
length: 2
pc-rel: false
extern: false
symbol: 16777215
- offset: 0x00000046
type: ARM_RELOC_HALF
length: 3
pc-rel: false
extern: true
symbol: 4
- offset: 0x00000000
type: ARM_RELOC_PAIR
length: 3
pc-rel: false
extern: false
symbol: 16777215
- offset: 0x00000042
type: ARM_RELOC_HALF
length: 2
pc-rel: false
extern: true
symbol: 4
- offset: 0x00000000
type: ARM_RELOC_PAIR
length: 2
pc-rel: false
extern: false
symbol: 16777215
- offset: 0x0000003E
type: ARM_RELOC_HALF
length: 3
pc-rel: false
extern: false
symbol: 1
- offset: 0x00000053
type: ARM_RELOC_PAIR
length: 3
pc-rel: false
extern: false
symbol: 16777215
- offset: 0x0000003A
type: ARM_RELOC_HALF
length: 2
pc-rel: false
extern: false
symbol: 1
- offset: 0x00000000
type: ARM_RELOC_PAIR
length: 2
pc-rel: false
extern: false
symbol: 16777215
- offset: 0x00000036
scattered: true
type: ARM_RELOC_HALF
length: 3
pc-rel: false
value: 0x00000098
- offset: 0x000000A0
type: ARM_RELOC_PAIR
length: 3
pc-rel: false
extern: false
symbol: 16777215
- offset: 0x00000032
scattered: true
type: ARM_RELOC_HALF
length: 2
pc-rel: false
value: 0x00000098
- offset: 0x00000000
type: ARM_RELOC_PAIR
length: 2
pc-rel: false
extern: false
symbol: 16777215
- offset: 0x0000002E
type: ARM_RELOC_HALF
length: 3
pc-rel: false
extern: false
symbol: 2
- offset: 0x00000098
type: ARM_RELOC_PAIR
length: 3
pc-rel: false
extern: false
symbol: 16777215
- offset: 0x0000002A
type: ARM_RELOC_HALF
length: 2
pc-rel: false
extern: false
symbol: 2
- offset: 0x00000000
type: ARM_RELOC_PAIR
length: 2
pc-rel: false
extern: false
symbol: 16777215
- offset: 0x00000024
scattered: true
type: ARM_RELOC_HALF_SECTDIFF
length: 3
pc-rel: false
value: 0x00000052
- offset: 0x00000028
scattered: true
type: ARM_RELOC_PAIR
length: 3
pc-rel: false
value: 0x0000002A
- offset: 0x00000020
scattered: true
type: ARM_RELOC_HALF_SECTDIFF
length: 2
pc-rel: false
value: 0x00000052
- offset: 0x00000000
scattered: true
type: ARM_RELOC_PAIR
length: 2
pc-rel: false
value: 0x0000002A
- offset: 0x0000001C
scattered: true
type: ARM_RELOC_HALF_SECTDIFF
length: 3
pc-rel: false
value: 0x00000098
- offset: 0x00000076
scattered: true
type: ARM_RELOC_PAIR
length: 3
pc-rel: false
value: 0x0000002A
- offset: 0x00000018
scattered: true
type: ARM_RELOC_HALF_SECTDIFF
length: 2
pc-rel: false
value: 0x00000098
- offset: 0x00000000
scattered: true
type: ARM_RELOC_PAIR
length: 2
pc-rel: false
value: 0x0000002A
- offset: 0x00000014
scattered: true
type: ARM_RELOC_HALF_SECTDIFF
length: 3
pc-rel: false
value: 0x00000098
- offset: 0x0000006E
scattered: true
type: ARM_RELOC_PAIR
length: 3
pc-rel: false
value: 0x0000002A
- offset: 0x00000010
scattered: true
type: ARM_RELOC_HALF_SECTDIFF
length: 2
pc-rel: false
value: 0x00000098
- offset: 0x00000000
scattered: true
type: ARM_RELOC_PAIR
length: 2
pc-rel: false
value: 0x0000002A
- offset: 0x0000000C
type: ARM_THUMB_RELOC_BR22
length: 2
pc-rel: true
extern: true
symbol: 4
- offset: 0x00000008
type: ARM_THUMB_RELOC_BR22
length: 2
pc-rel: true
extern: true
symbol: 4
- offset: 0x00000004
scattered: true
type: ARM_THUMB_RELOC_BR22
length: 2
pc-rel: true
value: 0x00000098
- offset: 0x00000000
type: ARM_THUMB_RELOC_BR22
length: 2
pc-rel: true
extern: false
symbol: 2
- segment: __DATA
section: __data
type: S_REGULAR
attributes: [ ]
address: 0x0000000000000098
content: [ 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x04, 0x00, 0x00, 0x00, 0xA8, 0xFF, 0xFF, 0xFF,
0xA8, 0xFF, 0xFF, 0xFF, 0x4D, 0xFF, 0xFF, 0xFF,
0x4D, 0xFF, 0xFF, 0xFF ]
relocations:
- offset: 0x00000020
scattered: true
type: ARM_RELOC_SECTDIFF
length: 2
pc-rel: false
value: 0x00000000
- offset: 0x00000000
scattered: true
type: ARM_RELOC_PAIR
length: 2
pc-rel: false
value: 0x000000B8
- offset: 0x0000001C
scattered: true
type: ARM_RELOC_SECTDIFF
length: 2
pc-rel: false
value: 0x00000000
- offset: 0x00000000
scattered: true
type: ARM_RELOC_PAIR
length: 2
pc-rel: false
value: 0x000000B4
- offset: 0x00000018
scattered: true
type: ARM_RELOC_SECTDIFF
length: 2
pc-rel: false
value: 0x00000054
- offset: 0x00000000
scattered: true
type: ARM_RELOC_PAIR
length: 2
pc-rel: false
value: 0x000000B0
- offset: 0x00000014
scattered: true
type: ARM_RELOC_SECTDIFF
length: 2
pc-rel: false
value: 0x00000054
- offset: 0x00000000
scattered: true
type: ARM_RELOC_PAIR
length: 2
pc-rel: false
value: 0x000000AC
- offset: 0x00000010
type: ARM_RELOC_VANILLA
length: 2
pc-rel: false
extern: true
symbol: 4
- offset: 0x0000000C
type: ARM_RELOC_VANILLA
length: 2
pc-rel: false
extern: true
symbol: 4
- offset: 0x00000008
scattered: true
type: ARM_RELOC_VANILLA
length: 2
pc-rel: false
value: 0x00000000
- offset: 0x00000004
type: ARM_RELOC_VANILLA
length: 2
pc-rel: false
extern: false
symbol: 1
local-symbols:
- name: _foo_thumb
type: N_SECT
sect: 1
desc: [ N_ARM_THUMB_DEF ]
value: 0x0000000000000000
- name: _x
type: N_SECT
sect: 2
value: 0x0000000000000098
- name: _t1
type: N_SECT
sect: 1
desc: [ N_ARM_THUMB_DEF ]
value: 0x0000000000000052
- name: _foo_arm
type: N_SECT
sect: 1
value: 0x0000000000000054
undefined-symbols:
- name: _undef
type: N_UNDF
scope: [ N_EXT ]
value: 0x0000000000000000
...
# CHECK: defined-atoms:
# CHECK: - name: _x
# CHECK: type: data
# CHECK: references:
# CHECK: - kind: pointer32
# CHECK: offset: 4
# CHECK: target: _foo_thumb
# CHECK-NOT: addend:
# CHECK: - kind: pointer32
# CHECK: offset: 8
# CHECK: target: _foo_thumb
# CHECK: addend: 4
# CHECK: - kind: pointer32
# CHECK: offset: 12
# CHECK: target: _undef
# CHECK-NOT: addend:
# CHECK: - kind: pointer32
# CHECK: offset: 16
# CHECK: target: _undef
# CHECK: addend: 4
# CHECK: - kind: delta32
# CHECK: offset: 20
# CHECK: target: _foo_arm
# CHECK-NOT: addend:
# CHECK: - kind: delta32
# CHECK: offset: 24
# CHECK: target: _foo_arm
# CHECK: addend: 4
# CHECK: - kind: delta32
# CHECK: offset: 28
# CHECK: target: _foo_thumb
# CHECK-NOT: addend:
# CHECK: - kind: delta32
# CHECK: offset: 32
# CHECK: target: _foo_thumb
# CHECK: addend: 4
# CHECK: - name: _foo_thumb
# CHECK: references:
[mach-o] add initial support for modes in arm code. This patch just supports marking ranges that are thumb code (vs arm code). Future patches will mark data and jump table ranges. The ranges are encoded as References with offsetInAtom being the start of the range and the target being the same atom. llvm-svn: 213712
2014-07-23 08:51:37 +08:00
# CHECK: - kind: modeThumbCode
# CHECK: offset: 0
[mach-o] Add Pass to create are shim Atoms for ARM interworking. Arm code has two instruction encodings "thumb" and "arm". When branching from one code encoding to another, you need to use an instruction that switches the instruction mode. Usually the transition only happens at call sites, and the linker can transform a BL instruction in BLX (or vice versa). But if the compiler did a tail call optimization and a function ends with a branch (not branch and link), there is no pc-rel BX instruction. The ShimPass looks for pc-rel B instructions that will need to switch mode. For those cases it synthesizes a shim which does the transition, then modifies the original atom with the B instruction to target to the shim atom. llvm-svn: 219655
2014-10-14 09:51:42 +08:00
# CHECK: - kind: thumb_bl22
[mach-o] Add parsing of arm/thumb relocations This converts the very complicated mach-o arm relocations into the simple Reference Kinds in lld. The next patch will use the internal Reference kinds to fix up arm/thumb code. llvm-svn: 212306
2014-07-04 08:11:09 +08:00
# CHECK: offset: 0
# CHECK: target: _x
# CHECK-NOT: addend:
[mach-o] Add Pass to create are shim Atoms for ARM interworking. Arm code has two instruction encodings "thumb" and "arm". When branching from one code encoding to another, you need to use an instruction that switches the instruction mode. Usually the transition only happens at call sites, and the linker can transform a BL instruction in BLX (or vice versa). But if the compiler did a tail call optimization and a function ends with a branch (not branch and link), there is no pc-rel BX instruction. The ShimPass looks for pc-rel B instructions that will need to switch mode. For those cases it synthesizes a shim which does the transition, then modifies the original atom with the B instruction to target to the shim atom. llvm-svn: 219655
2014-10-14 09:51:42 +08:00
# CHECK: - kind: thumb_bl22
[mach-o] Add parsing of arm/thumb relocations This converts the very complicated mach-o arm relocations into the simple Reference Kinds in lld. The next patch will use the internal Reference kinds to fix up arm/thumb code. llvm-svn: 212306
2014-07-04 08:11:09 +08:00
# CHECK: offset: 4
# CHECK: target: _x
# CHECK: addend: 4
[mach-o] Add Pass to create are shim Atoms for ARM interworking. Arm code has two instruction encodings "thumb" and "arm". When branching from one code encoding to another, you need to use an instruction that switches the instruction mode. Usually the transition only happens at call sites, and the linker can transform a BL instruction in BLX (or vice versa). But if the compiler did a tail call optimization and a function ends with a branch (not branch and link), there is no pc-rel BX instruction. The ShimPass looks for pc-rel B instructions that will need to switch mode. For those cases it synthesizes a shim which does the transition, then modifies the original atom with the B instruction to target to the shim atom. llvm-svn: 219655
2014-10-14 09:51:42 +08:00
# CHECK: - kind: thumb_bl22
[mach-o] Add parsing of arm/thumb relocations This converts the very complicated mach-o arm relocations into the simple Reference Kinds in lld. The next patch will use the internal Reference kinds to fix up arm/thumb code. llvm-svn: 212306
2014-07-04 08:11:09 +08:00
# CHECK: offset: 8
# CHECK: target: _undef
# CHECK-NOT: addend:
[mach-o] Add Pass to create are shim Atoms for ARM interworking. Arm code has two instruction encodings "thumb" and "arm". When branching from one code encoding to another, you need to use an instruction that switches the instruction mode. Usually the transition only happens at call sites, and the linker can transform a BL instruction in BLX (or vice versa). But if the compiler did a tail call optimization and a function ends with a branch (not branch and link), there is no pc-rel BX instruction. The ShimPass looks for pc-rel B instructions that will need to switch mode. For those cases it synthesizes a shim which does the transition, then modifies the original atom with the B instruction to target to the shim atom. llvm-svn: 219655
2014-10-14 09:51:42 +08:00
# CHECK: - kind: thumb_bl22
[mach-o] Add parsing of arm/thumb relocations This converts the very complicated mach-o arm relocations into the simple Reference Kinds in lld. The next patch will use the internal Reference kinds to fix up arm/thumb code. llvm-svn: 212306
2014-07-04 08:11:09 +08:00
# CHECK: offset: 12
# CHECK: target: _undef
# CHECK: addend: 4
# CHECK: - kind: thumb_movw_funcRel
# CHECK: offset: 16
# CHECK: target: _x
# CHECK: addend: -42
# CHECK: - kind: thumb_movt_funcRel
# CHECK: offset: 20
# CHECK: target: _x
# CHECK: addend: -42
# CHECK: - kind: thumb_movw_funcRel
# CHECK: offset: 24
# CHECK: target: _x
# CHECK: addend: -34
# CHECK: - kind: thumb_movt_funcRel
# CHECK: offset: 28
# CHECK: target: _x
# CHECK: addend: -34
# CHECK: - kind: thumb_movw_funcRel
# CHECK: offset: 32
# CHECK: target: _t1
# CHECK: addend: -42
# CHECK: - kind: thumb_movt_funcRel
# CHECK: offset: 36
# CHECK: target: _t1
# CHECK: addend: -42
# CHECK: - kind: thumb_movw
# CHECK: offset: 42
# CHECK: target: _x
# CHECK-NOT: addend:
# CHECK: - kind: thumb_movt
# CHECK: offset: 46
# CHECK: target: _x
# CHECK-NOT: addend:
# CHECK: - kind: thumb_movw
# CHECK: offset: 50
# CHECK: target: _x
# CHECK: addend: 8
# CHECK: - kind: thumb_movt
# CHECK: offset: 54
# CHECK: target: _x
# CHECK: addend: 8
# CHECK: - kind: thumb_movw
# CHECK: offset: 58
# CHECK: target: _t1
# CHECK-NOT: addend:
# CHECK: - kind: thumb_movt
# CHECK: offset: 62
# CHECK: target: _t1
# CHECK-NOT: addend:
# CHECK: - kind: thumb_movw
# CHECK: offset: 66
# CHECK: target: _undef
# CHECK-NOT: addend:
# CHECK: - kind: thumb_movt
# CHECK: offset: 70
# CHECK: target: _undef
# CHECK-NOT: addend:
# CHECK: - kind: thumb_movw
# CHECK: offset: 74
# CHECK: target: _undef
# CHECK: addend: 8
# CHECK: - kind: thumb_movt
# CHECK: offset: 78
# CHECK: target: _undef
# CHECK: addend: 8
# CHECK: - name: _t1
# CHECK: content: [ C0, 46 ]
[mach-o] add initial support for modes in arm code. This patch just supports marking ranges that are thumb code (vs arm code). Future patches will mark data and jump table ranges. The ranges are encoded as References with offsetInAtom being the start of the range and the target being the same atom. llvm-svn: 213712
2014-07-23 08:51:37 +08:00
# CHECK: references:
# CHECK: - kind: modeThumbCode
# CHECK: offset: 0
[mach-o] Add parsing of arm/thumb relocations This converts the very complicated mach-o arm relocations into the simple Reference Kinds in lld. The next patch will use the internal Reference kinds to fix up arm/thumb code. llvm-svn: 212306
2014-07-04 08:11:09 +08:00
# CHECK: - name: _foo_arm
# CHECK: references:
[mach-o] add initial support for modes in arm code. This patch just supports marking ranges that are thumb code (vs arm code). Future patches will mark data and jump table ranges. The ranges are encoded as References with offsetInAtom being the start of the range and the target being the same atom. llvm-svn: 213712
2014-07-23 08:51:37 +08:00
# CHECK-NOT: - kind: modeThumbCode
[mach-o] Add Pass to create are shim Atoms for ARM interworking. Arm code has two instruction encodings "thumb" and "arm". When branching from one code encoding to another, you need to use an instruction that switches the instruction mode. Usually the transition only happens at call sites, and the linker can transform a BL instruction in BLX (or vice versa). But if the compiler did a tail call optimization and a function ends with a branch (not branch and link), there is no pc-rel BX instruction. The ShimPass looks for pc-rel B instructions that will need to switch mode. For those cases it synthesizes a shim which does the transition, then modifies the original atom with the B instruction to target to the shim atom. llvm-svn: 219655
2014-10-14 09:51:42 +08:00
# CHECK: - kind: arm_bl24
[mach-o] Add parsing of arm/thumb relocations This converts the very complicated mach-o arm relocations into the simple Reference Kinds in lld. The next patch will use the internal Reference kinds to fix up arm/thumb code. llvm-svn: 212306
2014-07-04 08:11:09 +08:00
# CHECK: offset: 0
# CHECK: target: _x
# CHECK-NOT: addend:
[mach-o] Add Pass to create are shim Atoms for ARM interworking. Arm code has two instruction encodings "thumb" and "arm". When branching from one code encoding to another, you need to use an instruction that switches the instruction mode. Usually the transition only happens at call sites, and the linker can transform a BL instruction in BLX (or vice versa). But if the compiler did a tail call optimization and a function ends with a branch (not branch and link), there is no pc-rel BX instruction. The ShimPass looks for pc-rel B instructions that will need to switch mode. For those cases it synthesizes a shim which does the transition, then modifies the original atom with the B instruction to target to the shim atom. llvm-svn: 219655
2014-10-14 09:51:42 +08:00
# CHECK: - kind: arm_bl24
[mach-o] Add parsing of arm/thumb relocations This converts the very complicated mach-o arm relocations into the simple Reference Kinds in lld. The next patch will use the internal Reference kinds to fix up arm/thumb code. llvm-svn: 212306
2014-07-04 08:11:09 +08:00
# CHECK: offset: 4
# CHECK: target: _x
# CHECK: addend: 4
[mach-o] Add Pass to create are shim Atoms for ARM interworking. Arm code has two instruction encodings "thumb" and "arm". When branching from one code encoding to another, you need to use an instruction that switches the instruction mode. Usually the transition only happens at call sites, and the linker can transform a BL instruction in BLX (or vice versa). But if the compiler did a tail call optimization and a function ends with a branch (not branch and link), there is no pc-rel BX instruction. The ShimPass looks for pc-rel B instructions that will need to switch mode. For those cases it synthesizes a shim which does the transition, then modifies the original atom with the B instruction to target to the shim atom. llvm-svn: 219655
2014-10-14 09:51:42 +08:00
# CHECK: - kind: arm_bl24
[mach-o] Add parsing of arm/thumb relocations This converts the very complicated mach-o arm relocations into the simple Reference Kinds in lld. The next patch will use the internal Reference kinds to fix up arm/thumb code. llvm-svn: 212306
2014-07-04 08:11:09 +08:00
# CHECK: offset: 8
# CHECK: target: _undef
# CHECK-NOT: addend:
[mach-o] Add Pass to create are shim Atoms for ARM interworking. Arm code has two instruction encodings "thumb" and "arm". When branching from one code encoding to another, you need to use an instruction that switches the instruction mode. Usually the transition only happens at call sites, and the linker can transform a BL instruction in BLX (or vice versa). But if the compiler did a tail call optimization and a function ends with a branch (not branch and link), there is no pc-rel BX instruction. The ShimPass looks for pc-rel B instructions that will need to switch mode. For those cases it synthesizes a shim which does the transition, then modifies the original atom with the B instruction to target to the shim atom. llvm-svn: 219655
2014-10-14 09:51:42 +08:00
# CHECK: - kind: arm_bl24
[mach-o] Add parsing of arm/thumb relocations This converts the very complicated mach-o arm relocations into the simple Reference Kinds in lld. The next patch will use the internal Reference kinds to fix up arm/thumb code. llvm-svn: 212306
2014-07-04 08:11:09 +08:00
# CHECK: offset: 12
# CHECK: target: _undef
# CHECK: addend: 4
# CHECK: - kind: arm_movw_funcRel
# CHECK: offset: 16
# CHECK: target: _x
# CHECK: addend: -36
# CHECK: - kind: arm_movt_funcRel
# CHECK: offset: 20
# CHECK: target: _x
# CHECK: addend: -36
# CHECK: - kind: arm_movw_funcRel
# CHECK: offset: 24
# CHECK: target: _x
# CHECK: addend: -28
# CHECK: - kind: arm_movt_funcRel
# CHECK: offset: 28
# CHECK: target: _x
# CHECK: addend: -28
# CHECK: - kind: arm_movw
# CHECK: offset: 36
# CHECK: target: _x
# CHECK-NOT: addend:
# CHECK: - kind: arm_movt
# CHECK: offset: 40
# CHECK: target: _x
# CHECK-NOT: addend:
# CHECK: - kind: arm_movw
# CHECK: offset: 44
# CHECK: target: _x
# CHECK: addend: 8
# CHECK: - kind: arm_movt
# CHECK: offset: 48
# CHECK: target: _x
# CHECK: addend: 8
# CHECK: - kind: arm_movw
# CHECK: offset: 52
# CHECK: target: _undef
# CHECK-NOT: addend:
# CHECK: - kind: arm_movt
# CHECK: offset: 56
# CHECK: target: _undef
# CHECK-NOT: addend:
# CHECK: - kind: arm_movw
# CHECK: offset: 60
# CHECK: target: _undef
# CHECK: addend: 8
# CHECK: - kind: arm_movt
# CHECK: offset: 64
# CHECK: target: _undef
# CHECK: addend: 8
# CHECK: undefined-atoms:
# CHECK: - name: _undef
# .align 2
# .code 16
# .thumb_func _foo_thumb
#_foo_thumb:
# bl _x
# bl _x+4
# bl _undef
# bl _undef+4
# movw r1, :lower16:(_x-L1)
[mach-o] Add Pass to create are shim Atoms for ARM interworking. Arm code has two instruction encodings "thumb" and "arm". When branching from one code encoding to another, you need to use an instruction that switches the instruction mode. Usually the transition only happens at call sites, and the linker can transform a BL instruction in BLX (or vice versa). But if the compiler did a tail call optimization and a function ends with a branch (not branch and link), there is no pc-rel BX instruction. The ShimPass looks for pc-rel B instructions that will need to switch mode. For those cases it synthesizes a shim which does the transition, then modifies the original atom with the B instruction to target to the shim atom. llvm-svn: 219655
2014-10-14 09:51:42 +08:00
# movt r1, :upper16:(_x-L1)
[mach-o] Add parsing of arm/thumb relocations This converts the very complicated mach-o arm relocations into the simple Reference Kinds in lld. The next patch will use the internal Reference kinds to fix up arm/thumb code. llvm-svn: 212306
2014-07-04 08:11:09 +08:00
# movw r2, :lower16:(_x+8-L1)
[mach-o] Add Pass to create are shim Atoms for ARM interworking. Arm code has two instruction encodings "thumb" and "arm". When branching from one code encoding to another, you need to use an instruction that switches the instruction mode. Usually the transition only happens at call sites, and the linker can transform a BL instruction in BLX (or vice versa). But if the compiler did a tail call optimization and a function ends with a branch (not branch and link), there is no pc-rel BX instruction. The ShimPass looks for pc-rel B instructions that will need to switch mode. For those cases it synthesizes a shim which does the transition, then modifies the original atom with the B instruction to target to the shim atom. llvm-svn: 219655
2014-10-14 09:51:42 +08:00
# movt r2, :upper16:(_x+8-L1)
[mach-o] Add parsing of arm/thumb relocations This converts the very complicated mach-o arm relocations into the simple Reference Kinds in lld. The next patch will use the internal Reference kinds to fix up arm/thumb code. llvm-svn: 212306
2014-07-04 08:11:09 +08:00
# movw r1, :lower16:(_t1-L1)
[mach-o] Add Pass to create are shim Atoms for ARM interworking. Arm code has two instruction encodings "thumb" and "arm". When branching from one code encoding to another, you need to use an instruction that switches the instruction mode. Usually the transition only happens at call sites, and the linker can transform a BL instruction in BLX (or vice versa). But if the compiler did a tail call optimization and a function ends with a branch (not branch and link), there is no pc-rel BX instruction. The ShimPass looks for pc-rel B instructions that will need to switch mode. For those cases it synthesizes a shim which does the transition, then modifies the original atom with the B instruction to target to the shim atom. llvm-svn: 219655
2014-10-14 09:51:42 +08:00
# movt r1, :upper16:(_t1-L1)
[mach-o] Add parsing of arm/thumb relocations This converts the very complicated mach-o arm relocations into the simple Reference Kinds in lld. The next patch will use the internal Reference kinds to fix up arm/thumb code. llvm-svn: 212306
2014-07-04 08:11:09 +08:00
# add r1, pc
#L1:
# movw r3, :lower16:_x
# movt r3, :upper16:_x
# movw r4, :lower16:_x+8
# movt r4, :upper16:_x+8
# movw r3, :lower16:_t1
# movt r3, :upper16:_t1
# movw r5, :lower16:_undef
# movt r5, :upper16:_undef
# movw r6, :lower16:_undef+8
# movt r6, :upper16:_undef+8
#
# .thumb_func _t1
#_t1:
# nop
#
#
# .code 32
# .align 2
#_foo_arm:
# bl _x
# bl _x+4
# bl _undef
# bl _undef+4
# movw r1, :lower16:(_x-L2)
[mach-o] Add Pass to create are shim Atoms for ARM interworking. Arm code has two instruction encodings "thumb" and "arm". When branching from one code encoding to another, you need to use an instruction that switches the instruction mode. Usually the transition only happens at call sites, and the linker can transform a BL instruction in BLX (or vice versa). But if the compiler did a tail call optimization and a function ends with a branch (not branch and link), there is no pc-rel BX instruction. The ShimPass looks for pc-rel B instructions that will need to switch mode. For those cases it synthesizes a shim which does the transition, then modifies the original atom with the B instruction to target to the shim atom. llvm-svn: 219655
2014-10-14 09:51:42 +08:00
# movt r1, :upper16:(_x-L2)
[mach-o] Add parsing of arm/thumb relocations This converts the very complicated mach-o arm relocations into the simple Reference Kinds in lld. The next patch will use the internal Reference kinds to fix up arm/thumb code. llvm-svn: 212306
2014-07-04 08:11:09 +08:00
# movw r2, :lower16:(_x+8-L2)
[mach-o] Add Pass to create are shim Atoms for ARM interworking. Arm code has two instruction encodings "thumb" and "arm". When branching from one code encoding to another, you need to use an instruction that switches the instruction mode. Usually the transition only happens at call sites, and the linker can transform a BL instruction in BLX (or vice versa). But if the compiler did a tail call optimization and a function ends with a branch (not branch and link), there is no pc-rel BX instruction. The ShimPass looks for pc-rel B instructions that will need to switch mode. For those cases it synthesizes a shim which does the transition, then modifies the original atom with the B instruction to target to the shim atom. llvm-svn: 219655
2014-10-14 09:51:42 +08:00
# movt r2, :upper16:(_x+8-L2)
[mach-o] Add parsing of arm/thumb relocations This converts the very complicated mach-o arm relocations into the simple Reference Kinds in lld. The next patch will use the internal Reference kinds to fix up arm/thumb code. llvm-svn: 212306
2014-07-04 08:11:09 +08:00
# add r1, pc
#L2:
# movw r3, :lower16:_x
# movt r3, :upper16:_x
# movw r4, :lower16:_x+8
# movt r4, :upper16:_x+8
# movw r5, :lower16:_undef
# movt r5, :upper16:_undef
# movw r6, :lower16:_undef+8
# movt r6, :upper16:_undef+8
#
#
# .data
#_x: .long 0
# .long _foo_thumb
# .long _foo_thumb+4
# .long _undef
# .long _undef+4
# .long _foo_arm - .
# .long _foo_arm+4- .
# .long _foo_thumb - .
# .long _foo_thumb+4 - .
#