forked from OSchip/llvm-project
85 lines
3.1 KiB
TableGen
85 lines
3.1 KiB
TableGen
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//===- ARMCallingConv.td - Calling Conventions for ARM ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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// This describes the calling conventions for ARM architecture.
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//===----------------------------------------------------------------------===//
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/// CCIfSubtarget - Match if the current subtarget has a feature F.
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class CCIfSubtarget<string F, CCAction A>:
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CCIf<!strconcat("State.getTarget().getSubtarget<ARMSubtarget>().", F), A>;
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/// CCIfAlign - Match of the original alignment of the arg
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class CCIfAlign<string Align, CCAction A>:
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CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
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//===----------------------------------------------------------------------===//
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// ARM APCS Calling Convention
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//===----------------------------------------------------------------------===//
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def CC_ARM_APCS : CallingConv<[
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// f64 is passed in pairs of GPRs, possibly split onto the stack
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CCIfType<[f64], CCCustom<"CC_ARM_APCS_Custom_f64">>,
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CCIfType<[f32], CCBitConvertToType<i32>>,
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CCIfType<[i32, f32], CCAssignToReg<[R0, R1, R2, R3]>>,
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CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
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CCIfType<[f64], CCAssignToStack<8, 4>>
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]>;
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def RetCC_ARM_APCS : CallingConv<[
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CCIfType<[f32], CCBitConvertToType<i32>>,
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CCIfType<[f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>,
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CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
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CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
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]>;
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//===----------------------------------------------------------------------===//
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// ARM AAPCS (EABI) Calling Convention
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//===----------------------------------------------------------------------===//
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def CC_ARM_AAPCS : CallingConv<[
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CCIfType<[i8, i16], CCPromoteToType<i32>>,
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// i64/f64 is passed in even pairs of GPRs
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// i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register
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CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>,
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CCIfType<[f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
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CCIfType<[f32], CCBitConvertToType<i32>>,
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CCIfType<[i32, f32], CCAssignToReg<[R0, R1, R2, R3]>>,
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CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
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CCIfType<[f64], CCAssignToStack<8, 8>>
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]>;
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def RetCC_ARM_AAPCS : CallingConv<[
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CCIfType<[f32], CCBitConvertToType<i32>>,
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CCIfType<[f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,
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CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
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CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
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]>;
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//===----------------------------------------------------------------------===//
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// ARM Calling Convention Dispatch
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//===----------------------------------------------------------------------===//
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def CC_ARM : CallingConv<[
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CCIfSubtarget<"isAAPCS_ABI()", CCDelegateTo<CC_ARM_AAPCS>>,
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CCDelegateTo<CC_ARM_APCS>
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]>;
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def RetCC_ARM : CallingConv<[
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CCIfSubtarget<"isAAPCS_ABI()", CCDelegateTo<RetCC_ARM_AAPCS>>,
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CCDelegateTo<RetCC_ARM_APCS>
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]>;
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