2013-08-24 04:39:19 +08:00
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -mattr=+sse4.1 | FileCheck %s
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2011-09-08 16:31:31 +08:00
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2013-07-19 06:47:09 +08:00
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;CHECK-LABEL: vsel_float:
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2011-09-08 16:31:31 +08:00
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;CHECK: blendvps
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;CHECK: ret
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define <4 x float> @vsel_float(<4 x float> %v1, <4 x float> %v2) {
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[X86] Teach how to combine a vselect into a movss/movsd
Add target specific rules for combining vselect dag nodes into movss/movsd
when possible.
If the vector type of the vselect dag node in input is either MVT::v4i13 or
MVT::v4f32, then try to fold according to rules:
1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B)
2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A)
If the vector type of the vselect dag node in input is either MVT::v2i64 or
MVT::v2f64 (and we have SSE2), then try to fold according to rules:
3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B)
4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A)
llvm-svn: 199683
2014-01-21 03:35:22 +08:00
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%vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x float> %v1, <4 x float> %v2
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2011-09-08 16:31:31 +08:00
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ret <4 x float> %vsel
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}
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2013-07-19 06:47:09 +08:00
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;CHECK-LABEL: vsel_4xi8:
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2011-09-14 22:42:15 +08:00
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;CHECK: blendvps
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;CHECK: ret
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define <4 x i8> @vsel_4xi8(<4 x i8> %v1, <4 x i8> %v2) {
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[X86] Teach how to combine a vselect into a movss/movsd
Add target specific rules for combining vselect dag nodes into movss/movsd
when possible.
If the vector type of the vselect dag node in input is either MVT::v4i13 or
MVT::v4f32, then try to fold according to rules:
1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B)
2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A)
If the vector type of the vselect dag node in input is either MVT::v2i64 or
MVT::v2f64 (and we have SSE2), then try to fold according to rules:
3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B)
4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A)
llvm-svn: 199683
2014-01-21 03:35:22 +08:00
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%vsel = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x i8> %v1, <4 x i8> %v2
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2011-09-14 22:42:15 +08:00
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ret <4 x i8> %vsel
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}
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2013-07-19 06:47:09 +08:00
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;CHECK-LABEL: vsel_4xi16:
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2011-09-14 22:42:15 +08:00
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;CHECK: blendvps
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;CHECK: ret
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define <4 x i16> @vsel_4xi16(<4 x i16> %v1, <4 x i16> %v2) {
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[X86] Teach how to combine a vselect into a movss/movsd
Add target specific rules for combining vselect dag nodes into movss/movsd
when possible.
If the vector type of the vselect dag node in input is either MVT::v4i13 or
MVT::v4f32, then try to fold according to rules:
1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B)
2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A)
If the vector type of the vselect dag node in input is either MVT::v2i64 or
MVT::v2f64 (and we have SSE2), then try to fold according to rules:
3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B)
4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A)
llvm-svn: 199683
2014-01-21 03:35:22 +08:00
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%vsel = select <4 x i1> <i1 true, i1 false, i1 true, i1 true>, <4 x i16> %v1, <4 x i16> %v2
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2011-09-14 22:42:15 +08:00
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ret <4 x i16> %vsel
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}
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2013-07-19 06:47:09 +08:00
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;CHECK-LABEL: vsel_i32:
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2011-09-08 16:31:31 +08:00
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;CHECK: blendvps
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;CHECK: ret
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define <4 x i32> @vsel_i32(<4 x i32> %v1, <4 x i32> %v2) {
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[X86] Teach how to combine a vselect into a movss/movsd
Add target specific rules for combining vselect dag nodes into movss/movsd
when possible.
If the vector type of the vselect dag node in input is either MVT::v4i13 or
MVT::v4f32, then try to fold according to rules:
1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B)
2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A)
If the vector type of the vselect dag node in input is either MVT::v2i64 or
MVT::v2f64 (and we have SSE2), then try to fold according to rules:
3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B)
4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A)
llvm-svn: 199683
2014-01-21 03:35:22 +08:00
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%vsel = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x i32> %v1, <4 x i32> %v2
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2011-09-08 16:31:31 +08:00
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ret <4 x i32> %vsel
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}
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2013-07-19 06:47:09 +08:00
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;CHECK-LABEL: vsel_double:
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[X86] Teach how to combine a vselect into a movss/movsd
Add target specific rules for combining vselect dag nodes into movss/movsd
when possible.
If the vector type of the vselect dag node in input is either MVT::v4i13 or
MVT::v4f32, then try to fold according to rules:
1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B)
2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A)
If the vector type of the vselect dag node in input is either MVT::v2i64 or
MVT::v2f64 (and we have SSE2), then try to fold according to rules:
3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B)
4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A)
llvm-svn: 199683
2014-01-21 03:35:22 +08:00
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;CHECK: movsd
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2011-09-08 16:31:31 +08:00
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;CHECK: ret
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define <4 x double> @vsel_double(<4 x double> %v1, <4 x double> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x double> %v1, <4 x double> %v2
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ret <4 x double> %vsel
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}
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2013-07-19 06:47:09 +08:00
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;CHECK-LABEL: vsel_i64:
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[X86] Teach how to combine a vselect into a movss/movsd
Add target specific rules for combining vselect dag nodes into movss/movsd
when possible.
If the vector type of the vselect dag node in input is either MVT::v4i13 or
MVT::v4f32, then try to fold according to rules:
1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B)
2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A)
If the vector type of the vselect dag node in input is either MVT::v2i64 or
MVT::v2f64 (and we have SSE2), then try to fold according to rules:
3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B)
4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A)
llvm-svn: 199683
2014-01-21 03:35:22 +08:00
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;CHECK: movsd
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2011-09-08 16:31:31 +08:00
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;CHECK: ret
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define <4 x i64> @vsel_i64(<4 x i64> %v1, <4 x i64> %v2) {
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%vsel = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i64> %v1, <4 x i64> %v2
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ret <4 x i64> %vsel
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}
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2013-07-19 06:47:09 +08:00
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;CHECK-LABEL: vsel_i8:
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2011-09-08 16:31:31 +08:00
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;CHECK: pblendvb
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;CHECK: ret
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define <16 x i8> @vsel_i8(<16 x i8> %v1, <16 x i8> %v2) {
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%vsel = select <16 x i1> <i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false, i1 true, i1 false, i1 false, i1 false>, <16 x i8> %v1, <16 x i8> %v2
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ret <16 x i8> %vsel
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}
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2011-09-13 03:30:40 +08:00
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;; TEST blend + compares
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; CHECK: A
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define <2 x double> @A(<2 x double> %x, <2 x double> %y) {
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2011-09-13 05:24:07 +08:00
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; CHECK: cmplepd
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2011-09-13 03:30:40 +08:00
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; CHECK: blendvpd
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%max_is_x = fcmp oge <2 x double> %x, %y
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%max = select <2 x i1> %max_is_x, <2 x double> %x, <2 x double> %y
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ret <2 x double> %max
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}
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; CHECK: B
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define <2 x double> @B(<2 x double> %x, <2 x double> %y) {
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2011-09-18 00:49:39 +08:00
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; CHECK: cmpnlepd
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2011-09-13 03:30:40 +08:00
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; CHECK: blendvpd
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2011-09-18 00:49:39 +08:00
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%min_is_x = fcmp ult <2 x double> %x, %y
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%min = select <2 x i1> %min_is_x, <2 x double> %x, <2 x double> %y
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ret <2 x double> %min
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2011-09-13 03:30:40 +08:00
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}
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2011-09-08 16:31:31 +08:00
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2012-04-15 23:08:09 +08:00
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; CHECK: float_crash
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define void @float_crash() nounwind {
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entry:
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%merge205vector_func.i = select <4 x i1> undef, <4 x double> undef, <4 x double> undef
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%extract214vector_func.i = extractelement <4 x double> %merge205vector_func.i, i32 0
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store double %extract214vector_func.i, double addrspace(1)* undef, align 8
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ret void
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}
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