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llvm-project/llvm/test/CodeGen/ARM/armv4.ll

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Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests. llvm-svn: 134590
2011-07-07 11:55:05 +08:00
; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB
; RUN: llc < %s -mtriple=armv4-unknown-eabi -mcpu=strongarm | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -mtriple=armv7-unknown-eabi -mcpu=cortex-a8 | FileCheck %s -check-prefix=THUMB
; RUN: llc < %s -mtriple=armv6-unknown-eabi | FileCheck %s -check-prefix=THUMB
Initial bits of ARMv4-only support. Patch by John Tytgat! llvm-svn: 97886
2010-03-07 03:39:36 +08:00
; RUN: llc < %s -mtriple=armv4-unknown-eabi | FileCheck %s -check-prefix=ARM
; RUN: llc < %s -mtriple=armv4t-unknown-eabi | FileCheck %s -check-prefix=THUMB
Remove the arm_aapcscc marker from the tests. It is the default for the linux targets. llvm-svn: 106029
2010-06-16 03:04:29 +08:00
define i32 @test(i32 %a) nounwind readnone {
Initial bits of ARMv4-only support. Patch by John Tytgat! llvm-svn: 97886
2010-03-07 03:39:36 +08:00
entry:
; ARM: mov pc
; THUMB: bx
ret i32 %a
}