2015-08-01 01:53:38 +08:00
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//===- WebAssemblyInstrControl.td-WebAssembly control-flow ------*- tablegen -*-
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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2018-05-01 23:54:18 +08:00
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/// WebAssembly control-flow code-gen constructs.
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2015-08-01 01:53:38 +08:00
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///
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//===----------------------------------------------------------------------===//
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2015-11-26 03:36:19 +08:00
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let Defs = [ARGUMENTS] in {
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2015-09-17 00:51:30 +08:00
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let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
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2015-12-05 11:03:35 +08:00
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// The condition operand is a boolean value which WebAssembly represents as i32.
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2016-02-09 05:50:13 +08:00
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def BR_IF : I<(outs), (ins bb_op:$dst, I32:$cond),
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2015-12-05 11:03:35 +08:00
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[(brcond I32:$cond, bb:$dst)],
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2016-10-25 04:21:49 +08:00
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"br_if \t$dst, $cond", 0x0d>;
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2015-12-05 11:03:35 +08:00
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let isCodeGenOnly = 1 in
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2016-10-06 05:24:08 +08:00
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def BR_UNLESS : I<(outs), (ins bb_op:$dst, I32:$cond), []>;
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2015-09-17 00:51:30 +08:00
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let isBarrier = 1 in {
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def BR : I<(outs), (ins bb_op:$dst),
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2015-11-06 04:42:30 +08:00
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[(br bb:$dst)],
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2016-10-25 04:21:49 +08:00
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"br \t$dst", 0x0c>;
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2015-09-17 00:51:30 +08:00
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} // isBarrier = 1
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} // isBranch = 1, isTerminator = 1, hasCtrlDep = 1
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2015-12-05 11:03:35 +08:00
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} // Defs = [ARGUMENTS]
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def : Pat<(brcond (i32 (setne I32:$cond, 0)), bb:$dst),
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2016-02-09 05:50:13 +08:00
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(BR_IF bb_op:$dst, I32:$cond)>;
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2015-12-05 11:03:35 +08:00
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def : Pat<(brcond (i32 (seteq I32:$cond, 0)), bb:$dst),
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2016-02-09 05:50:13 +08:00
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(BR_UNLESS bb_op:$dst, I32:$cond)>;
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2015-12-05 11:03:35 +08:00
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let Defs = [ARGUMENTS] in {
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2015-09-17 00:51:30 +08:00
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// TODO: SelectionDAG's lowering insists on using a pointer as the index for
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2016-03-08 11:18:12 +08:00
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// jump tables, so in practice we don't ever use BR_TABLE_I64 in wasm32 mode
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2015-09-17 00:51:30 +08:00
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// currently.
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2016-01-12 09:45:12 +08:00
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// Set TSFlags{0} to 1 to indicate that the variable_ops are immediates.
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2016-01-13 04:30:51 +08:00
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// Set TSFlags{1} to 1 to indicate that the immediates represent labels.
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2015-09-17 00:51:30 +08:00
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let isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
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2016-03-08 11:18:12 +08:00
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def BR_TABLE_I32 : I<(outs), (ins I32:$index, variable_ops),
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[(WebAssemblybr_table I32:$index)],
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2016-10-25 04:21:49 +08:00
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"br_table \t$index", 0x0e> {
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2016-01-12 09:45:12 +08:00
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let TSFlags{0} = 1;
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2016-01-13 04:30:51 +08:00
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let TSFlags{1} = 1;
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2016-01-12 09:45:12 +08:00
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}
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2016-03-08 11:18:12 +08:00
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def BR_TABLE_I64 : I<(outs), (ins I64:$index, variable_ops),
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[(WebAssemblybr_table I64:$index)],
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"br_table \t$index"> {
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2016-01-12 09:45:12 +08:00
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let TSFlags{0} = 1;
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2016-01-13 04:30:51 +08:00
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let TSFlags{1} = 1;
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2016-01-12 09:45:12 +08:00
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}
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2015-09-17 00:51:30 +08:00
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} // isTerminator = 1, hasCtrlDep = 1, isBarrier = 1
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2018-05-11 06:16:44 +08:00
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// This is technically a control-flow instruction, since all it affects is the
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// IP.
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def NOP : I<(outs), (ins), [], "nop", 0x01>;
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2018-03-02 09:03:40 +08:00
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// Placemarkers to indicate the start or end of a block or loop scope.
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2017-06-30 08:43:15 +08:00
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// These use/clobber VALUE_STACK to prevent them from being moved into the
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// middle of an expression tree.
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2016-10-04 06:43:53 +08:00
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let Uses = [VALUE_STACK], Defs = [VALUE_STACK] in {
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2016-10-25 04:21:49 +08:00
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def BLOCK : I<(outs), (ins Signature:$sig), [], "block \t$sig", 0x02>;
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def LOOP : I<(outs), (ins Signature:$sig), [], "loop \t$sig", 0x03>;
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2016-10-25 04:32:04 +08:00
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2018-03-02 09:03:40 +08:00
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// END_BLOCK, END_LOOP, and END_FUNCTION are represented with the same opcode in
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// wasm.
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2016-10-25 07:27:49 +08:00
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def END_BLOCK : I<(outs), (ins), [], "end_block", 0x0b>;
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def END_LOOP : I<(outs), (ins), [], "end_loop", 0x0b>;
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2017-02-25 07:18:00 +08:00
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let isTerminator = 1, isBarrier = 1 in
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def END_FUNCTION : I<(outs), (ins), [], "end_function", 0x0b>;
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2016-10-04 06:43:53 +08:00
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} // Uses = [VALUE_STACK], Defs = [VALUE_STACK]
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2015-09-17 00:51:30 +08:00
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2015-08-01 12:48:44 +08:00
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multiclass RETURN<WebAssemblyRegClass vt> {
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2015-11-06 04:42:30 +08:00
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def RETURN_#vt : I<(outs), (ins vt:$val), [(WebAssemblyreturn vt:$val)],
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2016-10-25 07:27:49 +08:00
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"return \t$val", 0x0f>;
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2016-05-21 08:21:56 +08:00
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// Equivalent to RETURN_#vt, for use at the end of a function when wasm
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// semantics return by falling off the end of the block.
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let isCodeGenOnly = 1 in
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def FALLTHROUGH_RETURN_#vt : I<(outs), (ins vt:$val), []>;
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2015-08-01 12:48:44 +08:00
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}
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2015-11-10 08:30:57 +08:00
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2016-08-03 07:16:09 +08:00
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multiclass SIMD_RETURN<ValueType vt> {
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def RETURN_#vt : SIMD_I<(outs), (ins V128:$val),
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[(WebAssemblyreturn (vt V128:$val))],
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2016-10-25 07:27:49 +08:00
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"return \t$val", 0x0f>;
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2016-08-03 07:16:09 +08:00
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// Equivalent to RETURN_#vt, for use at the end of a function when wasm
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// semantics return by falling off the end of the block.
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let isCodeGenOnly = 1 in
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def FALLTHROUGH_RETURN_#vt : SIMD_I<(outs), (ins V128:$val), []>;
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}
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2015-11-10 08:30:57 +08:00
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let isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
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2016-10-04 05:33:09 +08:00
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2015-11-10 08:30:57 +08:00
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let isReturn = 1 in {
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2015-09-26 09:09:44 +08:00
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defm : RETURN<I32>;
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defm : RETURN<I64>;
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defm : RETURN<F32>;
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defm : RETURN<F64>;
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2018-03-08 12:05:37 +08:00
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defm : RETURN<EXCEPT_REF>;
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2016-08-03 07:16:09 +08:00
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defm : SIMD_RETURN<v16i8>;
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defm : SIMD_RETURN<v8i16>;
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defm : SIMD_RETURN<v4i32>;
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defm : SIMD_RETURN<v4f32>;
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2016-10-25 07:27:49 +08:00
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def RETURN_VOID : I<(outs), (ins), [(WebAssemblyreturn)], "return", 0x0f>;
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2016-05-21 08:21:56 +08:00
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// This is to RETURN_VOID what FALLTHROUGH_RETURN_#vt is to RETURN_#vt.
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let isCodeGenOnly = 1 in
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def FALLTHROUGH_RETURN_VOID : I<(outs), (ins), []>;
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2015-11-10 08:30:57 +08:00
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} // isReturn = 1
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2016-10-04 05:33:09 +08:00
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2016-10-25 07:27:49 +08:00
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def UNREACHABLE : I<(outs), (ins), [(trap)], "unreachable", 0x00>;
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2018-03-02 09:03:40 +08:00
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} // isTerminator = 1, hasCtrlDep = 1, isBarrier = 1
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2016-10-04 05:33:09 +08:00
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2018-03-02 09:03:40 +08:00
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//===----------------------------------------------------------------------===//
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// Exception handling instructions
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//===----------------------------------------------------------------------===//
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// Throwing an exception: throw / rethrow
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let isTerminator = 1, hasCtrlDep = 1, isBarrier = 1 in {
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def THROW_I32 : I<(outs), (ins i32imm:$tag, I32:$val),
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[(int_wasm_throw imm:$tag, I32:$val)], "throw \t$tag, $val",
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2017-06-30 08:43:15 +08:00
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0x08>;
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2018-03-02 09:03:40 +08:00
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def THROW_I64 : I<(outs), (ins i32imm:$tag, I64:$val),
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[(int_wasm_throw imm:$tag, I64:$val)], "throw \t$tag, $val",
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2017-06-30 08:43:15 +08:00
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0x08>;
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def RETHROW : I<(outs), (ins i32imm:$rel_depth), [], "rethrow \t$rel_depth",
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0x09>;
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2015-11-10 08:30:57 +08:00
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} // isTerminator = 1, hasCtrlDep = 1, isBarrier = 1
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2015-11-26 03:36:19 +08:00
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2018-03-02 09:03:40 +08:00
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// Region within which an exception is caught: try / end_try
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let Uses = [VALUE_STACK], Defs = [VALUE_STACK] in {
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def TRY : I<(outs), (ins Signature:$sig), [], "try \t$sig", 0x06>;
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def END_TRY : I<(outs), (ins), [], "end_try", 0x0b>;
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} // Uses = [VALUE_STACK], Defs = [VALUE_STACK]
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[WebAssembly] Support instruction selection for catching exceptions
Summary:
This lowers exception catching-related instructions:
1. Lowers `wasm.catch` intrinsic to `catch` instruction
2. Removes `catchpad` and `cleanuppad` instructions; they are not
necessary after isel phase. (`MachineBasicBlock::isEHFuncletEntry()` or
`MachineBasicBlock::isEHPad()` can be used instead.)
3. Lowers `catchret` and `cleanupret` instructions to pseudo `catchret`
and `cleanupret` instructions in isel, which will be replaced with other
instructions in `WebAssemblyExceptionPrepare` pass.
4. Adds 'WebAssemblyExceptionPrepare` pass, which is for running various
transformation for EH. Currently this pass only replaces `catchret` and
`cleanupret` instructions into appropriate wasm instructions to make
this patch successfully run until the end.
Currently this does not handle lowering of intrinsics related to LSDA
info generation (`wasm.landingpad.index` and `wasm.lsda`), because they
cannot be tested without implementing `EHStreamer`'s wasm-specific
handlers. They are marked as TODO, which is needed to make isel pass.
Also this does not generate `try` and `end_try` markers yet, which will
be handled in later patches.
This patch is based on the first wasm EH proposal.
(https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md)
Reviewers: dschuff, majnemer
Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D44090
llvm-svn: 333705
2018-06-01 06:25:54 +08:00
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// Catching an exception: catch / catch_all
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let hasCtrlDep = 1 in {
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def CATCH_I32 : I<(outs I32:$dst), (ins i32imm:$tag),
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[(set I32:$dst, (int_wasm_catch imm:$tag))],
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"i32.catch \t$dst, $tag", 0x07>;
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def CATCH_I64 : I<(outs I64:$dst), (ins i32imm:$tag),
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[(set I64:$dst, (int_wasm_catch imm:$tag))],
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"i64.catch \t$dst, $tag", 0x07>;
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def CATCH_ALL : I<(outs), (ins), [], "catch_all", 0x05>;
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}
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2017-06-30 08:43:15 +08:00
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[WebAssembly] Support instruction selection for catching exceptions
Summary:
This lowers exception catching-related instructions:
1. Lowers `wasm.catch` intrinsic to `catch` instruction
2. Removes `catchpad` and `cleanuppad` instructions; they are not
necessary after isel phase. (`MachineBasicBlock::isEHFuncletEntry()` or
`MachineBasicBlock::isEHPad()` can be used instead.)
3. Lowers `catchret` and `cleanupret` instructions to pseudo `catchret`
and `cleanupret` instructions in isel, which will be replaced with other
instructions in `WebAssemblyExceptionPrepare` pass.
4. Adds 'WebAssemblyExceptionPrepare` pass, which is for running various
transformation for EH. Currently this pass only replaces `catchret` and
`cleanupret` instructions into appropriate wasm instructions to make
this patch successfully run until the end.
Currently this does not handle lowering of intrinsics related to LSDA
info generation (`wasm.landingpad.index` and `wasm.lsda`), because they
cannot be tested without implementing `EHStreamer`'s wasm-specific
handlers. They are marked as TODO, which is needed to make isel pass.
Also this does not generate `try` and `end_try` markers yet, which will
be handled in later patches.
This patch is based on the first wasm EH proposal.
(https://github.com/WebAssembly/exception-handling/blob/master/proposals/Exceptions.md)
Reviewers: dschuff, majnemer
Subscribers: jfb, sbc100, jgravelle-google, sunfish, llvm-commits
Differential Revision: https://reviews.llvm.org/D44090
llvm-svn: 333705
2018-06-01 06:25:54 +08:00
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// Pseudo instructions: cleanupret / catchret
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// They are not return instructions in wasm, but setting 'isReturn' to true as
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// in X86 is necessary for computing funclet membership.
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let isTerminator = 1, hasSideEffects = 1, isBarrier = 1, hasCtrlDep = 1,
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isCodeGenOnly = 1, isReturn = 1 in {
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def CLEANUPRET : I<(outs), (ins), [(cleanupret)], "", 0>;
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def CATCHRET : I<(outs), (ins bb_op:$dst, bb_op:$from),
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[(catchret bb:$dst, bb:$from)], "", 0>;
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}
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} // Defs = [ARGUMENTS]
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